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S27: Advanced Substrate/PCB Process and Manufacturing

Oct. 28, 2022 13:30 PM - 15:30 PM

Room: 504c
Session chair: Shu Huang, Division Director,ITRI / John Liu, Consultant, TPCA

IPC Test Method Standard - Measuring High Frequency Signal Loss and Propagation on Printed Boards with Frequency Domain Methods
發表編號:S27-1時間:13:30 - 14:00

Invited Speaker

Jimmy Hsu, Principal Engineer, Intel

- Background
- De-embedding challenges and the Eigen-value based de-embedding methodology
- Probing Solutions
- Accurate reporting of insertion loss performance by physics-based fitting
- Addressing the Quality of Reported Insertion Loss
- Environmental Impact on Insertion Loss
- Summary


 
RDL Copper Plating Process for Panel Level Packaging Application
發表編號:S27-2時間:14:00 - 14:15

論文編號:US0016
Maddux Sy, Sean Fleuriel, Confesol Rodriguez, Kesheng Feng

ABSTRACT
Advanced packaging suppliers are having two primary challenges during IC substrate fabrication, meeting the requirements on copper plating performance and reducing the cost from manufacturing process. The requirements on plating performance include both high resolution and strict height uniformity within a die (WID) and within a panel (WIP), consistent deposit grain structure and great copper physical properties to meet reliability requirements. The plated features include fine lines, trenches and vias, whose top shape and coplanarity are critical to the product quality. A non-planar surface could result in signal transmission loss and introduce weak points in the connections. Therefore, copper plating solutions providing uniform, planar structures, without any special post treatment are highly desirable features from RDL plating processes. The copper plating solution can also reduce cost by plating two or three types of features in a single electrolyte, this flexibility allows fabricators to save on space and equipment
In this paper, an electroplating package, Systek UVF 200, is introduced to plate RDL under different current densities in vertical continuous platers (VCP) or high-speed panel plater. The plating uniformity and coplanarity of both RDL fine lines and vias was evaluated on a panel level.
The Systek UVF 200 package offered excellent coplanarity within a pattern unit or die for RDL plating. The variation in the plated height (or thickness) between fine lines, as low as 9 µm in width, and pads, was below 2.0 µm when using a current density below 3.0 ASD to obtain the plated copper thickness around 12 µm. For 14 µm wide lines, the plated copper thickness variation can be below 1.0 µm. Under higher plating CD, such as 4-6 ASD, the plating thickness variation can be below 2.0 µm. The variation of plated thickness across 510 mm x 515 mm panels was below 10%. The tops of the fine lines have defined, slightly domed shapes, these types of profiles have excellent conductivity.
Physical properties of the plated copper deposit are essential for the reliability of the finished product. A few key physical properties are tensile strength, elongation %, and internal stress. These properties show the tolerance of the deposit for thermal stress and warpage. The additives (wetter, brightener, and leveler) strongly influence the physical properties of the deposit. Copper deposited with the Systek UVF 200 package has tensile strength above 40,000 psi, elongation % above 18%, and internal stress below 1.0 Kg/mm2. The physical properties of the deposited copper did not change considerably during the bath aging, showing that the package has stable performance.


 
Printed Circuit Board (PCB) Routing Optimization with an Innovative Edge Connector for PCI-Express 5.0 and Beyond
發表編號:S27-3時間:14:15 - 14:30

論文編號:AS0033
Huafang Ju, Xiang Li, Jimmy Hsu, Shaohua Li, Thonas Su, Mo Liu, Kai Xiao

PCI-Express (PCIe) data rate continues to double generation by generation from Gen4 with 16Gbps, Gen5 with 32Gbps to Gen6 with 64Gbps in recent years. However, data center motherboard form factor and landing zone requirement remain the same, which implies all enablers in channel need be improved to meet the maximized board routing length. PCB and connector are important components in channel, in addition to perspective performance, board designers should also pay attention to connector pin field PCB footprint design, which can cause full channel solution space variation and PCB cost difference.
Surface Mount Technology (SMT) connectors are adopted for PCIe Gen5 to enhance the electrical performance, different from Plating Through Hole (PTH) connectors, SMT sits on PCB pad by reflow soldering, and the pin side lead-in/break-out has two routing directions: toe side entry from front of the pin contact and heel side entry from back of pin contact. The two options of footprint routing entry cause different pin-pad stub length because the bifurcation point between connector pin and PCB pad is not in the middle of the rectangular pad. Toe routing with shorter pin-pad stub is recommended. Heel routing led to the longer stub degrading channel solution space significantly.

The heel routing cannot be completely avoided in some designs where the connector must be placed on very edge of a board because of routing density, mechanical limitation, or other reasons, which implies the board space is not sufficient for toe routing. It usually occurs on some high-density baseboards, riser cards or Graphics Processing Unit (GPU) switch boards.

Two approaches are proposed in this paper to mitigate these longer stub design issues. The first is to apply PCB via in pad plating over (VIPPO) process to reduce the routing stub. The other is to adopt an innovative connector with a row of pins flipped to have the heel entry flipped to toe entry without routing direction changing.

In this study, PCIe Gen5 card electro-mechanical (CEM) connector is addressed as an example, and full channel simulation based on two connector riser topology shows that the reduction is greater than 10% on eye height and eye width with heel entry compared to toe entry. VIPPO and new innovative connectors are also analyzed in this channel and the two approaches show comparable electrical performance with toe routing. In terms of cost, VIPPO has about 7% PCB cost added by complex manufacture process, and there is no additional cost increase by adopting innovative connectors as a satisfactory solution, which has already been manufactured by two connector suppliers. PCB design optimization was conducted for SMT connector to meet this high-frequency connector design up to 32GT/s.



 
The inventive adhesion promoter system for ultra-fine line package substrates
發表編號:S27-4時間:14:30 - 14:45

論文編號:EU0119
Thomas Thomas, Christopher A. Seidemann, Wonjin Cho, Cedric Lin, Patrick Brooks

To ensure good adhesion between conductor tracks and dielectrics is very essential in package substrates manufacturing. Currently, surface roughening process is the predominant method for bonding enhancement, due to providing a strong mechanical interlocking between roughened conductor tracks and dielectrics. Driven by increase of design complexity and growing demand for high I/O in package substrates, the dimension of conductor tracks L/S is reduced gradually to 5/5 µm L/S and lower. The conventional approach to ensure good adhesion by only rely on mechanical anchoring is no longer suitable. Excessive etching of conductor tracks from the roughening process has detrimental effect on the line integrity, hence creates inevitable functional failure. A new way of bonding enhancement process needs to be developed, and this must be independent from the surface roughness. For this reason, various processes have been developed with organosilane as adhesion promoter, where a synergy of mechanical and chemical bonding occurs to improve bonding strength and thermal reliability. Nonetheless, introduction of organosilane on conductor surface prior to polymeric material lamination has failed to provide good resistance to thermal shock and chemical leaching. This work focuses on the development of a novel organic pre-coating prior to organosilane adhesion promoter to improve thermal shock and chemical resistance property of the interface, without negative consequence to the adhesion performance. Several surface analytical methods are used to derive the presence of nano structure and adhesion molecules on the conductor surface such as AFM, FESEM and FTIR. With the suitable chemical entity and concentration of organic pre-coating on the surface, the resistance against thermal shock and chemical leaching are significantly improved. A unique zero conductor line width reduction of the process is very suitable for ultra-fine line < 5/5 µm L/S package substrates manufacturing.


 
A Methodology to Resize the PCB Differential Pair Routing Automatically
發表編號:S27-5時間:14:45 - 15:00

論文編號:TW0021
Ian Chu

This paper describes and discusses the method used in the differential pair line layout of the printed circuit board (PCB) to resize its width and spacing when PCB stack-up type or material is required to change.

Formerly, while developing differential pair circuits of PCB there always came along with sudden requests to change PCB stack-up type, material, or the number of layers.

In the realization of these kinds of requests there are many problems encountered, which resulted in a lot of time spent by layout engineers to remove and reroute differential pairs manually.

To resolve the problems mentioned above, we devise a method named reference polygon. Comparing it with popular industrial layout tools, this reference polygon method not only has an intuitive operation to layout engineers who are asked to realize the requested values of impedance in each layer but also has a unique design, especially in resolving arbitrary degrees and serpentine line routing.

Keywords: PCB stack-up, Differential Pair, Reference Polygon


 
A robust collaborative demand fulfillment framework for demand planning and production planning to empower smart production in printed circuit board industry
發表編號:S27-6時間:15:00 - 15:15

論文編號:TW0095
Hsuan An Kuo

The global economic boom of automotive market has been starting to recover optimistically from COVID-19. The market recovery of automotive chip demand is expected to grow with high demand and cross among all regions including customer behavior, business revenue, and numerous aspects of corporate operations. The advanced technologies including cloud computing, artificial intelligence (AI), big data analytics, and Cyber Physical System (CPS) boost the technology diffusion of intellectual devices and automotive electronics, enhancing the demand of PCB products. It becomes an important issue for players in the supply chain to adopt the technology migration of embedded power printed circuit board (PCB) technology in PCB industry with a robust solution framework. Facing the dynamic global market, companies have to ensure the production planning decisions is capable of fulfilling customer demand on time to achieve higher profitability and competitiveness. With the shortening product life cycle and increasing supply chain complexity, it becomes a great challenge to derive an accurate forecast result. The overestimate of the demand results in the waste of the capacity costs and work-in-process (WIP) costs, while the underestimate of the demand decreases the customer satisfaction and revenue. To deal with the risk of oversupply, shortage and production costs from the forecast bias, this study proposed a collaborated decision framework that considers both demand forecasting and robust production planning model for production system resilience. For demand forecasting, this study incorporated statistical and computational intelligence forecast methods, which the inherent and non-stationary characteristics of the time series data can be captured by the proposed forecast model including autoregressive integrated moving average (ARIMA), exponential smoothing (ETS), long short term memory (LSTM) and support vector regression (SVR) as a combinational method for demand forecast. Based on the results from forecasted demand with related forecasted errors in the rolling planning horizon, both additive and multiplicative Martingale Model of Forecast Evolution (MMFE) are applied to adjust forecasted demand and generate a more accurate demand realization threshold as the input for robust optimization model. The robust optimization production planning model aims to minimize the risk of backlog costs, WIP costs and inventory costs in production planning. For validation, considering realistic demand scenarios, the study constructs a multi-paradigm simulation model to investigate the performance of the proposed approach with conventional solutions. Based on empirical scenarios, practical viability of the proposed approach was validated. The results have shown robustness and practical viability for the proposed model under demand uncertainty.


 
Environment-adaptable Printed-circuit Board Positioning using Deep Reinforcement Learning
發表編號:S27-7時間:15:15 - 15:30

論文編號:TW0020
Carlos Solorzano, Du-Ming Tsai

The Printed-Circuit Boards (PCB) industry has held one of the most advanced manufacturing technologies, as the size of electronic components tends to decrease. Visual inspection for quality control and automatic assembly are key to improve efficiency in manufacturing. Alignment or positioning is only the first stage in a manufacturing line for assembly or visual inspection tasks. A precise and fast object positioning can ensure the successful visual inspection between a test image and a golden reference image. Vision-based techniques and methods are commonly used in the industry for assembly and inspection tasks. Many methods have been proposed to tackle the problem, either by traditional machine vision or by deep learning techniques. The traditional machine vision methods rely on template matching or feature point correspondence. They are computationally intensive and are easily affected by illumination changes and noise. Deep learning models such as Convolutional Neural Networks (CNN) are computationally very efficient but are also sensitive against environmental changes. They need to be trained with all possible environmental conditions or scenarios. Samples must be collected manually, as some samples can not be simply augmented digitally. Synthesized lightning variations are generally linear, but real lightning changes are non-linear and dynamic. In this article, a deep Reinforcement Learning (RL) model based on the Actor-Critic style Proximal Policy Optimization (AC-PPO) algorithm is proposed. The proposed method is applied for the positioning of Printed Circuit Boards (PCB) in images. The model uses as the current environment the input sensed image and the reference template as a guide. It requires only a single manually marked template in the reference image. All possible training images are automatically and randomly generated during the neural network training without human intervention. The model outputs the estimated geometric transformation parameters of the input sensed image. The proposed RL model is shown to be adaptive to unseen environmental changes or conditions, including illumination, noise, de-focusing and template occlusion, compared with the CNN regressor. Experimental results indicate that the proposed model on average can achieve estimation errors less than 1 pixel in translation and 1° in orientation measurement, with fast evaluation for the real-time PCB positioning task.


 


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Co-hosting Event - TPCA Show 2022