Oral Sessions

The packaging of the processor and memory closed together on one substrate is evident in the AI server packaging such as Nvidia H100. Where GPU is connected to six HBM3s on a CoWoS substrate. AMD I300 has eight HBMs. Processers with 12 or 16 HBM are expected in the future; this requires a high-density and big-area substrate. The challenges for AI substrates are fine line, yield, and flatness as substrate size and wiring density increase.
The conventional substrate is symmetrically built, and more than ten layers of ABF on each side can be built. However, most fine line interconnections need to be placed close to the chip side; the ABF routing capability on the PCB side can be used only through the substrate core, which is not electrically desirable.
A better way is to move more ABF layers from the bottom side of the core to the top side and put fine line capability to the chip side. This asymmetric structure is substrate 2.0.
In this talk, we shall show processes to solve the warpage of the high layer counts of the asymmetric structure of substrate 2.0 and empower the substrate with fine-line capabilities. The warpage along the 20x20mm TV is only +/-3um.

Bio:
Dr. Dyi-Chung Hu is a world-renowned expert in semiconduction advanced electronic packaging. He has also pioneered Taiwan’s electronic packaging and TFT LCD display industry. He earned Ph. D. degree from MIT in Material Science and Engineering Department.
He joined IBM East Fishkill to develop thin film MCM substrate for high-performance computers. In 1990, he returned to Taiwan and became Professor at National Chao Tung University. Later, he joined Industry Research Organization in Taiwan to pioneer the development of wafer bumping, TAB, and COG processes for TFT LCD displays. He has been one of the pioneers in creating the Taiwan TFT LCD industry and cofounder of two Taiwanese TFT LCD Companies, E-Ink and HannStar Co. He serves as founding committee chairman of SEMICON Taiwan in electronic packaging. From 2010 to 2014, he is the Senior VP of RD at Unimicron. He set up and managed the advanced IC substrate development. In 2014, he founded a system integration company, SiPlus Co. In SiPlus, he has developed 2.0D, 2.1D, 2.2D, and 2.3D integrated substrate structures and processes for semiconductor heterogeneous integration.
He has many invited speeches in advanced substrate and packaging development worldwide. He has been regarded as the world’s leading expert in advanced electronic packaging.
Dr. Hu has contributed substantially to Taiwan semiconductor packaging, TFT LCD display, and substrate development and manufacture. He has over 100 patents in the above fields.

 

As a material with good electrical conductivity and low cost, copper has been widely used in different kinds of electronic devices. With the continuous advancement of electronic devices, copper foils in various scales with outstanding mechanical properties are in need. Maintaining the mechanical properties of copper foils while changing the thickness might be an interesting issue.
Alloys have always been an intuitive way to strengthen metals, but it can also drastically affect conductivity while strengthening. Therefore, our team is still committed to improving the mechanical properties and strength of pure electroplated copper foils by proper additives and electroplating parameters. By manipulate different electroplating parameters, we can product nanotwinned copper foil with different microstructures included columnar grains and fine grains.
The UTS (Ultimate tensile strength) and YS (Yield strength) of copper foil often decreases while the thickness increases, which grainsize is around tens to hundreds of micrometers. [1]
In this study, the nanotwinned copper foil with columnar grains show better resistance against the size effect on UTS and YS. Thickness ranges from 5 μm to 30 μm were adjusted to observe the difference in mechanical property against the size effect. The UTS decreases 18% and YS decreases 23% in the fine grain nanotwinned copper foil. The UTS decreases 6% and YS decreases 8% in the columnar grain nanotwinned copper foil, which show better resistance against size effectobviously.

 

Direct Cu/Cu bonding and dielectric/dielectric bonding plays a vital role in advanced packaging due to the surge of 3D integration, and the combination of Cu and dielectric to realize fine pitch hybrid bonding is the new trend. The primary challenge of direct bonding is to reduce the thermal budget while maintaining its bonding strength. Previous studies have shown that <111>-oriented nanotwinned copper films and SiCN dielectrics are possible candidates to address this limitation. By using NT-Cu for direct Cu/Cu bonding, the bonding temperature can be lowered to 150 °C owing to its highly surface diffusivity on the (111) plane. Moreover, SiCN was found to have better bonding strength compared to SiO2 under same bonding temperature as it can form more dangling bonds after plasma treatment. In this study, we aim to analyze the difference of using Ar plasma and N2 plasma on NT-Cu and SiCN films respectively. The activation process was then conducted under various conditions to find a compatible
condition for both NT-Cu/NT-Cu and SiCN/SiCN bonding.

Highly <111>-oriented NT-Cu films were fabricated through the process of electroplating, followed by citric acid cleaning and chemical mechanical polishing (CMP). SiCN films were fabricated by PECVD and the planarization of SiCN films are also realized by CMP with an amino-based slurry. AFM results show that the roughness of SiCN films can be lower to about 0.1 nm, which is crucial for dielectric bonding. Afterwards, surface activation of the films is achieved by using Ar plasma and N2 plasma under different conditions. Surface analysis isthen conducted. Roughness was further examined by AFM and surface wettability was studied by contact angle. After N2 plasma treatment, the contact angle of SiCN surface can be lowered from 61.3 degree to less than 5 degree. This shows that the surface becomes more hydrophilic which is beneficial for dielectric bonding. Finally, XPS analysis was conducted to study the surface chemical states.

After surface activation, NT-Cu / NT-Cu and SiCN / SiCN films were transferred to the bonding process at 150°C immediately. Then, the quality of bonding interfaces was examined using scanning acoustic microscopy (SAM), transmission electron microscopy (TEM), and Focus Ion Beam (FIB). It is worth notice that an oxide layer was found at the SiCN bonding interface. Additionally, bonding strength was later evaluated.

It has been demonstrated that direct bonding of NT-Cu/NT-Cu and SiCN/SiCN can be realized at 150 °C without damaging the surface of NT-Cu meanwhile lowering the bonding temperature of SiCN. Moreover, our result shows the prospect of utilizing NT-Cu and SiCN in hybrid bonding with the help of plasma activation.

 

With the increasing demand on the high-performance computing (HPC), downscaling of electronic devices are sought after. Fabricating the chips with higher I/O number and transistor numbers in per unit volume, despite facing with various challenges, is an inevitable path. Comparing to the methods such as system-on-chip (SOC), fabricate chips in three dimensional (3D-IC) is a relatively inexpensive approach. More important, 3D-IC possesses the flexibility on the heterogeneous integration with different chip sizes and node technologies. Thus, 3D-IC is already on the road of R&D and production.
Vertical stacking is the primary concept of 3D-IC. For instance, flip chip utilizes solder bumps to connect the chip and PCB. Despite solder can be used for vertical stacking, they collapse in fine pitch (<10 μm) and result in severe reliability issues and low production yield. Cu-Cu bonding is currently a critical technology utilized in 3D-IC. They possess advantages such as low electrical resistivity and high electromigration resistance. However, the thermal budget is the vital concern for such method. Normally speaking, the Cu-Cu joints require to be bonded at 400 ℃ for 1 h for the good bonding quality, owing to its high melting point. It could be harmful for most of the electronic components. Low Cu-Cu bonding temperature can be achieved by various methods such as surface activated bonding (SAB), surface passivation and utilization of (111) Cu surface. Because the Cu has face-centered cubic structure, the (111) plane has the largest surface diffusivity among others. We have demonstrated that using highly (111)-oriented nanotwinned Cu (NT-Cu), the bonding temperature can be reduced to 200 ℃ in 30 min.
More research has pointed out that the remaining bonding interface could be the potential fracture site. On the other hand, if the bonding interface is eliminated, the reliability can be improved significantly. Therefore, eliminating the bonding interface of Cu-Cu joints is essential to consider. It has been shown that the thermal stability of Cu is related to whether the interface can be eliminated. In this study, we investigate the thermal stability of fine pitch damascene NT-Cu vias. By adjusting the electroplating parameters, the NT-Cu vias can occur grain growth low to 200 ℃. The grain size of the Cu vias increases from 0.15 μm to ~8 μm after annealing. This result shows that the Cu-Cu joints could become a single Cu grain using NT-Cu for bonding.

 

This study presents a comprehensive analysis of stress distribution in the Cu/SiO2 hybrid joints during bonding processes and thermal cycling tests (TCT) using the finite element method (FEM) and microbeam diffraction provided by the National Synchrotron Radiation Research Center (NSRRC).
Microbeam diffraction experiments were conducted using synchrotron radiation to achieve high resolution, enabling observation of joint stress distribution at a scale of approximately 10 μm. Measurements were taken at temperatures of 27°C, 100°C, 150°C, and 200°C to assess the stress and strain behavior of the bonded joint. The coefficient of thermal expansion (CTE) mismatch between the Cu pad and SiO2 was determined to be approximately 12 ppm/K. Additionally, the experiments revealed an uneven stress distribution in the bonded joint, with higher compressive stress observed in the center compared to the sides.
FEM simulation was employed to analyze the stress distribution. A three-layer joint simulation model with dimensions of 10 μm - 8 μm - 12 μm was utilized, considering periodic boundary conditions. Simulations of the top die (10 μm) and bottom die (8 μm + 12 μm) at different temperatures showed Cu protrusions ranging from 2 to 4 nm. Decreasing the Cu pad diameter in the simulations resulted in smaller Cu protrusions, emphasizing the importance of surface flatness control during chemical mechanical polishing (CMP) as joint sizes decrease. The simulations aligned with previous successful bonding experiences, highlighting the critical role of limiting Cu surface dishing to under 4 nm to avoid failure.
Subsequent simulations were conducted on the top and bottom dies both with a 3 nm Cu surface dishing, assuming completion of the SiO2-SiO2 pre-bonding stage. At the process condition of a post-annealing temperature of 200°C without applying external forces, the simulations revealed an inability to effectively close the gap between the Cu pad surfaces. It may be caused by the absence of plastic deformation and interfacial diffusion mechanisms in the FEM simulation model.
Finally, TCT simulations were conducted on the bonded joint, considering initial stress. The simulated average stress matched microbeam diffraction results, enabling accurate prediction of average stress magnitudes. The simulations also identified locations of stress concentration both in tension and compression during the TCT process, aligning with void formation observed in the experiments.
In conclusion, this study combines FEM simulation and microbeam diffraction analysis to investigate stress distribution in the Cu/SiO2 hybrid joint during the bonding processes and TCT. The results reveal valuable insights into bonding behavior and failure mechanisms, underscoring the significance of CTE mismatch, surface flatness control, and interfacial phenomena.

 

The thermally-induced warpages of integrated-circuit (IC) package- or the component-PCB (printed circuit board) assemblies during and after solder reflow processes, due to the mismatch of the coefficients of thermal expansion (CTEs) of those packages or components with the PCB, would cause the problems of the later-on assembly and the solder joint reliability under in-service thermal cycling. In the case of the DIMM socket-PCB assembly after the solder reflow processes, its excessive thermal warpage could generate assembly and reliability problems, which include the difficulty of a latch engagement and the shift of contact points with gold fingers in the DIMM socket, and a later-on installation with a flat metal plate on the full socket-PCB assembly during structural reinforcement. Therefore, the thermal warpage for the DIMM socket-PCB assembly along the socket lines and over the entire assembly after the solder reflow process will be thoroughly investigated theoretically and numerically in this study. A newly-proposed theory and a finite element method (FEM) simulation are to calculate the thermal warpage of the socket-PCB assembly to understand its thermo-mechanical behavior and then further identify some important parameters. A beam-like theoretical solution to this problem has been successfully proposed by modifying the existing Suhir theory. The theoretical solution validated by the FEM simulation has provided detailed mechanics, including the critical parameters such as the CTE (α), elastic modulus (E2), and thickness (t2) of the effective material (which is a combined material of solder joint and Cu pin), and width of the PCB. In addition, the theoretical results and FEM simulation, predicting the cylindrical-like thermal deformation and warpage, are also consistent well with the moiré measurement.

Keywords: Thermal Warpage, DIMM socket, Printed circuit board, Theory, Finite element method.

 

Thermoelectric generators (TEGs) that can convert environmental thermal energy into electricity are regarded as a potential solution to support the intermittent energy consumption of wearable devices and remote wireless sensors. Flexible TEGs (f-TEGs) based on printing technology have gained growing interests due to their design flexibility, ease of fabrication, and low cost. In this report, we have demonstrated a planar f-TEG with 8 pairs of Bi-Te based thermoelements prepared by dispenser printing and pressured sintering processes. The f-TEG can deliver a power of 68 µW under a temperature difference of 33 K. A modular assembly of 7 planar f-TEGs is sufficient to power a light-emitting diode and charge a 1.2 V NiMH battery. In addition to planar TEG configuration, a f-TEG with vertical thermoelement arrangement is also under development. The major issue associated with the vertical TEG fabrication is the poor electrical and mechanical contacts between Cu electrodes and thermoelements caused by gross interfacial reaction during the pressured sintering process. We have introduced a Pd/Ni composite barrier metallization in between the Cu electrode and the printed thermoelements by a selective chemical deposition method to resolve the contact issue. The influence of pressured sintering conditions on the microstructure and contact property of the Cu/thermoelements is investigated.

 

In the state-of-the-art packaging technology, highly (111)-oriented nanotwinned Cu (NT-Cu) has been widely utilized as an interconnect material due to its superior properties and reliability. However, it is quite challenge to fabricate NT-Cu vias for fine-pitch damascene process. The presence of sidewall growth causes reduction of surface (111) texture and affects the filling mode of nanotwinned grains. And this situation will become more serious when the via size continuously scales down to below 10 µm. To solve the scale-limit issue, we developed an optimized electroplating method. Sidewall effect could be suppressed by tailoring electroplating parameters including bath temperatures and waveforms. In this work, we had compared this optimized approach with the common direct current (DC) electroplating. We observed that the sidewall effect was effectively reduced by adding a reverse period during electrodeposition. It is noteworthy that randomly nuclei will be removed during the reverse duration, thus a bottom-up filling mode of NT-Cu in the fine-pitch damascene vias was achieved. The percentage of surface (111) grain of the 10-µm and 2-µm vias reaches 87% and 57%, respectively. In order to predict the surface (111) ratio based on this optimized electroplating method, a mathematical model was established in this work. And we found a great agreement between theoretical value and experimental results.