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With the evolution of advanced IC packaging technology, improving the yield and reliability of packaging products has become a challenge job for engineers. For IC assembly houses, using experiments to identify package performance and life expectation will take a significant amount of time and money to finish the job. To reduce cost and time, predictive analyses of reliability and performance using simulation tools have become a feasible approach for IC assembly Industry. Therefore, this study utilized Moldex3D molding simulation software to analyze VFBGA (very thin profile fine pitch ball grid array) packages and establish a numerical analysis procedure from molding and curing process, post-mold cure (PMC) process to temperature cycling test (TCT) in order to predict the amount of package warpage during processing and reliability after TCT.
In the simulation of the filling process, cross Castro-Macosko viscosity model, Kamal's cure kinetics model and the P-V-T-C relationship of EMC were used to describe the change of viscosity, degree of cure and volume change of EMC over the time during the filling stage. In the post-mold cure (PMC) process, the generalized Maxwell's model was used to describe the relaxation modulus changes of EMC under long-term high-temperature conditions.
VFBGA packaging substrates have a fine pitch redistribution layer (RDL). It is difficult to establish the complex and small composite material layers under a large-scale package strip mesh model. Therefore, in this study, volume percentage method and equivalent reference temperature were used to find the amount of warpage during the substrate lamination process, and it was found that the amount of warpage of the substrate was small after laminating process. Therefore, residual stress and warpage were ignored for the substrate. The simulated amounts of warpage after EMC molding and post mold cure processes were 7.383 mm and 9.005 mm. The shapes of the package after molding and post mold cure process were double-egg-yolk concave downward, which agreed well with the experiment results.
For reliability analysis, to observe the exact failure location, trace import modeling method was employed to establish a single unit substrate model. The modeling process for fine pitch substrate unit was based on volume percentage of copper and convergence analysis was executed to select suitable mesh size for subsequent thermal cycling analysis. The predicted amount of warpage of a single unit was compared with the measured warpage using Shadow Moiré. The results showed that the warpage trends of both experiments and simulations during the same temperature ramping process are similar. In the thermal cycling analysis, the trace import model was assumed to experience two temperature cycles, referring to the temperature profile defined by JESD22-A104F. From the results, potential failure locations were found to be at the copper pillars and RDL, where the maximum Von Mises stress occurred at the lowest temperature (-65°C) during the thermal cycling. The fatigue life model, Coffin-Manson model, was used to calculate the potential fatigue life at the two locations, resulting in 2,140 cycles (copper pillars) and 1,917 cycles (RDL L1).

Bio:
Shen-Jye Huang is a professor in the Department of Mechanical Engineering at National Cheng Kung University. He has dedicated to field of manufacturing process simulation, reliability and failure prediction analysis of IC packages for years.
Research areas:
- Mold filling simulation, wire sweep, and paddle shift analyses, Underfill simulations
- Warpage simulations after molding and post mold cure of packages
- Reliability analysis considering manufacturing process induced residual stresses

 

Electronic packages are manufactured through various processes. The packaging processes, for example resin-molding, sometimes generate a high residual (mechanical) stress in the electronic package. The residual stress during packaging processes of a silicon chip causes a variation of electrical characteristics of semiconductor devices because of the piezo-effect. This issue is a serious for productions of electronic packages and devices. In addition, recently, since silicon chips are becoming larger and thinner for high integration to achieve or beyond Moore’s law, residual stresses on the silicon chips are becoming larger. Therefore, mechanical stress-induced variations of electrical performances of semiconductor devices must be evaluated before manufacturing electronic packages and devices.
We are studying mechanical stress effects on Si metal-oxide-semiconductor field-effect-transistors (Si-MOSFETs). This study evaluates mechanical stress effects in Silicon-on-Insulator (SOI) power n-type MOSFETs (nMOSFETs) by experimental and numerical approaches. The electrical characteristics of SOI-power-nMOSFETs under mechanical loading are measured using a four-point bending method. In addition, a device simulation for evaluating the mechanical stress effects in SOI-power-nMOSFETs are conducted. The device simulation includes physical models for considering mechanical stress effects in Si devices. Especially, because SOI devices perform with parasitic bipolar effects depending on the electrical driving conditions, this study focuses on mechanical stress effects under parasitic bipolar region. The parasitic bipolar effect is a unique physical phenomenon of SOI-type devices.
First, the dc characteristics variations of SOI-power-nMOSFETs under uniaxial-stresses are measured using a 4-point bending system. Two types of specimens are prepared for our 4-point bending measurements; the angles between the longitudinal direction of the specimen and the current flow direction are 0 degrees and 90 degrees. This specimen preparation enables us to apply a uniaxial-stress to the SOI-power-nMOSFETs parallel or perpendicular to the current flow direction. As experimental results, the parasitic bipolar effects observe the region where the applied gate voltage is low. The stress sensitivities of drain conductance change are higher in the parallel direction than in the perpendicular direction. This qualitative tendency is same to the mechanical stress effects on conventional nMOSFETs. It is demonstrated that the parasitic bipolar effects may accelerate the electrical variation induced by the mechanical stress effects.
Next, a drift-diffusion device simulation is conducted for evaluating the mechanical stress effects on SOI-power-nMOSFETs, and the simulation model is included the mechanical stress effects. In the drift-diffusion device simulation, the effects of mechanical stress are reflected in the carrier mobility (i.e., electron mobility): The stress-induced changes in the relative occupancy, the momentum relaxation time and the effective mass of electrons. In addition, in this study, an impact ionization model is used in our device simulation to simulate the parasitic bipolar effects. As a result, the increase in drain current induced by the parasitic bipolar effects can be reproduced in qualitatively. In quantitatively, the comparison between our experimental and simulation results infers that the impact ionization rate reported by a literature varies with mechanical stresses.

 

The tabbed routing is mostly implemented on the PCB with relatively wide trace spacing. For the package level, there is a big challenge for routing hundreds of single-end trace and enlarge each trace space in the limited layout region. Therefore, this work will evaluate the feasibility of the tabbed design at package level. The initial design is considering a pure parallel traces with Single-end 50 ohm. Through simulate S-Parameter and the ratio of LC for tabbed design reference. Then, the tabbed width, length and pitch will be optimized to generate the desired FEXT. Finally, implement the tabbed design in Die to BGA connection and Die-to-Die connection.

 

Over the past decade, Moore's Law has played a crucial role in promoting the growth of semiconductor technology. To further advance Moore's Law, the industry is increasingly relying on advanced packaging techniques such as Fan-Out packages, System-in-Package (SiP), and System-on-Package (SOP). These advanced packaging methods have significantly contributed to achieving outstanding performance in semiconductor devices. Among these packaging methods, the Fan-Out Flip-Chip Ball Grid Array (FO-FCBGA) has emerged as a prevalent and efficient packaging solution with excellent performance. FO-FCBGA offers several advantages, including a substantial increase in input/output (I/O) pins, a reduction in package size, and cost advantages. However, the FO-FCBGA is susceptible to thermally induced warpage caused by the mismatch in coefficients of thermal expansion (CTE) between different materials. This warpage, in turn, leads to thermal stress damage, which can impact subsequent manufacturing processes and product reliability. Therefore, it is imperative to investigate the behavior inside the package and analyze the effects of the geometric structure to effectively mitigate warpage. By gaining a better understanding of the package's internal dynamics and considering the influence of its geometry, measures can be taken to successfully reduce warpage and enhance overall product reliability.
This study focuses on utilizing FO-FCBGA as a research platform to investigate the energy distribution of the copper pillar bump during the packaging process, which can potentially result in package damage. The research is divided into two parts. In the first part, a tensile test is conducted on the polyimide (PI) film, which serves as the dielectric layer material in the package. The test is performed using the MTS Acumen micro force tensile machine, and the characteristics of the PI material under various temperature conditions are examined in a thermal chamber. The warpage of FO-FCBGA under the thermal load of post-mold cure is simulated using Ansys, and the warpage of the actual processed package is measured using the shadow Moiré method. The simulation results exhibit a deviation of approximately 2% compared to the experimental results, indicating good agreement between the finite element method (FEM) and experimental data. In the second part, Ansys is employed to analyze the stress distribution and energy of the copper pillar bump during thermal cycling tests (TCT). The objective is to evaluate the risk of cracking failure in the copper pillar bump. The study investigates dominant geometric factors, such as compound thickness, copper coverage, and die thickness, using the Response Surface Methodology (RSM). Overall, this study aims to comprehensively analyze the energy distribution, warpage, stress distribution, and risk of cracking failure in FO-FCBGA packaging. By employing experimental testing, finite element analysis, and optimization techniques, valuable insights are gained to enhance the reliability and performance of the package structure.

 

Recently, the concept and platform of electric vehicles is widely developed, and the corresponding reliability issue of electronic components contained in aforementioned vehicle is being urgent and must be overcome. In motor or electric vehicle, the vibration loading during operation is inevitable and influenced the long term reliability of aforementioned vehicles. In this study, a tapping test is performed to analyze the modals and corresponding frequency and compared with the finite element analysis (FEA) simulation results. The tapping test is set up as Fig. 1(a), and the experimental extracted modals and frequency are summarized in Fig. 1(b), the analyzed frequency of experimental and simulated results are highly comparable, and the first modal with corresponding natural frequency is regarded as the major vibration loading source and will be adopted in subsequent reliability assessment. To accurately estimate the mechanical responses of SAC305 solder under vibration loading, the cumulative damage test is performed based on the dynamic response under first natural frequency, the utilized electromagnetic vibration test system is shown in Fig. 2. Because the structural dimension of solder ball is narrow and hard to observe the deformation directly, the strain gauge is mounted neighboring the outermost solder location and the strain magnitude induced by cumulative damage test is measured and compared with the FEA simulation result to valid its prediction accuracy. The time-dependence strain magnitude of strain gauge under various acceleration loading is summarized in Fig. 3, and the extracted strain is almost identical to the simulation results on same location. Accordingly, the prediction accuracy of mechanical response is precisely validated and the principal stresses are extracted from FEA simulation for the demonstration of S-N curve. The principal stress-based S-N curve is demonstrated via the assistant of experimental tapping test and FEA stress simulation, the demonstrated S-N curve of SAC 305 solder is illustrated in Fig. 4.The experimental and predicted life cycles are summarized in Table. 1 and the life prediction results showed appropriate accuracy on high acceleration loading and acceptable results on relative lower acceleration loading from 7G to 15G. Accordingly, the principal stress-based S-N curve of SAC305 is demonstrated.

 

OPLGA package is a clear compound encapsulated. Since clear compound is highly sensitive to moisture, it is necessary to avoid influence of diffusion in design of packaging structure. Otherwise, if design is in position with high moisture content, the residue on moisture will be delaminated or even compound will be crack by vapor pressure at silicon interface. Therefore, early design through simulation Fick's diffusion theory to find the best design without changing size of package, the compound volume affects optics, so modify design not only avoids moisture but also ensures that optical performance will be keeping.

 

Demonstrate integration of failure analysis with predictive analytics to expedite determination of potential root causes and their interactions leading to early life time cracks of wafer probe card. Root causes of early failure (i.e. activation of probe card, tip length and overdrive of pogo pins) were validated by experiments. This problem solving approach can be effectively used for early failure analysis of semiconductor devices leading to fast, accurate and efficient diagnosis of root causes of failures specially when failures are caused by multiple-interactions among different variables.

 

The World Radio Conference (WRC) established the fifth generation (5G) frequency bands in WRC’19, including 24, 25–27.5, 31.8–33.4, and 37–40.5 GHz bands. The main reason is the availability of these bandwidths can significantly increase the wireless binary rates above 10 Gbps, thereby being very benificial to the applications of communication satellites, short-range targeting radars, web servers and so on. Since high-frequency/-speed signal transmission is more susceptible to the transmission line design and material characterestics, a comprehensive study of the signal transmission performance in different types of transmission lines is of fundamental interest and practice importance at the current stage.
High-layer-count printed circuit boards (HLC-PCBs) can save space by stacking circuits via plate through holes (PTHs) to electrical connections among different circuit-board layers to meet the requirements of the lower time delays, faster data rates, and higher capacities. However, the existence of stub in the PTH structure might cause SI concerns due to impedance discontinuity resulting from parasitic inductance and capacitance, particularly in the high-frequency transmission. As shown in Fig. 1(a), signals split into two portions when they are delivered in a via structure. The stubs show a resonant behavior similar to an open/short transmission line due to the wave effect. As a consequence, stubs may act as electric open/short at their terminal, resulting in near-zero signal transmission in transmission line. To eliminate the undesired stubs and to assure SI in the high-frequency transmission, a back drilling process is now being adopted in the fabrication of HLC-PCBs. However, a portion of stubs can still remain in PCB after the back drilling process owing to the back drill engineering tolerance. The focus of this study is to quantitatively characterize the effect of the remaining stub length (δ) on the signal transmission performance in eco-friendly HLC-PCB (Dk = 3.26; Df = 0.0025 at f = 10 GHz).
Experimentally, the effects of δ on the signal transmission performances (Sdd21, impedance, and current density distribution) at 1–40 GHz frequency bands were quantitatively analyzed through the finite element analysis (FEA) method with a 3D electromagnetic simulation software. Sdd21 is defined as the differential response at receiving end due to a stimulus at transmitting end, and is a key indicator of the signal loss of differential mode transmission. Furthermore, experimental measurements via vector network analyzers (VNA) were conducted to characterize Sdd21 arising from different δ, so as to validate the FEA simulation.
Fig. 1(b) shows the simulated Sdd21 arising from different δ at f = 1–40 GHz. For δ >=30 mil, a noticeable signal loss can be observed, especially at specific f values (frs). Generally, the theoretical value of frs agreed well with the simulation results and VNA measurements. A theoretical estimation on frs will be addressed in the full text. Interestingly, Sdd21 significantly reduced as δ decreased to 10 mil, reflecting the positive effect of back drilling process on the signal transmission performance. Fig. 1(c) shows the simulated surface current density (Jsurf) distribution in the PTH structure without back-drilling. Noticeable surface current distributed over the ground vias can be clearly observed for a long remaining stub at 40 GHz. The induced current over the ground vias was caused by the proximity effect and might result in SI and electromagnetic compatibility (EMC) reliability concerns. This simulation results provided rationalization about the significant signal degradation observed for δ >= 30 mil (Fig. 1b). Detailed analysis on the S-parameters, impedance, and current density distribution in relation to the via stub length will be presented in this paper.

 

As the size of advanced packaging products continues to decrease, the thermal budget available for flip chip products during the bonding process also decreases. Laser-Assisted Bonding (LAB) process offers an alternative method to establish interconnections between dies and substrates, as compared to the conventional mass reflow process. LAB process provides several advantages, including localized heating, precise thermal energy control, and prevention of substrate overheating. These benefits contribute to reducing overall warpage of the strip and enable the bonding process of a single package unit to be completed in just a few hundred milliseconds. With the significantly reduced heating time, it is crucial to achieve a uniform temperature distribution across the heated die to ensure a proper interconnection between the die and substrate. However, our partners' experimental results indicate a significant temperature difference between the die center and the die corner. Initially, the temperature of the corner side increases rapidly during the LAB process, followed by a sudden temperature drop, eventually aligning with the temperature trend observed in the center region. In our preliminary research, we hypothesized that these temperature differences between the die center and corner were a result of the inherent warpage of the dies and substrates, which prevented uniform contact between the die and substrate prior to laser heating. As the die is heated by the laser, thermal-induced deformation improves the contact condition, and the solder bumps that contact the substrate play a crucial role in conducting heat from the die to the substrate, thereby reducing the temperature of the die corner. In this study, we introduce a simplified two-dimensional flip chip model consisting of a single die unit, a substrate, several solder bumps, and the air surrounding the die and bumps to validate our hypothesis. We employ finite-element methods to solve the simulations, which consider the deformation of the die when subjected to laser heating and the heat transfer phenomenon occurring within the entire package. A notable feature of this model is the application of the phase-field model to describe the liquid solder/air interface. This model allows us to successfully simulate the formation of new contacts between the die and substrate during the heating process and demonstrate that these new contacts serve as a pathway for conducting excess heat from the die to the substrate. The simulation method developed in this study proves to be a powerful tool for packaging analysis, as it offers valuable insights into both the heat profile and warpage profile changes resulting from the formation of new contacts through solder during the heating and cooling processes.