Oral Sessions


S26: Advanced Packagng Process and Design

Oct. 28, 2022 13:30 PM - 15:30 PM

Room: 504b
Session chair: MY Tsai , Professor, CGU / Jenn-Ming Song,Professor, NCHU

Adhesion and Reliability Study of Different EMC and Pre-plated Leadframe Surface Combination for Au and Cu wire bonded Leadless Package
發表編號:S26-1時間:13:30 - 13:45

April Joy Garete

In this study, different molding compounds and pre-plated leadframe surface combinations were characterized in terms of adhesion and its impact on package delamination. Furthermore, Au and Cu wire bonded devices assembled using different EMC and leadframe surface treatment combinations were also assessed to evaluate the quality and reliability performance of these BOM as packaging materials for a DFN package. Key features of the different molding compound materials investigated in this study includes advanced formulation for improved delamination resistance, better fluidity, and copper wire compatibility.
Full material characterization was conducted to compare the physical and thermo-mechanical properties of the EMCs. Button shear test on standard and rough pre-plated lead frame surfaces was then performed to compare the interfacial adhesion performance and typical shear failure modes of various molding compounds. Adhesion data was further supported by subjecting the assembled of DFN package with different BOM combination to Moisture Sensitivity Level 1 (MSL1). Scanning Acoustic Microscopy (SAM) was then used to check the delamination performance on all mold interfaces at zero hour and after MSL1. The delamination level difference between samples built with different EMC types and pre-plated leadframe combinations were summarized in this study.
A 23um diameter Au-wire and Cu-wire bonded transistor was used as test vehicle to evaluate the material reliability performance on package level. Moldability check was done to inspect any external voids, incomplete fill, or wire sweep occurrence for all BOM combinations. Reliability performance was assessed by subjecting the assembled units to 1000 cycles Temperature Cycling Test (TCT), 96 hours Highly Accelerated Stress Test (HAST), and 1000 hours High Temperature Reverse Bias (HTRB) at a junction temperature of 150°C. Overall, the material study was able to successfully assess the adhesion, moldability, delamination and reliability performance of different molding compounds and pre-plated leadframe combinations on Au-wire and Cu-wire bonded DFN package.
Keywords: adhesion, reliability, epoxy molding compound, pre-plated leadframe, Au and Cu wire

Effect of Package Singulation Parameters on Dual Flat Non-leaded Package Delamination
發表編號:S26-2時間:13:45 - 14:00

Siying Wu

With the evolution of electronic field, the reliability requirement of package is getting stringent. The package is required to work and maintain good performance under extreme conditions. Interfacial delamination is one of the key factors that destroy the reliability of electronic package. When the delamination occurs between lead frame (LF) and epoxy molding compound (EMC), the moisture will ingress into the package and cause popcorn phenomenon, which eventually induce package crack and lead to electrical failure.

To improve the delamination performance and enhance the stability of Dual Flat Non-leaded (DFN) package, the effects of package singulation parameters on package delamination performance were investigated in this study, using different types of blade, saw method, spindle speed, feed speed and waterflow rate. After singulation, the package outlook quality was checked using Microscope, were tested by Scanning Acoustic Microscope (C-SAM) with C mode. And the delamination defect number was count after C-SAM. To further investigate the reliability of sample, the moisture sensitivity level (MSL) test was used to accelerated sample ageing (24h bake under 125°C, 158h moisture soak at 85C/85%RH and three times reflow). Besides, take the cross section of delaminated sample and observed the delamination gap under Scanning Electron Microscope (SEM).
As the result shows, the grit size of saw blade is one of the impact factors in delamination. The blade with large grit size will cause more stress on the package and lead to delamination during singulation. The saw methods also have effect on delamination performance. The chopper cut and normal cut method were used in the same type of package to compare the delamination performance. The results of C-SAM show the normal cut has better delamination performance than chopper cut. In addition, the delamination performance deteriorated with increase of spindle speed, which is related to the adverse impact of blade at high spindle speed and heat generation of friction. During blade singulation mechanism, heat was generated at few hundred degree Celsius temperature, causing EMC and LF expand and contract, creating a stress which reduced the adhesion strength between EMC and LF. And the feed speed has no significant in delamination performance. Besides, an interesting phenomenon was observed, the delamination performance improved with increase of water flowrate. The saw blade was cooled by water flow which can reduce the frictional thermal stress during singulation process.

To sum up, the effect of package singulation on delamination defects are present in this study. The blade with small grit size can reduce the stress between blade and package. And the delamination performance can improve by suitable saw method, low spindle speed and large water flowrate.

Keywords: Singulation, Blade type, spindle speed, feed rate, water flowrate

A Sn-Bi-X low-temperature solder design with high ductility
發表編號:S26-3時間:14:00 - 14:15

Ahmad Kholik, Yu-chen Liu, Chih-han Yang, and Shih-kang Lin

Currently, the Sn-Ag-Cu (SAC) solder system has been widely-used in electronic packaging. The typical reflow temperature of 250℃ in applying the SAC solder as interconnections causes warpage issue in advanced packaging. The warpage issue causes the alignment fault between chips and boards, and thus decreases the reliability of the electronic products. Low-melting temperature solder material has been proposed as a solution in reducing the reflow temperature in order to solve the warpage issue. Material systems such as Sn-Bi, Sn-In, Sn-Zn are considered as potential candidates in replacing SAC materials. Among the all, Sn-Bi solder material has its potential for real applications due to the cost, and processing feasibility. Nevertheless, the segregation and coarsening of (Bi) phase causing brittleness leads to the mechanical property degradation of the solder. Typically, Sn-Bi-based solder exhibited an elongation decrease after the it was aged at elevated temperature in mimicking the thermal cycling test. Research has proposed that element doping in Sn-Bi solder is one of the ways to tailor the material properties. Elements doping effect such as In, Zn, Ga, Ag, Al, Ti, etc., have been studied. In this study, we proposed a Sn-Bi-X solder alloy which exhibited an ultimate tensile strength (UTS) of 38.1 MPa and elongation of 274.3 % after thermally aged at 80℃ for 3 weeks. The tensile test was performed at the strain rate of 0.33 mm/min. The as-cast alloy exhibited UTS of 42.3 MPa and elongation of 148.5 %. The elongation of the designed alloy did not degrade after the aging test. On contrary, the elongation was further improved ca. twice times and UTS only decreased in a minor manner. The solidus temperature was 79.4℃ while the liquidus temperature was 130℃. Series of scanning electron microscopic, electron backscatter diffraction, and x-ray diffraction were performed to study the microstructure evolution. The mechanism of the superior elongation of the designed alloy is pursued in the present work.

3D IC packaging design may take a village but starts with a netlist
發表編號:S26-4時間:14:15 - 14:30

Tarek Ramadan

The semiconductor industry is facing an inflexion point as higher cost, lower yield, and reticle size limitations drive the need for viable alternatives to traditional monolithic solutions, which are hitting or coming close to the limits of manufacturing and physics. Integrating multiple dies and substrates into a single package is an increasing focus and practice of the semiconductors industry. Compared to the traditional transistor scaling approach, advanced packaging promises improved form factor, cost, performance, and functionality as well. One common approach is the use of 2.5D-IC technologies to connect multiple dies side by side using an interposer which can be silicon-based or organic. Equally common is the use of fan-out wafer level packaging technologies, where multiple dies are connected through the package RDL routing.

For the past few years, the emphasis has been on the heterogeneous aspect of advanced packaging. That is, multiple dies manufactured using different technology nodes are integrated into a single package.
However, recently, slicing a big monolithic SoC into chiplets and connecting these chiplets through a silicon interposer is gaining significant traction as well. This approach supports a new integration paradigm in which designers can mix and match already-built blocks (hard IPs) into their products. Moreover, it shifts the attention back to silicon interposers, which had been considered by many a too-costly integration option given the technological aspects involved.
The full commercial productization of these advanced packaging options requires the assurance of both an acceptable yield and correct (as intended) functionality. This assurance, like that for integrated circuit (IC) designs, depends on the availability of proven and qualified methodologies and workflows that can be used by semiconductor design teams to build products with confidence. In the context of physical verification, designers need to confirm that the full assembly (available in a manufacturing format) is connected as expected (as compared to the design intent, which is captured in the system-level design before physical implementation). To run assembly verification, the designer should first be able to capture the 3D IC assembly connectivity as intended. This can be a challenge as each substrate of the assembly can be owned by a different design team.
As 3D IC assembly verification requires a system source netlist, a designer needs to make sure that he or she can capture the full, intended connectivity of the die, silicon interposer, and organic substrate. The silicon interposer is usually owned by an IC design team with an IC design background and uses IC design tools and formats. Meanwhile, the organic substrate is usually owned by the package design team that has a traditional package design background and related design tools and formats.
Typically, the organic substrate connectivity is captured in a CSV file that basically includes the package bump (x,y) locations, pin names and numbers, and net names. On the other hand, interposer connectivity can be captured in many ways. For years, the interposer design methodology has been considered borderline IC/package design.
However, recently, a significant number of designers have begun to build silicon interposers similar to how they build digital SoCs. This is done by using automatic place and route (P&R) methodologies, which means that the interposer connectivity is usually captured in a Verilog netlist format.
To capture both the connectivity of the silicon interposer (Verilog) plus the connectivity of the organic package (spreadsheet), a system-level connectivity planning and management platform is essential. Designers need an aggregation platform that can consume different connectivity formats, allow users to modify and assign connectivity (either interactively or batch), and, eventually, combine the different netlists and generate a single system-level netlist that can drive 3D IC assembly verification
In this paper, I will discuss and present a methodology, process and platform for the robust capture and definition of a complete 3D package assemblies netlist which will become the “golden” system netlist that can then be used to drive all downstream verification activities

Stretchable piezoresistive strain sensors based on gold nanoparticle films for highly sensitive human pulse sensing
發表編號:S26-5時間:14:30 - 14:45

Wei-Rong Yang

The principle of commercial pulse diagnosis devices is attaching a radial sensor to the artery position, where the arterial pulses introduce stress or strain to the sensor, causing periodic voltage change or resistance change. The pulse wave can thus be transduced and recorded in the form of electrial signals. In order to enhance waveform resolution, the improvement of sensor sensitivity is still an ongoing issue. Over a decade, intensive efforts have been devoted to build flexible sensors using conductive nanomaterials based on piezoresistive mechanisms. In this study, highly-sensitive piezoresistive strain sensors based on gold nanoparticle thin films deposited on a stretchable PDMS substrate by centrifugation were developed to measure arterial pulse waveform. By controlling carbon chain length of surfactants, pH value and particle density of the colloidal solutions, the gauge factors of nanoparticle thin film sensors can be optimized up to 677 in tensile mode and 338 in compressive mode, while the pressure sensitivity up to 350. Low pH and thin NP films produce positive influences to superior gauge factors. It has been demonstrated that nanoparticle thin film sensors on PDMS substrates were successfully applied to sense arterial pulses in different body positions, including wrist, elbow crease, neck, and ches.

Interfacial Analysis on Microelectronic Packaging: Voids Observation and Crystallographic Analysis at Bonding Interface on Fine-pitch Cu-Cu Hybrid Joints by Cut-and-view Techniques
發表編號:S26-6時間:14:45 - 15:00

Jia-Juen Ong

Lead (Pb) free solder has been used as bonding materials in microelectronics packaging known as transient liquid phase diffusion bonding (TLPDB) for the last few decades due to its excellent reliability, process cost, and form factors. To increase the performance of transistors, a larger amount of inputs/outputs (I/Os) is needed which is known as Moore’s law. Thus, the dimension of I/Os must be significantly decreased. In addition, solder microbumps have intrinsic issues such as side wall wetting, whiskers, bridging, eventually resulting in circuit failures. Recently, the potential in scaling with excellent electrical properties of Cu-Cu bonding has been reported. Furthermore, filling the molding compound into the gaps between Cu joints to prevent further oxidation has become a great challenge. Currently, metal/dielectric hybrid bonding could be one of the best solutions to fabricated ultra-high density I/O devices with excellent bonding strength and electrical properties. However, defects (voids) in the bonding interface are unavoidable due to the atomic diffusion in metals. It has been reported that the electrical resistance of devices is highly related to interfacial voids. Thus, interfacial analyzing tools for void observation at the bonding interface are crucial. In this study, we demonstrate a continuous etching quasi-in situ observation using focused ion beam (FIB), scanning electron microscope (SEM), and electron backscattered diffraction (EBSD). Results show the reliable data of void quantization and variation in size and distribution at the bonding interface.

Enhancing Cu/Sn3.5Ag/Cu transient liquid phase soldering mechanical properties with element addition
發表編號:S26-7時間:15:00 - 15:15

Zih-You Wu

Recently, the transient liquid phase (TLP) bonding process has become a promising method in advanced electronic packaging. Full intermetallic compounds (IMCs) joints provide good strength and reliable high-melting point phase after bonding. However, Kirkendall voids accompanied with Cu3Sn and the strong preferred orientation of Cu6Sn5 may deteriorate the reliability in conventional Cu/Sn/Cu bumps. To resolve these problems and further enhance the mechanical proprieties, Ni and Zn are used to modify microstructures of the TLP bonding. Moreover, microstructure, grain, and mechanical analyses are employed to elucidate the mechanisms behind the strengthening effect of Ni and Zn in Cu18Ni/SA/Cu and Cu18Ni18Zn/SA/Cu bump.


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