Oral Sessions


S22: Power Electronics

Oct. 28, 2022 10:30 AM - 12:30 PM

Room: R504b
Session chair: Albert Wu, Professor, NCU / Allen Liu, ITRI

Power Module Packaging & Thermal Management in EV Applications
發表編號:S22-1時間:10:30 - 11:00

Invited Speaker

Chun-Kai Liu, Principle Engineer, Industrial Technology Research Institute


Impact of Via Structure Toward Wire Bond Interconnect Quality
發表編號:S22-2時間:11:00 - 11:15

Lee Kuan Fang, Alex Schliebitz, Jakob Holfeld, Ng Hong Seng

Vertical interconnect access (VIA) is an electrical structure designed as a bridge between multi-layers metallization of microelectronic silicon wafer. As a conductive gateway between metal layers, via structure designated at all possible locations in a device base on integrated circuit (IC) routing requirement. As an effective current passageway, it is very common to have via structure fabricated underneath aluminum bonding pad. In the subsequent process of IC packaging, bond pad will be subjected to thermosonic wire bonding by using gold or copper wire. Certain devices will be subjected to ultrasonic wedge bonding of aluminum wire based on specific application. There is no direct contact of via structure and bonding wire in this entire process. Nevertheless, via underneath bond pad is optically observable as imprint on bond pad surface in some devices. Existence of via imprint leads to a quality inquiry of bond pad surface for wire bonding process. It was naturally assumed that via imprint will increase bond pad surface roughness as compared to bond pad without via structure directly underneath bonding area. In this study, test samples with various via structure design were selected for examination. The study involved attentive bond pad surface roughness measurement by using AFM analysis. Key surface roughness indicators (such as Ra, Rq, and Z-Range) were collected from wire bonding area of test samples. These measurements data are important to provide quantitative surface roughness conditions of test samples. On top of surface roughness, via structure density is also part of the research. Hence, test samples selected consist of bond pads with various via structure variants and bond pads with no vias underneath aluminum layer as a baseline. Via to via distance of the evaluated samples were 1.2µm and 1.4 µm. The samples also covered minor differences in term of via structure formation. Wire bondability study was the following step after bond pad surface roughness assessment. Impact of via-induced surface roughness toward wire bonding process was carefully evaluated. The conventional thermosonic wire bonding was performed by using 2N gold wire together with optimized parameters settings. This followed by standard bond quality check of wire bond shear test, wire pull test, as well as failure mode examination through optical microscope. These are important information to analyze impact of surface roughness and via density toward bondability. Results obtained from this evaluation enable better understanding of via structure’s impact toward wire bonding process. This also served as valuable information for IC product design, especially whenever application of via structure underneath bond pad is required.

Development and Power Loss Estimation of SiC-based Power Module
發表編號:S22-3時間:11:15 - 11:30

Yan-Cheng Liu, Hsien-Chie Cheng, Hsin-Han Lin, Shian-Chiau Chiou, Tao-Chih Chang

In recent years, countries are actively developing green energy, such as solar and wind power, to replace fossil fuels and set rigorous regulations for CO2 emissions from automobiles to safeguard the environment and achieve sustainable development [1-2]. Due to their ability to control the circuit and to convert electrical and kinetic energy, power semiconductor components/modules are used in the functions of frequency conversion, voltage conversion, current conversion, power amplification, and power management for electric vehicles (EVs), EV charging stations, unmanned aerial vehicles (UAVs), and green energy. The MOSFETs and IGBTs power components, such as inverters and converters, are widely used in power conversion systems, including renewable energy generation systems, three-phase motor drives for EVs, hybrid EVs, battery EVs, and industrial servo motors [3]. However, MOSFETs have the advantage of lower switching losses, lower on-state resistance, and higher switching speeds [4]. Despite the rapid development and numerous benefits of power modules, there are still many issues to be resolved, such as heat dissipation and reliability. Many related works of literature have been researched on issues related to power modules [5-6]. Furthermore, power semiconductor using wide bandgap (WBG) silicon carbide (SiC) and Gallium Nitride (GaN) as chip materials have lower switching times and losses as a result of advancements in material and process technology [7-10]. High breakdown voltage, high operating electric field, high operating temperature, high switching frequency, and low loss are all the advantages of WBG materials [11, 12]. Biela et al. [11] discovered that SiC power components perform far better than Si power components under high voltage and high temperature operating conditions. Thus, the SiC power components have become the preferred material for the next generation of power semiconductor devices, replacing the Si technology. Therefore, this research develops an SiC-based power module (see Fig. 1) with an output power of 12 kW and a switching frequency of 30 kHz to control servo motors of electric engineering vehicle. The developed SiC-based power module is divided into three different parts based on their functions: the brake circuit, the three-phase rectifier, and the SiC-based inverter, which consists of 12 SiC power MOSFET components. The primary objective of this research is to evaluate the power loss and switching transients of the SiC power MOSFET inverter during the three-phase switching operation in a 1200V/200A SiC-based power module through a fully integrated electromagnetic circuit (FIEC) co-simulation method. This FIEC model utilizes space vector pulse width modulation (SVPWM) control signal to achieve a three-phase switching operation. The power losses of the SiC-based inverter, including switching, conduction, diode, and reverse recovery losses. To conduct a precise study on the switching transients of power components, a curve analyzer is used to evaluate the temperature-dependent output and transfer characteristics of the SiC power MOSFET device, as well as the body diode characteristics. By incorporating an electromagnetic (EM) simulation, the effects of the parasitic parameters of the SiC-based inverter calculated at a 1 MHz operating frequency on switching transients and the power losses are also considered. In accordance with IEC standard of Double Pulse Test, switching transient waveforms at 600V drain voltage and 200A load current are utilized to validate the FIEC co-simulation (see Table 1). An FIEC model of a SiC-based inverter is shown in Fig.2, which is used to estimate the power loss during the three-phase switching operation through SVPWM control under a resistive load in a 12 Ω delta configuration with a 400V DC bus voltage and 30A load current, while the switching frequency and duty cycle of SVPWM control are at 15 kHz and 82%, respectively. The result of the power loss can be see in Table 2. The output waveform of the SiC-based inverter through FIEC model is further validated by three-phase inverter switching experiment (see Fig. 3). Finally, parametric analysis is used to study the effect of switching frequency on the power loss of the SiC inverter during the load cycle.

Thermal Design of SiC Power Module for EV/HEV Applications
發表編號:S22-4時間:11:30 - 11:45

Chun-Kai Liu, Chiu Po-Kai, Yuan-Cheng Huang, Ji-Yuan Syu, Yu-An Chou, Kuang-Hung, Wu, Wen-Yang Pan

Currently, the transportation sector contributes about 30% of greenhouse gas emissions annually. Electrifying the transportation sector to combat climate change is a major concern for governments and global automakers [1]. Power electronics (PE) converters in electric vehicles determine much of the vehicle's efficiency and power output. The efficiency directly affects the performance of a vehicle, such as the driving distance. Thus, improving the efficiency, while reducing the volume and weight of the powertrain system is an important trend in electric vehicles. The Department of Energy (DOE) in the US has set an efficiency target of 98% and a power density target of 100 kW/L for automotive PE by 2025. Thermal management solutions of power modules face new challenges in mitigating the increased heat flux in PE equipment due to increased power density. High heat flux can raise the temperature of power devices and ICs, which reduces reliability and efficiency, and can lead to failure. Power semiconductor devices are packaged into power modules, which are the core of PE converters. Silicon-Carbide semiconductor device has the benefits of higher breakdown voltage, higher current, higher operating temperature, higher switching speed, and lower switching loss over Si devices. It offers system-level benefits of high efficiency and power density to electric drivetrains. However, thermal management remains an important issue for the performance of SiC power modules. Thermal solutions of power modules can be implemented as indirect, direct, or double-sided cooling methods and can have a large impact on the performance of the system. The thermal design of the power module can be analyzed by numerical simulation and thermal measurement. The optimum thermal design of SiC power modules has significant effects on system performance.
In this paper, we studied the thermal design of the 1200V, 400A SiC power module for EV/HEV applications by numerical simulation and experimental measurement. The SiC power module has 3 phases of topology. SiC semiconductor devices are soldered on the AMB ceramic substrate, interconnected by Al wire bonding. The AMB ceramic substrates are soldered to a pin fin heat sink. Without the thermal interface material, the power module is directly cooled by the liquid flowing through the heat sink, as shown in Figure 1. The results of thermal simulation show that the most heat of SiC chips is conducted through the ceramic substrate to heat sink and then removed to liquid by convection heat transfer [5]. The liquid with a constant volume flow rate flowed through the inlet and outlet of the liquid jacket and the pin fin heat sink. The lower temperature at upstream chips and higher temperature at downstream chips in the flow direction, as shown in Figure 2. The flow resistance of the liquid inlet, outlet, and pin fin forms a pressure drop. Increasing the number of fins decrease thermal resistance, while increasing the pressure drop. The transient thermal resistance of the power module was measured by T3ster equipment, as shown in Figure 3. Thermal resistance calculated by simulation agreed with the experimental test result. We compared the thermal performance of the Si IGBT power module and SiC power module with simulation and experimental measurement. The optimum thermal performance of pin fin design and the effects of pressure drop are comprehensively studied.

The numerical study of mechanical improvement of the metal annealing process during the manufacturing of the IC backend Damascene structure.
發表編號:S22-5時間:11:45 - 12:00

P.Y. Sun, Cadmus C.A. Yuan and K.N. Chiang

 The demand for the high speed and smaller dimensions drives the IC industry to the advanced technologies, such as the Cu/low-k structure for low RC delay. Since the 2000s, industries have introduced the Dam easene process, including the chemical vapor deposition of the low-k material, chemical-electrical plating of the copper, and chemical-mechanical polishing process, and it is very different than the conventional aluminum-based process, and many new failure modes have been detected [1]. Up to now, the Cu/low-k structure has been applied to many applications.
 Chen and Jang [2] have revealed a two-stage Damascene process, which introduces the copper trace annealing process in manufacturing each metal stack. In the second annealing, the condition of the environmental temperature of 350-450℃ and the duration of 25-30 minutes is preferred. Moreover, Harman and Johnson [3]indicated that the annealing of the copper under the argon environment at 300 ℃ for 30 minutes significantly reduces the copper mechanical modulus.
 One of the essential root causes of the Cu/low-k structure reliability challenge is the tremendous difference in the mechanical characteristics of the copper and the low-k material. Compared to the conventional aluminum-based structure, the stiffness of copper is approximately two times higher than aluminum. On the other hand, the low-k material is roughly 8-10 times softer than the conventional silicon dioxide material. Considering the inversed high-rise building-like back-end-of-line (BEOL) structure of IC design, a large deformation is expected when the loading from the IC pad is detected, compared to the aluminum-based structure.
 Analyzing the IC manufacturing process, the wire bonding (w/b) process, which is a high-flexible and cost-effective process to enable the electrical interconnect to the exterior PCB, introduces the most axial loading to the BEOL. A typical w/b process comprises two stages: a vertical movement of the wire and a following ultrasonic movement to increase the bonding strength. During the w/b process, remarkable energy has been transduced to the IC BEOL through the w/b machine.
 This research establishes a set of transient finite element models to represent the mechanical impacts during the w/b process[4]. Moreover, a finite element model of the BEOL structure, which consisted of 7 layers of copper metal stacks and an aluminum pad to represent the current frequent-used technology, is established to investigate the stress pattern. A full w/b process, including the downward wire movement and the ultrasonic movement, is considered the external loading of the model. The results show that, although the ultrasonic loading introduces periodical stress propagation within the structure, the maximum stress increase is insignificant. Moreover, reducing the copper stiffness reduces the risk of copper stack failure.

Wire Boning Process Failure Risk Estimation of the Cu/low-k Structure using the Transient Finite Element
發表編號:S22-6時間:12:00 - 12:15

Jing Yu Wang

The Cu/low-k structure is attracted by the IC back-end-of-line (BEOL) designer due to its excellent electrical performance. Silicon oxide based low-k materials are preferred because the fabrication processes for these materials exhibit high IC compatibility with a high yielding rate. These low-k materials, e.g., the SiOC:H (Black Diamond), are fabricated by the chemical vapor deposition (CVD) based processes and are mostly amorphous and porous. Hence, the mechanical resistances of the low-k material, including Young's modulus and the fracture toughness, are often much lower than the conventional silicon oxide.

Delamination at the interfaces with low-k material is a critical issue for the reliability of IC backend structures[1, 2]. The mechanical characteristics of the low-k material can be tuned by precisely controlling the CVD process[3], and such mechanical improvement can be optimized by the numerical model[2, 4]. Hence, to maintain the robustness of the IC/packaging yield/reliability, it is important for the IC backend designer to draft a proper mechanical strength requirement for the low-k material manufacturer.
Considering the Cu/low-k failure, one of the critical processes is the wire bonding (w/b) process. Due to its flexibility and high yield, the w/b process remains the mainstream interconnect method for IC packaging. On the other hand, identifying the potential failure of the Cu/low-k structure remains a technical challenge, because the complexity of the IC backend structure and the point failure might propagate through time, which might interact with another layer/structure. Hence, the numerical approach is often proceeded to estimate the design risk and obtain the design requirements.

This research establishes a set of transient finite element models to represent the mechanical impacts during the w/b process[5]. Moreover, a finite element model of the BEOL structure, which consisted of 7 layers of copper metal stacks and an aluminum pad to represent the current frequent-used technology, is established to investigate the stress pattern. The results show that both the Cu/low-k design and the w/b process parameters, including the free-air ball (FAB) size and w/b capillary, influence the maximum stress of the Cu/low-k structure. It is suggested that the w/b process of Cu/low-k structure should be precisely controlled, compared to the conventional w/b process of the Al/SiO4 structure, to maintain the low stress level of the Cu/low-k structure.

High-strength and fine-grained pure copper foils for electronic components
發表編號:S22-7時間:12:15 - 12:30

Fu-Chian Chen, Chih Chen,

As a material with good electrical conductivity and low cost, copper has been widely used in electronic devices as conductors. With the continuous advancement of electronic devices, the demand for the behavior of copper is also increasing. Some electronic components operate under high power and long-term working environment. In other words, we need the copper not only to have good tensile strength behavior, but we also need it to have good electrical and thermal stability at the same time. As a part of electronic components, it still must maintain a certain degree of conductivity.

Alloys have always been an intuitive way to strengthen metals, but it can also drastically affect conductivity while strengthening. Therefore, our team is still committed to improving the mechanical properties and strength of pure electroplated copper foils by proper additives and electroplating parameters.

In this study we electroplated copper foils by rotary plating. We used iridium oxide and titanium wheel as electrode. By using multiple types of additives, we have successfully electroplated nanotwinned copper foils with a titanium wheel which the ultimate tensile strength can reach up to over 740 MPa. Figure 2 shows the microstructures of the as fabricated Cu foils and fine grains were obtained. The thickness of copper foils we electroplated is around 20 μm, the commercial electroplated copper foil with same thickness often behaves ultimate tensile strength around 400MPa.


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