Oral Sessions


Pleanry IV

Oct. 28, 2022 08:50 AM - 09:30 AM

Room: R504a
Session chair: Hsien-Chie Cheng, Distinguished Professor, FCU

Co-creative Packaging Evaluation Platform “JOINT2” for 2.xD and 3D Package

Plenary speaker

Hidenori Abe, Director, Showa Denko Materials

We continue to provide the highly reliable and process compatible materials by the packaging fabrication and evaluation utilizing our installed facility which has the similar spec as our customers. On the other hand, the semiconductor packaging requires more and more complicated structure and process to keep increasing the performance at a reasonable cost. Showa Denko Materials has started Packaging Solution Center as new R&D center to propose one-stop solution for customers in 2018 and established the co-creative packaging evaluation platform “JOINT2” with leading companies to accelerate the development of advanced materials, equipment and substrates for 2.xD and 3D package in October, 2021. We introduce the significance and strength of JOINT2 and the R&D update status.
Abe is leading R&D of semiconductor, substrate and display materials at Showa Denko. In addition, he is head of packaging solution center, which is open innovation hub in advanced packaging development. He launched JOINT2, new advanced packaging consortium targeting 2.xD and 3D package in 2021.
Prior to current mission, Hidenori Abe has been a General Manager of CMP slurry business sector for three years. Before that Abe was a manager of Marketing Promotion group in Innovation Promotion Center at Hitachi Chemical for 2 years with responsibility to propose new R&D projects, especially targeting new business field for Hitachi Chemical using new technology, and also to promote developing R&D products. Abe was manager of business development group in packaging solution center at Hitachi Chemical for 1 year with responsibility to promote open laboratory to partners such as customers and equipment makers, responsibility of marketing wearable related materials. Before that, Abe was molding compounds engineer at Hitachi Chemical. During his 16 years carrier as molding compounds engineer, Abe spent time doing responsibility of development of non-conductive carbon, Green molding compounds, Cu wire compatible molding compounds, wafer level compression compounds, power module molding compounds and so on. His Cu wire compatible molding compounds development work contributed to the promotion to Cu wire conversion through several published papers.
Abe received a master degree in chemical engineering field from Tokyo institute of technology, Japan and a master degree at the EMBA course from Oxford, UK.


Pleanry V

Oct. 28, 2022 09:30 AM - 10:10 AM

Room: R504a
Session chair: Yu-Hua Chen, VP, Unimicron

Advanced Packaging and Its Impact on Substrate Demand

Plenary speaker

Shiuh-Kao Chiang , Managing Partner, Prismark

Substrates are a critical component in semiconductor packaging. When multiple high-performance and large body-size ICs are interconnected and integrated in one advanced package, the technical and economic requirements on substrates are monumental. There are a few promising high-performance 2.5D and 3D packaging formats available in the industry now. Interestingly, they all require a relatively sophisticated and large-sized substrate to connect to a system motherboard. As a result, FCBGA substrate demands are surging and substrate capital investments are booming. In this paper, recent developments in advanced packaging will be reviewed. Technology developments and supply capacity expansion of advanced substrates will be discussed.

Short Bio

Dr. Shiuh-Kao Chiang
- BS from National Tsing Hua University and PhD from the Ohio State University.
- Joined Prismark in 1998 and has been one of the Managing Partners for over 20 years.
- Active business consultant in the semiconductor packaging and PCB industry.


S21: Market Trend: Innovative More-than-Moore Packaging

Oct. 28, 2022 10:30 AM - 12:30 PM

Room: 504a
Session chair: Albert Lan ,Applied Material

The Prospect of Global and Taiwan Economy
發表編號:S21-1時間:10:30 - 11:00

Invited Speaker

Jiann-Chyuan Wang, CIER

Ⅰ.Bizarre & changeful global economic development

Ⅱ.Global economic perspective

Ⅲ.Taiwan’s economic growth & uncertainty

Ⅳ.Important issues for next 10 years

IC Substrate (ICS)
發表編號:S21-2時間:11:00 - 11:30

Invited Speaker

Hayao Nakahara, President, N.T. Information Ltd. (Onsite Presenter:Shiuh-Kao Chiang , Managing Partner, Prismark )

Of top 25 makers in 2021, 13 are ICS Makers
Number of ICS makers decreases rapidly
Possibility of Recession
2021 IC PKG Substrate Production

The strong impact of compound semiconductors on the packaging industry
發表編號:S21-3時間:11:30 - 12:00

Invited Speaker

Shalu Agarwal, Yole Développement

This presentation will cover the impact of compound semiconductors on the packaging industry. We will outline deployed solutions, highlight the challenges, and analyze the current and expected market situation.

Enable Sustainability in the Electronics Industry
發表編號:S21-4時間:12:00 - 12:30

Invited Speaker

Tim Tsai, Director, DuPont Interconnect Solutions

DuPont Interconnect Solution business aims to be a total solution and system design partner for signal integrity and power transmission, leading in sustainability. The key areas for our sustainable interconnect solutions are innovation for green and sustainable chemistry, enabling the circular economy, and adopting renewable electricity. In 2021 DuPont Interconnect Solution achieved the milestone of 95 percent of global operations powered with renewable electricity. We have set the business ambition of Zero by 2030, reaching carbon neutral operations globally.


S22: Power Electronics

Oct. 28, 2022 10:30 AM - 12:30 PM

Room: R504b
Session chair: Albert Wu, Professor, NCU / Allen Liu, ITRI

Power Module Packaging & Thermal Management in EV Applications
發表編號:S22-1時間:10:30 - 11:00

Invited Speaker

Chun-Kai Liu, Principle Engineer, Industrial Technology Research Institute

1. Development Trend of EV and Power Semiconductors
2. Thermal Management of EV Power Moudule
3. System Level Thermal Design
4. Conclusion

Impact of Via Structure Toward Wire Bond Interconnect Quality
發表編號:S22-2時間:11:00 - 11:15

Lee Kuan Fang, Alex Schliebitz, Jakob Holfeld, Ng Hong Seng

Vertical interconnect access (VIA) is an electrical structure designed as a bridge between multi-layers metallization of microelectronic silicon wafer. As a conductive gateway between metal layers, via structure designated at all possible locations in a device base on integrated circuit (IC) routing requirement. As an effective current passageway, it is very common to have via structure fabricated underneath aluminum bonding pad. In the subsequent process of IC packaging, bond pad will be subjected to thermosonic wire bonding by using gold or copper wire. Certain devices will be subjected to ultrasonic wedge bonding of aluminum wire based on specific application. There is no direct contact of via structure and bonding wire in this entire process. Nevertheless, via underneath bond pad is optically observable as imprint on bond pad surface in some devices. Existence of via imprint leads to a quality inquiry of bond pad surface for wire bonding process. It was naturally assumed that via imprint will increase bond pad surface roughness as compared to bond pad without via structure directly underneath bonding area. In this study, test samples with various via structure design were selected for examination. The study involved attentive bond pad surface roughness measurement by using AFM analysis. Key surface roughness indicators (such as Ra, Rq, and Z-Range) were collected from wire bonding area of test samples. These measurements data are important to provide quantitative surface roughness conditions of test samples. On top of surface roughness, via structure density is also part of the research. Hence, test samples selected consist of bond pads with various via structure variants and bond pads with no vias underneath aluminum layer as a baseline. Via to via distance of the evaluated samples were 1.2µm and 1.4 µm. The samples also covered minor differences in term of via structure formation. Wire bondability study was the following step after bond pad surface roughness assessment. Impact of via-induced surface roughness toward wire bonding process was carefully evaluated. The conventional thermosonic wire bonding was performed by using 2N gold wire together with optimized parameters settings. This followed by standard bond quality check of wire bond shear test, wire pull test, as well as failure mode examination through optical microscope. These are important information to analyze impact of surface roughness and via density toward bondability. Results obtained from this evaluation enable better understanding of via structure’s impact toward wire bonding process. This also served as valuable information for IC product design, especially whenever application of via structure underneath bond pad is required.

Development and Power Loss Estimation of SiC-based Power Module
發表編號:S22-3時間:11:15 - 11:30

Yan-Cheng Liu, Hsien-Chie Cheng, Hsin-Han Lin, Shian-Chiau Chiou, Tao-Chih Chang

In recent years, countries are actively developing green energy, such as solar and wind power, to replace fossil fuels and set rigorous regulations for CO2 emissions from automobiles to safeguard the environment and achieve sustainable development [1-2]. Due to their ability to control the circuit and to convert electrical and kinetic energy, power semiconductor components/modules are used in the functions of frequency conversion, voltage conversion, current conversion, power amplification, and power management for electric vehicles (EVs), EV charging stations, unmanned aerial vehicles (UAVs), and green energy. The MOSFETs and IGBTs power components, such as inverters and converters, are widely used in power conversion systems, including renewable energy generation systems, three-phase motor drives for EVs, hybrid EVs, battery EVs, and industrial servo motors [3]. However, MOSFETs have the advantage of lower switching losses, lower on-state resistance, and higher switching speeds [4]. Despite the rapid development and numerous benefits of power modules, there are still many issues to be resolved, such as heat dissipation and reliability. Many related works of literature have been researched on issues related to power modules [5-6]. Furthermore, power semiconductor using wide bandgap (WBG) silicon carbide (SiC) and Gallium Nitride (GaN) as chip materials have lower switching times and losses as a result of advancements in material and process technology [7-10]. High breakdown voltage, high operating electric field, high operating temperature, high switching frequency, and low loss are all the advantages of WBG materials [11, 12]. Biela et al. [11] discovered that SiC power components perform far better than Si power components under high voltage and high temperature operating conditions. Thus, the SiC power components have become the preferred material for the next generation of power semiconductor devices, replacing the Si technology. Therefore, this research develops an SiC-based power module (see Fig. 1) with an output power of 12 kW and a switching frequency of 30 kHz to control servo motors of electric engineering vehicle. The developed SiC-based power module is divided into three different parts based on their functions: the brake circuit, the three-phase rectifier, and the SiC-based inverter, which consists of 12 SiC power MOSFET components. The primary objective of this research is to evaluate the power loss and switching transients of the SiC power MOSFET inverter during the three-phase switching operation in a 1200V/200A SiC-based power module through a fully integrated electromagnetic circuit (FIEC) co-simulation method. This FIEC model utilizes space vector pulse width modulation (SVPWM) control signal to achieve a three-phase switching operation. The power losses of the SiC-based inverter, including switching, conduction, diode, and reverse recovery losses. To conduct a precise study on the switching transients of power components, a curve analyzer is used to evaluate the temperature-dependent output and transfer characteristics of the SiC power MOSFET device, as well as the body diode characteristics. By incorporating an electromagnetic (EM) simulation, the effects of the parasitic parameters of the SiC-based inverter calculated at a 1 MHz operating frequency on switching transients and the power losses are also considered. In accordance with IEC standard of Double Pulse Test, switching transient waveforms at 600V drain voltage and 200A load current are utilized to validate the FIEC co-simulation (see Table 1). An FIEC model of a SiC-based inverter is shown in Fig.2, which is used to estimate the power loss during the three-phase switching operation through SVPWM control under a resistive load in a 12 Ω delta configuration with a 400V DC bus voltage and 30A load current, while the switching frequency and duty cycle of SVPWM control are at 15 kHz and 82%, respectively. The result of the power loss can be see in Table 2. The output waveform of the SiC-based inverter through FIEC model is further validated by three-phase inverter switching experiment (see Fig. 3). Finally, parametric analysis is used to study the effect of switching frequency on the power loss of the SiC inverter during the load cycle.

Thermal Design of SiC Power Module for EV/HEV Applications
發表編號:S22-4時間:11:30 - 11:45

Chun-Kai Liu, Chiu Po-Kai, Yuan-Cheng Huang, Ji-Yuan Syu, Yu-An Chou, Kuang-Hung, Wu, Wen-Yang Pan

Currently, the transportation sector contributes about 30% of greenhouse gas emissions annually. Electrifying the transportation sector to combat climate change is a major concern for governments and global automakers [1]. Power electronics (PE) converters in electric vehicles determine much of the vehicle's efficiency and power output. The efficiency directly affects the performance of a vehicle, such as the driving distance. Thus, improving the efficiency, while reducing the volume and weight of the powertrain system is an important trend in electric vehicles. The Department of Energy (DOE) in the US has set an efficiency target of 98% and a power density target of 100 kW/L for automotive PE by 2025. Thermal management solutions of power modules face new challenges in mitigating the increased heat flux in PE equipment due to increased power density. High heat flux can raise the temperature of power devices and ICs, which reduces reliability and efficiency, and can lead to failure. Power semiconductor devices are packaged into power modules, which are the core of PE converters. Silicon-Carbide semiconductor device has the benefits of higher breakdown voltage, higher current, higher operating temperature, higher switching speed, and lower switching loss over Si devices. It offers system-level benefits of high efficiency and power density to electric drivetrains. However, thermal management remains an important issue for the performance of SiC power modules. Thermal solutions of power modules can be implemented as indirect, direct, or double-sided cooling methods and can have a large impact on the performance of the system. The thermal design of the power module can be analyzed by numerical simulation and thermal measurement. The optimum thermal design of SiC power modules has significant effects on system performance.
In this paper, we studied the thermal design of the 1200V, 400A SiC power module for EV/HEV applications by numerical simulation and experimental measurement. The SiC power module has 3 phases of topology. SiC semiconductor devices are soldered on the AMB ceramic substrate, interconnected by Al wire bonding. The AMB ceramic substrates are soldered to a pin fin heat sink. Without the thermal interface material, the power module is directly cooled by the liquid flowing through the heat sink, as shown in Figure 1. The results of thermal simulation show that the most heat of SiC chips is conducted through the ceramic substrate to heat sink and then removed to liquid by convection heat transfer [5]. The liquid with a constant volume flow rate flowed through the inlet and outlet of the liquid jacket and the pin fin heat sink. The lower temperature at upstream chips and higher temperature at downstream chips in the flow direction, as shown in Figure 2. The flow resistance of the liquid inlet, outlet, and pin fin forms a pressure drop. Increasing the number of fins decrease thermal resistance, while increasing the pressure drop. The transient thermal resistance of the power module was measured by T3ster equipment, as shown in Figure 3. Thermal resistance calculated by simulation agreed with the experimental test result. We compared the thermal performance of the Si IGBT power module and SiC power module with simulation and experimental measurement. The optimum thermal performance of pin fin design and the effects of pressure drop are comprehensively studied.

The numerical study of mechanical improvement of the metal annealing process during the manufacturing of the IC backend Damascene structure.
發表編號:S22-5時間:11:45 - 12:00

P.Y. Sun, Cadmus C.A. Yuan and K.N. Chiang

 The demand for the high speed and smaller dimensions drives the IC industry to the advanced technologies, such as the Cu/low-k structure for low RC delay. Since the 2000s, industries have introduced the Dam easene process, including the chemical vapor deposition of the low-k material, chemical-electrical plating of the copper, and chemical-mechanical polishing process, and it is very different than the conventional aluminum-based process, and many new failure modes have been detected [1]. Up to now, the Cu/low-k structure has been applied to many applications.
 Chen and Jang [2] have revealed a two-stage Damascene process, which introduces the copper trace annealing process in manufacturing each metal stack. In the second annealing, the condition of the environmental temperature of 350-450℃ and the duration of 25-30 minutes is preferred. Moreover, Harman and Johnson [3]indicated that the annealing of the copper under the argon environment at 300 ℃ for 30 minutes significantly reduces the copper mechanical modulus.
 One of the essential root causes of the Cu/low-k structure reliability challenge is the tremendous difference in the mechanical characteristics of the copper and the low-k material. Compared to the conventional aluminum-based structure, the stiffness of copper is approximately two times higher than aluminum. On the other hand, the low-k material is roughly 8-10 times softer than the conventional silicon dioxide material. Considering the inversed high-rise building-like back-end-of-line (BEOL) structure of IC design, a large deformation is expected when the loading from the IC pad is detected, compared to the aluminum-based structure.
 Analyzing the IC manufacturing process, the wire bonding (w/b) process, which is a high-flexible and cost-effective process to enable the electrical interconnect to the exterior PCB, introduces the most axial loading to the BEOL. A typical w/b process comprises two stages: a vertical movement of the wire and a following ultrasonic movement to increase the bonding strength. During the w/b process, remarkable energy has been transduced to the IC BEOL through the w/b machine.
 This research establishes a set of transient finite element models to represent the mechanical impacts during the w/b process[4]. Moreover, a finite element model of the BEOL structure, which consisted of 7 layers of copper metal stacks and an aluminum pad to represent the current frequent-used technology, is established to investigate the stress pattern. A full w/b process, including the downward wire movement and the ultrasonic movement, is considered the external loading of the model. The results show that, although the ultrasonic loading introduces periodical stress propagation within the structure, the maximum stress increase is insignificant. Moreover, reducing the copper stiffness reduces the risk of copper stack failure.

Wire Boning Process Failure Risk Estimation of the Cu/low-k Structure using the Transient Finite Element
發表編號:S22-6時間:12:00 - 12:15

Jing Yu Wang

The Cu/low-k structure is attracted by the IC back-end-of-line (BEOL) designer due to its excellent electrical performance. Silicon oxide based low-k materials are preferred because the fabrication processes for these materials exhibit high IC compatibility with a high yielding rate. These low-k materials, e.g., the SiOC:H (Black Diamond), are fabricated by the chemical vapor deposition (CVD) based processes and are mostly amorphous and porous. Hence, the mechanical resistances of the low-k material, including Young's modulus and the fracture toughness, are often much lower than the conventional silicon oxide.

Delamination at the interfaces with low-k material is a critical issue for the reliability of IC backend structures[1, 2]. The mechanical characteristics of the low-k material can be tuned by precisely controlling the CVD process[3], and such mechanical improvement can be optimized by the numerical model[2, 4]. Hence, to maintain the robustness of the IC/packaging yield/reliability, it is important for the IC backend designer to draft a proper mechanical strength requirement for the low-k material manufacturer.
Considering the Cu/low-k failure, one of the critical processes is the wire bonding (w/b) process. Due to its flexibility and high yield, the w/b process remains the mainstream interconnect method for IC packaging. On the other hand, identifying the potential failure of the Cu/low-k structure remains a technical challenge, because the complexity of the IC backend structure and the point failure might propagate through time, which might interact with another layer/structure. Hence, the numerical approach is often proceeded to estimate the design risk and obtain the design requirements.

This research establishes a set of transient finite element models to represent the mechanical impacts during the w/b process[5]. Moreover, a finite element model of the BEOL structure, which consisted of 7 layers of copper metal stacks and an aluminum pad to represent the current frequent-used technology, is established to investigate the stress pattern. The results show that both the Cu/low-k design and the w/b process parameters, including the free-air ball (FAB) size and w/b capillary, influence the maximum stress of the Cu/low-k structure. It is suggested that the w/b process of Cu/low-k structure should be precisely controlled, compared to the conventional w/b process of the Al/SiO4 structure, to maintain the low stress level of the Cu/low-k structure.

High-strength and fine-grained pure copper foils for electronic components
發表編號:S22-7時間:12:15 - 12:30

Fu-Chian Chen, Chih Chen,

As a material with good electrical conductivity and low cost, copper has been widely used in electronic devices as conductors. With the continuous advancement of electronic devices, the demand for the behavior of copper is also increasing. Some electronic components operate under high power and long-term working environment. In other words, we need the copper not only to have good tensile strength behavior, but we also need it to have good electrical and thermal stability at the same time. As a part of electronic components, it still must maintain a certain degree of conductivity.

Alloys have always been an intuitive way to strengthen metals, but it can also drastically affect conductivity while strengthening. Therefore, our team is still committed to improving the mechanical properties and strength of pure electroplated copper foils by proper additives and electroplating parameters.

In this study we electroplated copper foils by rotary plating. We used iridium oxide and titanium wheel as electrode. By using multiple types of additives, we have successfully electroplated nanotwinned copper foils with a titanium wheel which the ultimate tensile strength can reach up to over 740 MPa. Figure 2 shows the microstructures of the as fabricated Cu foils and fine grains were obtained. The thickness of copper foils we electroplated is around 20 μm, the commercial electroplated copper foil with same thickness often behaves ultimate tensile strength around 400MPa.


S23:Advanced Packaging Ⅱ

Oct. 28, 2022 10:30 AM - 12:30 PM

Room: 504c
Session chair: CY Yang,Professor, NCU / D. S. Liu, Professor,NCCU

PCB Embedding for 150 GHz applications and beyond
發表編號:S23-1時間:10:30 - 11:00

Invited Speaker

Andreas Ostmann, Department Manager, Fraunhofer IZM

Frequencies of 150 GHz and above will be used for ultra high speed data transmittion in future 6G applications and for radar detection. The electrical connection of HF chips in this frequency range is a major challenge for packaging technology. These include e.g. B. the signal propagation between a beamforming chip and power amplifiers in a MIMO antenna module (Multiple Input Multiple Output) or the connections between radar chips and antenna elements.
  Embedding chips in a high-frequency printed circuit board combines very short connections with low signal losses with good scalability for low-cost mass production. A 39 GHz MIMO antenna module with a PCB-embedded beamforming chip will be shown as the result of a European funded project between industrial partners and Fraunhofer IZM. The manufacturing process and electrical characterization are presented. A 150 GHz antenna module with an embedded GaN power amplifier was realized in a strategic Fraunhofer project. Manufacturing processes and electrical properties are also shown here.
  In addition to the classic methods of transmitting high-frequency signals using strip lines or coplanar waveguides, hollow waveguides can also be used. Air-filled waveguides in printed circuit boards can be realized with different technologies. The biggest challenge is the development and manufacture of structures for coupling electromagnetic waves from striplines to waveguides. In a German cooperation project, waveguides in printed circuit boards and coupling structures were realized and characterized up to 110 GHz. Future applications of micro waveguides for very high frequencies are discussed.

Development of Automotive grade iBGA package for CMOS Image Sensors.
發表編號:S23-2時間:11:00 - 11:30

Invited Speaker

Tan Kai Chat, Principal Engineer – Package Development, onsemi

The Automotive industry has made big leap in advancement in the past 20 years with the introduction of hybrid and full EV vehicles; and more importantly the reduction in dependency of human intervention in driving thru implementation of driver assistance systems (ADAS) and autonomous driving (AD) technologies. These ADAS and AD rely solely on imaging camera to support applications such as pedestrian recognition, vehicle recognition, lane/junctions detection, traffic lights detection and driver fatigue detection in the cabin. All these features will help in keeping driving risk much lower and also helps our ageing society to continue to drive and be mobile.
These advancement have driven higher demand for image sensor packages that can meet the stringent automotive reliability. In this paper, we will present novel methods for packaging image sensor on laminate substrates and pushing the boundaries by increasing miniaturization to enable higher pixel counts towards technologies that enable higher image quality and functionality.
Studies in achieving a high assembly yield (especially in foreign particle control) and reliability will be presented. Top key challenges in qualifying this image sensors iBGA package and novel method to mitigate packaging risk will also be discussed.

Firewall Design for High Quality Electroplating Redistribution Layers on 600mm Panel
發表編號:S23-3時間:11:30 - 11:45

Boyin Wu, Mingtzung Kuo, Yuan-Feng Chiang, Jeffrey Yang, Jen-Kuang Fang

The quality of redistribution layer (RDL) dominates the electrical performance of semiconductor package. Theoretically, the RDL thickness uniformity control becomes more challenge as increasing the substrate size, especially on the 600mm panel platform. In this study, the dummy pattern around and across the panel, called as firewall, have been used to influence the electrical distribution, to overcome the electroplating copper thickness uniformity problem around the blank area, which is used to develop the high-quality fan-out panel level packaging (FOPLP). The experiment results show the RDL thickness non-uniformity can be improved by 21% and 31% by tuning the area and the metal density of firewall, respectively. This firewall tuning technology is useful to diminish the RDL thickness difference among all dies within the panel, which can be adopted in any high-performance large size panel level packaging.

A 2x2 Broadband Dual-Polarized Antenna Array using AiP Techniques for 5G mmWave Beamforming Systems
發表編號:S23-4時間:11:45 - 12:00

Wen-Chun Hsiao, Hong-Sheng Huang, Cheng-Yu Ho, Chia-Ching Chu, Sheng-Chi Hsieh, and Chen-Chao Wang

Majority of 5G NR can be grouped around one of three categories: Enhanced Mobile Broadband (eMBB), Ultra-Reliable Low-Latency Communications (URLLC), and massive Machine-Type Communications (mMTC), of which eMBB brings the advantages of 5G to the general public as it can deliver higher data rates internet access in previously challenging conditions.
In past years, many applications, therefore, are in the scope of eMBB such as mobile communication, HD media, macro/small cell, fixed wireless access, and many more. One of the eMBB applications is AR/VR/MR (Augmented Reality/Virtual Reality/Mixed Reality) fields. These devices are able to create 3D images by stimulating the user’s visual and auditory senses in order to create a realistic and immersive experience for the user. The most important issues regarding wireless transmission are low latency, high stable coverage, and high data rate requirements. The best solution is using the 5G FR2 spectrum, which is mmWave bands (like 28GHz, 39GHz, etc.). These bands have a significantly lower latency, higher network capacity, and higher throughput, as a “last-mile” wireless communication solution providing a high-speed and high-reliability connection to personal and business.
On the other hand, the mmWave bands have a shorter transmission range, limited coverage area and are more susceptible to signal loss due to weather or objects. Therefore, highly directional beamforming and massive MIMO antennas have become vital in commercial wireless communication.
Furthermore, the wavelength of mmWave is from 1mm to 10mm in the air. Antenna process can be designed from PCB level to package level. As the result, the antennas and ICs can be further integrated into one package, which is Antenna-in-Package (AiP) technology. This further provides very compact size, higher performance, lower power consumption, and more cost effective mmWave products, which are ideal for the above mentioned AR/VR/MR devices.
In this work, we implement a 2x2 broadband dual-polarized antenna array using AiP techniques for 5G mmWave applications. This design has been simulated using ANSYS HFSS program and parameters of substrate which were based on the extraction work in previous study. A stacked structure is designed and manufactured on the 4+2+4 substrate process with size of 13 x 13mm. This paper has analyzed and optimized the stack up ratio of the driving patch to the stacking patch, and added parasitic elements to expand the bandwidth, thereby achieving broadband characteristics on thinner substrates. We have also studied the effect of process tolerances on the performances of this design. In addition, these Dk/Df parameters of prepreg layer and core layer where extracted by T-resonators and patch antennas, respectively. When we have known these real parameters, we can avoid getting the performance deviation of antenna design such as impedance mismatching, resonant frequency and bandwidth shifting, etc.
The results show that structure provides a broadband benefit to cover the all 28GHz mmWave bands (n257, n258, and n261) of 3GPP standard. Dual-polarized feature is also achieved by different feed-in ports in vertical plane and horizontal plane. Within the bandwidth, this structure can get a good isolation between the different port. Thus, the signal channels can be separated from each other and allow data to be transmitted through both channels operating on same frequency without interference. Such a 2x2 MIMO configuration is the simplest and most popular architecture in the mmWave bands. Moreover, this antenna array presents the beamforming feature for beam steering applications. The simulation results show different beam direction by controlling the phase of each antenna element. Finally, a 2x2 broadband dual-polarized AiP is being implemented on 4+2+4 low cost multilayer substrate to verify the simulation and measurement results and expected to gain an agreement performance for 5G mmWave beamforming systems.

Laser Drilling & Plasma Descum Employed In The Process of Wafer-Level Chip Scale Package(WLCSP)
發表編號:S23-5時間:12:00 - 12:15

Jack Huang

Laser drilling is widely employed for PCB/FPCB production, especially for ABF/RDL substrates used for 5G telecommunication. Compared with the mechanical drilling which is usually used for the via diameter over 200um, laser drilling can fulfill the smaller via diameter amid 15um and 200um. Plasma descum and wet cleaning are the common post-processes after the laser drilling to obtain the better via quality by removing drilling residue and debris.
But traditional nano-second/pico-second lasers used in laser drilling may not drill well on the protective layer or redistribution layer(RDL) of the wafer-level chip-scale-package(WLCSP). Challenges including : (1) Bottom metal layer damaged or insulation layer peeling from the metal layer attributed to the severe heat-affected-zone(HAZ). (2) Via diameter smaller than 30um is unachievable. (3) Positional error below 5um can’t be secured while drilling at the faster speed.
This paper will demonstrate using the femto-second laser with the inherent feature of cold ablation to drill vias on the ABF layer and then carrying out the post-treatment of plasma descum to fulfill the requirements of higher taper angle and faster throughput. Advantages include : (1) Flesible drilling capability, via diameter is programmable in the range of 15um to 200um. (2) Undamaged and residue-free on the bottom metal layer. (3) Smooth via sidewall. (4) Continuous drilling can reach the speed of 3000 via/sec.

Effect of hybrid surface treatments on copper-to-copper thermal compression bonding
發表編號:S23-6時間:12:15 - 12:30

Liang-Hsing Shih, Wei-Ting Chen, Jenn-Ming Song

3D IC integration becomes one of the important trends in microelectronics manufacturing, and direct Cu bonding is considered an ideal way to achieve inter-chip vertical connections for TSV (through silicon via), due to size miniaturization and low electrical resistance. In this study, plasma was adopted to modified copper surface, and the effect of a subsequent light exposure was systematically investigated. Experimental results reveal that plasma bombardment contributed to a higher surface energy, especially those with H2-mixed gases. It also gave rise to compressive residual stress for copper surface, which led to an accelerated self-diffusion and improved bonding strength. With respect to plasma/flash combined treatment, only the N2-plasma samples showed enhanced bonding performance. For those treated with plasmas with H2 mixed gases, copper surface was highly activated and formed a thicker oxide layer which accounted for inferior bonding strength.


S24: HDI, IC Substrate and FPC Technology

Oct. 28, 2022 10:30 AM - 12:30 PM

Room: 503
Session chair: Chi-Shiung Hsi,National United University/ Irving Lee, Global Manager,UL

RF Circuit challenge of mmWave application
發表編號:S24-1時間:10:30 - 11:00

Invited Speaker

Jennifer Wu, Project Leader Engineer, ICHIA technologies, inc.

The mmWave Commerical promotes the doubling of the data transmission rate to 16Gbs. These performance improvements also affect the development of electronic products toward wireless, systematization, and lightweight. Therefore, the integration of electronic components has higher quality requirements for wireless transmission stability, shortened transmission distance, and reduced energy consumption. Under such performance considerations, RF (radio Frequency) circuit challenge of mmWave will be prersented form the perspectives of wiring, and interlayer connections on the circuit board.

Embedded Trace process by SCHMID
發表編號:S24-2時間:11:00 - 11:15

Laurent Nicolet

ET process by SCHMID has a new process which is capable to process line & space down to 2µm with an embedded trace technology based on the next generation of productions tools.

OBJECTIVE: Demonstrate a process capable to fit the actual and future requirements of Substrates & High-End PCB’s while taking into account the ecological and economical aspect of the process by using a green, Smartfab concept.

METHODS: Major process steps to reach the objective were newly developed. The creation of the trace into a non-fiber material like ABF or Polyimide is done by a Plasma-etching process. The newly developed system combines
a high selective anisotropic etching with none dust produced from the silica particles being present in the material (ABF). The metallization of the created pattern and holes are made by sputtering Ti or TiNx layer following a Cu seed. An optimized Cu plating process is filling traces and vias parallel. The following process is planarized and removing excess Cu from the surface. After that the boards will be ready for the next build up layer.
All major tools used in the ET Process are capable to handle panels up to 620x620mm (24”x4”) in a touch free mode.

RESULTS: Plasma etching of Polyimide is achieve with a speed over 1.5µm and for ABF material of 350nm/min as average etching speed. The depth of traces is 15µm with vias up to 60µm. The metallization of the pattern was made with TiNx following per Cu layer. Cu plating with a uniformity of min 94% for a plating thickness of 26µm simplify the CMP process.

CONCLUSIONS: ET by SCHMID is a process capable to cover the need for the actual and future demand of substrate & High-end PCB’s. The achieved results are showing a high potential for massive improvements in future board design like: Considerable increase in the mass of copper within the PCB, no limitation for the geometry and the quantity of holes and implementing 3D designs. This technology advantages are coming along with a new production tool generation including a smartfab concept to achieve massive saving on energy, chemistry, water and emissions.

Manufacturing Processes of Advancing 3-Dimensional Laser direct Ceramic (LDC) Circuits Boards by Laser Engraving
發表編號:S24-3時間:11:15 - 11:30

Chun Chieh Liao

As the rapid development of technology, the need for the ceramic circuit boards becomes more and more complicated. The traditional direct plating Cu (DPC) ceramics boards, which is patterned by the photo images and electro-plating technique, can only have the pattern on 2-dimensional surface. However, to increase the circuit density on ceramics boards, DPC technique does not meet the requirements of high-density circuits. To reach the high-density circuits on ceramic boards, 3-dimensional ceramic circuit boards are the trend in the future.
Due to the technical limitation of 2-dimensional DPC, it needs to come up with a totally different manufacturing process to achieve the 3-dimensional circuits on ceramic boards. To make the 3-dimesnsional circuits come true, a laser engraving technique which was called laser direct ceramic (LDC) was developed by Tong Hsing Electronic Industries Ltd. The main manufacturing processes of LDC contain five steps. Firstly, ceramic boards were cut by the saw and side wall of ceramic boards could be exposed and be processed. Then, the ceramic boards were sputtered by Ti/Cu seed layers on the top and bottom side. In the meantime, the side wall of ceramic boards was also sputtered by Ti/Cu seed layers. Thirdly, laser machine with 6-axis rotation stage was applied to engrave 3-dimensional pattern on circuit boards. Non-circuit area was engraved by laser and the Ti/Cu seed layers would be evaporated by the energy of laser. Besides, 6-axis rotation stage facilitated to engrave the side wall of ceramic boards and enabled to fulfill 3-dimensional circuits on ceramic boards. After that, the Cu thickness of conductor was increased by electro-less Cu plating or electro-plating Cu. Finally, the surface finish, such as electro-less Ni/Au, was plated on Cu surface to protect the Cu from oxidation and increase the solderability.
In conclusion, the assistance of laser machine with 6-axis rotation stage could make 3-dimensional circuits on ceramic boards and overcame the limitations of traditional 2-dimensional DPC process. The advancing manufacturing processes were proposed in this paper and the new processes could increase the density of ceramic circuits and widen the application of ceramic circuit boards.

Hydrogen Embrittlement Suppressors for Nickel-Free Electroless Copper Baths
發表編號:S24-4時間:11:30 - 11:45

Tobias Bernhard, Stefanie Manuela Bremmert, Sascha Dieter, Laurence John Gregoriades, Edith Steinhäuser

The deposition of a nanovoid-free electroless copper layer is one of the main quality criteria of an electroless copper bath. Without certain additives known to contribute to copper bath stability, copper deposit thickness and color, crystal structure, suppression of nanovoiding, etc., the properties of the obtained copper layer are unpredictable and uncontrolled copper growth can be observed.
Previous investigations have shown that nickel as an additive is one of the main drivers in suppressing hydrogen embrittlement (HE) and thus preventing nanovoiding, while other commonly used organic additives did not show any beneficial impact on suppressing HE.
Despite the advantages of nickel in this regard there are many reasons to substitute nickel as a HE suppression agent. The unavoidable incorporation of nickel in the electroless copper layer can lead to lower conductivity of the electroless copper layer and to lower throwing power in blind micro vias (BMVs). Moreover, a nickel-free electroless copper bath is also preferred in terms of high-quality BMV filling and is less hazardous to health and for the environment.
The report presents the results of a study carried out to investigate the impact of five different additives (A-E) on HE, surface morphology and epitaxy in a wide concentration range for a tartrate-based, nickel-free electroless copper bath. The additives chosen for these investigations belong to different chemical compound classes and can be categorized in organic and inorganic compounds (including transition metal complexes). To study the different effects of the additives on the deposited copper layer focused ion beam (FIB) and scanning electron microscopy (SEM) were utilized for examination.
Additive A shows a complete HE suppression over the entire concentration range studied without negatively affecting other copper deposit properties. For additive B and C, the HE suppression increases with bath concentration while the opposite is observed for additive D. Additive E demonstrates no HE suppression across the concentration range tested.
The results clearly demonstrate that certain additives are capable of completely suppressing the HE phenomenon and of providing thin, epitaxially grown and nanoscopically defect-free electroless copper layers with an optimal surface morphology for the subsequently plated electrolytic copper deposit. Additionally, the avoidance of the encapsulation of hydrogen during the copper deposition process results in a less nanopouros copper deposit, which minimizes the risk for delamination of the deposited copper.
Furthermore, the performance of these additives is comparable over a relatively wide concentration range (additive A: 50-200 ppm), which provides an additional advantage with respect to electroless copper bath handling and dosing. The present results moreover confirm that certain additives can reliably substitute nickel and overcome the HE phenomenon.

Next Generation Pulse Electroplating Copper Metallization for Advanced MLB
發表編號:S24-5時間:11:45 - 12:00

Crystal Zhang

5G network provides high data transmission rate, and will enable internet of things (IoT), autonomous vehicles, Virtual Reality (VR), etc. 5G wireless roll out requires more small-cell base station infrastructure to increase signal coverage. Networking and 5G wireless base station increase demand for advanced high layercount multi-layer boards (MLB) with higher routing density. In order to increase signal routing density, back panel board design trend is higher aspect ratio (AR), for higher board thickness with lower through hole diameter. In recent years, more and more customers are working on through holes with high AR > 16, while conventional AR is lower than 16. Major challenges for copper electroplating on high AR through holes are the balance among high throwing power, good uniformity which includes both the thickness uniformity inside through hole and also the uniformity of isolated features and dense features, together with high mechanical and thermal reliability.
Herein, we report our study on the development of next-generation pulse electroplating copper offering for advanced MLB. Electroplating copper formulation are mainly composed of inorganic additives (cupric ion, acid, and chloride ions), and organic additives (brightener, suppressors). The unique combination of organic additives provides strong suppression effects. In addition, the interaction between additives and pulse waveform has been studied by systematic design of experiments (DOE). Thermodynamics, kinetics, mass transfer, current distribution, and electrochemical crystallization are taken into account during pulse reverse plating, to achieve the balance between through hole throwing power and through hole uniformity. Furthermore, fundamental relationship between crystalline grain structure and plating conditions are investigated toward good mechanical and thermal reliability. The guideline for pulse plating parameters is established. In summary, this paper demonstrates an innovative pulse electroplating copper metallization package with high throwing power, good uniformity, and excellent reliability, for advanced MLB applications.

An Innovative Copper Electroplating Solution for High-Speed HDI Plating
發表編號:S24-6時間:12:00 - 12:15

Shih-Chun Huang

With the emerging development of high-tech applications such as consumer electronics, 5G network, artificial intelligence, and autonomous vehicles, the need of higher quality PCB manufacturing grows accordingly. Among all of PCB applications, high density interconnect (HDI) is one of the essential and fastest growing technology. In order to fulfill various customer’s need, critical challenges arise including higher throughput, wider and deeper via filling, higher aspect ratio through hole plating, and stricter than ever uniformity. To meet the above requirement, innovative plating formulated product is required for industrial development.
Herein, our study focuses on identifying key factors to simultaneously optimize via filling and through-hole plating. By leveraging design of experiment, machine learning, electrochemical experiment and plating verification, we summarized the primary factors and develop an outstanding electrolytic copper additive for HDI application. Proprietary design of organic additives provides excellent via-filling and through-hole throwing power even at 4 ASD. Besides the extraordinary performance, easy bath maintenance with this unconventional electrolytic plating solution is necessary. Moreover, this formulation offers a wide range of operating conditions and stable reliability to reinforce its high-quality manufacturing characteristics. In summary, this paper demonstrates an innovative electroplating solution for HDI applications.

Impact of Additives on the Recrystallisation of Plated Layers
發表編號:S24-7時間:12:15 - 12:30

R. Massey, T. Bernhard, K. Klaeden, S. Zarwell, E. Steinhaeuser, S. Kempa, F. Bruening

The use of electroless and electrolytic Copper plating has been readily adopted by the PCB industry since its onset, so much so that both processes are still considered as being “the best” of the available production techniques. However, as electronics becomes more pivotal in our daily lives, the range of safety and other critical applications is increasing significantly and there is a growing need to push product performance further and to then stabilize that performance at its maximum wherever possible.
While there is an extensive library of publications discussing both the physical testing and performance of various PCB technologies, these have been more recently complimented by disclosures relating to the microstructures found in their Copper layers and how these may also be somewhat influential. One item that has been highlighted within such work is the visibility of any interfaces within a plated structure, and how ideally this would not occur, with no discrete layers being apparent. It is assumed that such epitaxial structures are likely to offer the best opportunity for reliability performance due to a lack of significant macro and micro defects within the plated structure.
Within this paper we compare the influence of plating additives that have been applied to a commercially available electroless copper system and how their use impacts the morphology of the overall final plated structure. Through testing on insulating materials in addition to single and polycrystalline copper substrates, each electroless Cu solution is shown to be influential in suppressing grain growth in certain crystal orientations which can lead to significant physical differences across the final plated interface.
It is interesting to note that while the degree of epitaxy between the substrate Cu and the electroless Cu can be influenced dependent upon the additive utilized, this can occur independently of the impact between the electroless and electrolytic Cu. To wit, an epitaxial interface between the substrate and electroless Cu is not strictly indicative that an epitaxial structure will occur between the electroless and electrolytic Cu.
Through careful selection of the additive packages used within an electroless Cu system, there can be significant control gained over how not only the electroless layer itself crystalizes, but also the response of the subsequent electroplated layer as well. Both of these are understood to have significant impact on the physical and mechanical properties of such an interface, this in turn can be influential in achieving the desired overall properties such as microvia strength or a highly reflective plated surface as is often desirable to flexible PCB production.


S25: Advacned Design & Emerging Modeling

Oct. 28, 2022 13:30 PM - 15:30 PM

Room: 504a
Session chair: C.A. Yuan, Assoc. Professor, FCU / K-J Chung, Assoc. Professor,NCUE

RF Filter device Packaging Technology Trend
發表編號:S25-1時間:13:30 - 13:45


5G & 6G wireless communications are expanding spectrum bands into sub-terahertz frequencies, and RF front-end modules (FEM) are key devices for such frequency bands.
This paper introduces the RF filter device packaging technology trend with actual device tear-down study for understanding the next-generation technology approach.
And will discuss the key core technology of RF filter device packaging.

- Study of RF filter device packaging history with x-rays analysis
- Key RF filter packaging technology trends
- Wet chemical solution for RF device process

Keywords: RF filter device, 5G, X-rays analysis, AlN & Al etching rate

Warpage Analysis of IC Packages with Fine Pitch Substrate
發表編號:S25-2時間:13:45 - 14:00

Sheng-Jye Hwang

Some IC packages use lead-frame as the conducting interconnect and supporting carrier for dies. However, with the advancement of technologies, the demand for more interconnects in a package has been raised, and the available pin-count of lead-frame type packages is not high enough. Therefore, in the application field, substrate-based IC packages such as BGA (Ball Grid Array) or flip-chip are attracting more and more attentions recently. In past substrate-based-package simulation studies, substrates were commonly modeled as a single material layer with average material properties. This paper builds the RDL (Redistribution Layer) model in detail and makes the model as close as possible to the actual design.
This paper uses ANSYS trace import function to build a substrate mesh model, then uses Moldex3D to perform mold filling and post mold cure analyses on the complete package. P-V-T-C model, which considers both volume shrinkage due to thermal mismatch and chemical shrinkage, was used to predict the amount of warpage and residual stresses after the mold filling process. Next, the dual shift factor model for viscoelastic analysis was adopted to model the post mold cure process and predict the amount of warpage and residual stresses after the post mold cure process.
After comparison, it was found that results from both simulations and experiments agree well in both the warpage shape and amplitude after post mold cure process. In addition, it is found that the amount of warpage of each single unit at different locations in the strip is not the same. The magnitude of warpage values for each unit ranges from 9.4μm to 228μm.

Effective Modeling of Circuit Substrate for Flip Chip Chip Scale Package Using Trace Mapping
發表編號:S25-3時間:14:00 - 14:15

Wen You Jhu

Recently, to enable increased electrical performance, maximal I/O
density, and miniaturization, advanced packaging technologies such
as flip chip package on packaging [1,2] and flip-chip chip scale
packaging (FCCSP) [3,4] has emerged. In this packaging technology,
high-end chips are bonded onto a multi-layer circuit substrate. To
better comprehend the thermal-mechanical behaviors of the FCCSP so
as to assess its thermal-mechanical reliability [5,6] it is essential to
conduct detailed modeling and simulation of the multi-layer circuit
substrate. However, the circuit substrate is typically composed of a
great number of miniscule copper (Cu) pads and vias, and also various
Cu circuit layers surrounded by a prepreg (PP) dielectric material
together with a top protective material. Thus, it presents enormous
challenges and difficulties to straightforwardly and accurately model
the circuit substrate with multi-material and complex geometric
compositions using numerical approaches such as finite element
analysis (FEA). To ease the technical difficulty, effective modeling [7-
10] can be a very promising approach.
This study proposes a novel effective modeling approach to
accurately assess the equivalent material properties of circuit
substrates with complex geometry FCCSP. This effective modeling
approach integrates FEA, electronic computer-aided design (ECAD)
trace mapping (TM) technique [5-7], and a rule of mixture (ROM)
method [1,2,8-10]. This effective modeling is hereinafter termed
TM/FEA-based effective approach. The TM technique allows an
accurate, efficient and precise depiction of the microscopic, complex
Cu traces, pads and vias. A brief description of the TM procedure is
illustrated in Fig. 1. By this technique, the complex Cu traces and vias
in a Cu metal layer of the substrate in a high resolution ECAD model
are mapped onto a constructed three-dimensional (3D) finite element
grid with regularly- and uniformly-distributed mesh [1,2].
Furthermore, the ROM method is applied to estimate the average
element elastic properties, namely Young’s modulus, coefficient of
thermal expansion (CTE), and Poisson’s ratio, based on the volume
fraction of the Cu metal and the other material on each element. At
last, with the mapped Cu traces, vias and pads, together with the
calculated average elastic properties on each element, FEA is
performed to calculate the equivalent elastic properties of the Cu metal
layer. It should be noted that the Cu metal layer can be modeled as an
effective isotropic, orthotropic and anisotropic elastic material [11].
The above procedure is repeated until the effective elastic properties
of all the Cu metal layers in the circuit substrate are completed. At this
stage, a 3D finite element model of this circuit substrate with multimaterial
and complex geometric feature can be developed.
To demonstrate the effectiveness of the proposed TM/FEA-based
effective modeling approach, the calculated displacements under the
tensile and thermal loading are compared with those of several other
different approaches, such as the detail FEA modeling and the
conventional direct ROM averaging technique [4,5] that assumes the
Cu metal layer to be an isotropic elastic material. Besides, the results
calculated based on the effective orthotropic material assumption for
the Cu metal layer are also compared with those of the effective
anisotropic material assumption.
The predicted substrate’s effective elastic properties are further
utilized in the warpage process simulation of the FCSSP during
manufacturing [3,4]. The constructed 3D finite element model of the
FCCSP is depicted in Fig. 2 and the fabrication process of the FCCSP
is shown in Fig. 3. The modeled warpages are validated by the
experimental measurement data.
Table 1 and Table 2 reveals the comparison of the calculated
displacement results under tensile and thermal loading, respectively,
using four different models, i.e., detailed FEA, TM/FEA-based
effective modeling approach with the assumption of orthotropic and
anisotropic material, and conventional direct ROM method. They
demonstrate that the proposed effective modeling approach can offer
a much more accurate prediction of the thermal-mechanical behavior
of the Cu metal layer than the conventional direct ROM method. It is
also clear to see that the effective anisotropic material assumption for
the Cu metal layer outperforms the effective orthotropic one in the
prediction of its thermal-mechanical behaviors under tensile and
thermal loading. Moreover, the proposed TM/FEA-based effective
modeling approach can be also used to accurately evaluate the processinduced
warpage behavior of the FCCSP during fabrication.
It turns out that the proposed effective modeling approach can not
only give a very good prediction accuracy of the elastic properties of
the complex multi-layer, multi-material circuit substrate and the
process-induced warpage behaviors of the FCCSP during fabrication,
but also greatly ease modeling challenges and improve computational

Using Extra Trees Machine Learning Algorithm to Predict the Asymmetric Warpage Geometry of Panel Level Packaging
發表編號:S25-4時間:14:15 - 14:30

Z. Hsu, B. S. Wang and K.N. Chiang

In recent years, the market demand has resulted in the evolution of electronic components to be thin and multi-functional. Therefore, the related electronic packaging technology has also made considerable progress. Among them, Fan-Out Panel Level Packaging (FO-PLP) is a one of the options that can meet market demand, fan-out refers to the telecommunications connection between the chip and the circuit board through Redistribution Layers and Solder Balls. In addition, the fan-out package also saves many process steps, such as wafer bump, removal of flux, underfill and so on.
In this study, Finite Element Method (FEM) was used to build a 3D model, and the experimentally verified Equivalent CTE was used in the epoxy molding resin material. This is to simplify the curing reaction of the material. The resulting chemical effects such as volume shrinkage have finally successfully established a model for fan-out panel-level packaging. Although FEM can save a lot of time and cost compared with experiments, the results are often different due to human error, and the model must be re-established when the structure size is changed. Therefore, in order to reduce the above situation, this study uses machine learning (ML) to predict the amount of warpage at different packaging scales. First, a training database for fan-out panel-level packaging models of different geometric sizes will be established through the finite element method, and then machine learning will learn through these training databases. After learning, machine learning can quickly predict any geometric size panel Warpage value for level package.
In this study, an ensemble learning algorithm of Extremely Randomized Trees (ET) is used to predict the warpage value of the panel-level package. The algorithm is characterized by its fast operation for large-scale data. The database trains the algorithm, and finally the warpage value of the panel-level package can be predicted.
However, from many literatures, it can be found that the warpage of the fan-out panel level package is an asymmetric shape. There may be many reasons for affecting this result. For example, the thickness of the package epoxy resin is not uniform, and the thickness of the package epoxy resin will be different. There are different shrinkage rates. When the shrinkage rate of one side is different, it will affect the deformation behavior of other places, so there is a chance to produce asymmetric warpage. In addition, in the process of compression molding, the encapsulation epoxy resin is passed through the contact During the curing process, the encapsulated epoxy resin will shrink in volume, which will cause warpage and affect the contact area. Therefore, the heating temperature will be different, and the curing reaction of the encapsulated epoxy resin will be different.
Therefore, this study further explores the causes of asymmetric warpage, such as the influence of the process and so on. At the same time, a three-dimensional model is established by the finite element method to simulate asymmetric warpage caused by process differences.

Multiscale modeling of RDL-first FO-PLP utilizing the process-oriented simulation for warpage prediction
發表編號:S25-5時間:14:30 - 14:45

Chi-Wei Wang, Che-Pei Chang, Guang-Zhi Lin, Hao-Zhou Lin,Chang-Chun. Lee*

With the advantage of high I/O account, thin substrate, and good heterogeneous ability, the fan-out panel-level packaging (FO-PLP) has become a major topic for the future design of novel packaging. Despite of the enlarged area of the panel-level package, the process-induced warpage may cause a serious yielding problem in the subsequent process and assembly for the package. The process-induced warpage would be an urgent issue need to be solved for the FO-PLP. The coefficient of thermal expansion (CTE) mismatch between the materials is the main cause of the warpage. The process temperature for material is also a factor need to be considered. The tremendous cost of time for investigating the effect between materials through experiment is a problem that cannot be ignored. Therefore, the finite element analysis (FEA) is proposed in many researches to overcome the problem of time cost. Another issue is the discontinuous model and warpage after the sawing process from panel to stripe, and stripe to unit package. In this research, a redistribution layer (RDL) first FO-PLP is presented with integrated multiple scale of package model in FEA analysis. The complicated fine RDL and micro-bump is considered with the equivalent materials method and the equivalent stress-free temperature in the process-orientation simulation. The chemical shrinkage of molding underfill (MUF) is also concerned for the material characteristic. The effect of gravity cannot be ignored in the simulation due to the large area of FO-PLP. A rigid plane is constructed on the bottom of model to give a reference plane for the FEA. To give an entire process flow simulation, the saw process of panel to stripe and stripe to package is presented. The saw process must have a multiple scale problem in the FEA. Therefore, the multipoint constraint (MPC) is applied on the boundary of multiple scale model. The estimated warpage from the FEA is verified with measured warpage from experiment for three process steps, panel-level, stripe-level, and single unit package. The measured warpage of a single unit package is found that the position of package on the stripe-level would determine the warpage. The presented methodology for FEA also indicated the same results as the experiment. The warpage error between the simulation and experiment are below 10 %. Accordingly, the presented simulation methodology is validated, which can be utilized to estimate the warpage of FO-PLP. The factor and the material for the process can be further optimized based on the proposed methodology with FEA.

Measurements of Thermally-Induced Warpages and CTEs of Capped-Die Flip-Chip Packages Using Strain Gauges
發表編號:S25-6時間:14:45 - 15:00

Y. W. Wang, Y. S. Chou, and M. Y. Tsai

Heterogeneous integration using a silicon interposer has been increasingly applied to the advanced integrated circuit (IC) package such as 2.5D IC and 3D IC [1-3]. In order to monitor or measure package warpage, the high-cost commercial full-field shadow moiré or 3D-DIC [4] is usually used for those packages with a metal frame or cap on the top. A relatively low-cost and easy-to-use strain gauge measurement tool is newly proposed here for an alternative method for determining thermally-induced warpages and coefficients of thermal expansion (CTEs) of the capped-die flip-chip packages. The stiffness effect of the thermal interface material (TIM) of the capped-die flip-chip packages is also taken into account. The result suggests that the general back-to-back gauge measurement method on the top and bottom of the specimen would cause significant errors as the TIM inside the capped-die flip-chip package is relatively compliant. This study also further proposes a modified gauge method with a few related strain equations for those cases with compliant TIM to determine their curvatures and CTEs from the gauge measurement. With the good consistency of out-of-plane deformations from moiré and strains data from gauges, the model of the finite element method (FEM) are validated. It is further found from the FEM simulation that the curvatures and CTEs from the modified gauge method are in a good agreement with those from the effective one, and the out-of-plane deformations from the modified gauge method are also closer to the FEM ones than the effective method. As a result, it has been proven by experiments and simulations that the newly-developed modified methods of strain gauges are feasible and workable.
Keywords: Capped-die flip chip package, Thermal Warpage, CTE, Strain Gauge, Shadow Moiré, FEM.

Predict Reliability Life of Wafer Level Packaging Using GPR with Cluster Analysis
發表編號:S25-7時間:15:00 - 15:15

Chih Yi Chang

With the advancement of technology and consumers' demand for
electronic products, the technology of electronic packaging is
developing towards smaller sizes, lighter and thinner, and higher
performance. Before entering the market, electronic packaging
products will undergo a series of experiments to test their reliability.
Accelerated thermal cycling (Thermal Cycling Test) is one of the
reliability tests. The disadvantage of experimental detection is that it
takes a lot of time and human capital. This is for today's market
Finite element analysis is used in the simulation analysis of
reliability to improve the development time. A model that has been
verified by real experiments is used to simulate the package to obtain
a reliability life. In this study, ANSYS software will be used to
simulate the reliability of wafers and packages. The stress distribution
of the package is simulated by the application of a thermal cycling load.
The coffin-Mansion formula will be applied to calculate the reliability
life of the package. Bring the equivalent plastic strain generated on the
solder ball into the Coffin-Mansion formula to calculate the reliability
life. In addition, the mesh size is controlled for the most frequently
failed locations in the experiment to obtain more accurate simulation
values for comparison with the real thermal cycle experiment.
The finite element analysis still has its shortcomings. The models
established by different researchers often get different results. In order
to evaluate the reliability analysis of the package through simulation
analysis, professional background knowledge is required. To eliminate
simulation errors and reduce the difficulty of operation, this research
combines the application of artificial intelligence and machine
learning to estimate the reliability of the package body. The data sets
of different sizes and structures will be established by the finite
element model verified by the real thermal cycle test.
This research will apply the Gaussian process regression model for
data training to predict the reliability of the Wafer Level Chip Scale
Packaging (WLCSP). Initially, the simulation results will be compared
with experimental results of thermal cycle loading. With the verified
model, using the same modeling process, we will create a training
database that generates different parameters using FEM. This study
will explore the data effect of the Gaussian regression model on
different kernel functions. The study will also combine K-Means
clustering with an analysis of the time complexity of the Gaussian
regression model based on the amount of data.

The effects of time-dependent inelastic behaviors on the debonding of Cu-polyimide interface
發表編號:S25-8時間:15:15 - 15:30

Chien-Yu Wang, Tz-Cheng Chiu

Multilayered fan-in or fan-out redistribution interconnects are used extensively in advanced package designs for many state-of-the-art high-performance computing and portable applications. A common feature of the various redistribution interconnect designs is the high density of materials interfaces between metal conductors and ceramic or polymeric dielectrics. While the design offers significant benefit in electrical performance, the lack of strong bonds between the dissimilar materials leads to a higher risk in delamination failure under process and reliability test conditions. In the estimations of the mechanical or thermomechanical debond driving forces, an important factor to be considered is the time-dependent inelastic behaviors of metals and polymers. Under thermal or mechanical loading conditions, the energy dissipation in the layered structure is not only through the breaking of the weak chemical bonds at the dissimilar materials interface, but also through the viscoelastic and viscoplastic deformations of the polymer and metals around the interface. From the perspectives of the thermomechanical reliability and structural design of the redistribution interconnect, it is important to evaluate the contributions of the inelastic energy absorptions of the metal and polymer and their effects on the interface debond growth.
In this study, the influences of the viscoelastic behavior of polyimide dielectric and the viscoplastic behavior of Cu metallization on the debonding driving force of the redistribution interconnect is considered. The thermoviscoelastic constitutive behavior of the polyimide thin film was modelled by using a generalized Maxwell model with time-temperature superposition scheme. The viscoplastic behavior the Cu interconnect was considered by using the Anand model. A finite-element based numerical model was developed to evaluate the debonding growth at the Cu-polyimide interface. The model was first applied to evaluate the energy dissipations of the inelastic materials and their influences on the debonding strain energy release rate under either Mode-I or mixed-mode loading conditions. The effects of temperature and loading rate on the partition of energy dissipation through interface separation, viscoelastic and viscoplastic deformations were also discussed. The model was then applied to investigate an interface crack in redistribution interconnect under thermomechanical load. The numerical procedure developed in this study can be implemented to enable a quick evaluation of the interconnect geometry and materials selection for package design and process development.


S26: Advanced Packagng Process and Design

Oct. 28, 2022 13:30 PM - 15:30 PM

Room: 504b
Session chair: MY Tsai , Professor, CGU / Jenn-Ming Song,Professor, NCHU

Adhesion and Reliability Study of Different EMC and Pre-plated Leadframe Surface Combination for Au and Cu wire bonded Leadless Package
發表編號:S26-1時間:13:30 - 13:45

April Joy Garete

In this study, different molding compounds and pre-plated leadframe surface combinations were characterized in terms of adhesion and its impact on package delamination. Furthermore, Au and Cu wire bonded devices assembled using different EMC and leadframe surface treatment combinations were also assessed to evaluate the quality and reliability performance of these BOM as packaging materials for a DFN package. Key features of the different molding compound materials investigated in this study includes advanced formulation for improved delamination resistance, better fluidity, and copper wire compatibility.
Full material characterization was conducted to compare the physical and thermo-mechanical properties of the EMCs. Button shear test on standard and rough pre-plated lead frame surfaces was then performed to compare the interfacial adhesion performance and typical shear failure modes of various molding compounds. Adhesion data was further supported by subjecting the assembled of DFN package with different BOM combination to Moisture Sensitivity Level 1 (MSL1). Scanning Acoustic Microscopy (SAM) was then used to check the delamination performance on all mold interfaces at zero hour and after MSL1. The delamination level difference between samples built with different EMC types and pre-plated leadframe combinations were summarized in this study.
A 23um diameter Au-wire and Cu-wire bonded transistor was used as test vehicle to evaluate the material reliability performance on package level. Moldability check was done to inspect any external voids, incomplete fill, or wire sweep occurrence for all BOM combinations. Reliability performance was assessed by subjecting the assembled units to 1000 cycles Temperature Cycling Test (TCT), 96 hours Highly Accelerated Stress Test (HAST), and 1000 hours High Temperature Reverse Bias (HTRB) at a junction temperature of 150°C. Overall, the material study was able to successfully assess the adhesion, moldability, delamination and reliability performance of different molding compounds and pre-plated leadframe combinations on Au-wire and Cu-wire bonded DFN package.
Keywords: adhesion, reliability, epoxy molding compound, pre-plated leadframe, Au and Cu wire

Effect of Package Singulation Parameters on Dual Flat Non-leaded Package Delamination
發表編號:S26-2時間:13:45 - 14:00

Siying Wu

With the evolution of electronic field, the reliability requirement of package is getting stringent. The package is required to work and maintain good performance under extreme conditions. Interfacial delamination is one of the key factors that destroy the reliability of electronic package. When the delamination occurs between lead frame (LF) and epoxy molding compound (EMC), the moisture will ingress into the package and cause popcorn phenomenon, which eventually induce package crack and lead to electrical failure.

To improve the delamination performance and enhance the stability of Dual Flat Non-leaded (DFN) package, the effects of package singulation parameters on package delamination performance were investigated in this study, using different types of blade, saw method, spindle speed, feed speed and waterflow rate. After singulation, the package outlook quality was checked using Microscope, were tested by Scanning Acoustic Microscope (C-SAM) with C mode. And the delamination defect number was count after C-SAM. To further investigate the reliability of sample, the moisture sensitivity level (MSL) test was used to accelerated sample ageing (24h bake under 125°C, 158h moisture soak at 85C/85%RH and three times reflow). Besides, take the cross section of delaminated sample and observed the delamination gap under Scanning Electron Microscope (SEM).
As the result shows, the grit size of saw blade is one of the impact factors in delamination. The blade with large grit size will cause more stress on the package and lead to delamination during singulation. The saw methods also have effect on delamination performance. The chopper cut and normal cut method were used in the same type of package to compare the delamination performance. The results of C-SAM show the normal cut has better delamination performance than chopper cut. In addition, the delamination performance deteriorated with increase of spindle speed, which is related to the adverse impact of blade at high spindle speed and heat generation of friction. During blade singulation mechanism, heat was generated at few hundred degree Celsius temperature, causing EMC and LF expand and contract, creating a stress which reduced the adhesion strength between EMC and LF. And the feed speed has no significant in delamination performance. Besides, an interesting phenomenon was observed, the delamination performance improved with increase of water flowrate. The saw blade was cooled by water flow which can reduce the frictional thermal stress during singulation process.

To sum up, the effect of package singulation on delamination defects are present in this study. The blade with small grit size can reduce the stress between blade and package. And the delamination performance can improve by suitable saw method, low spindle speed and large water flowrate.

Keywords: Singulation, Blade type, spindle speed, feed rate, water flowrate

A Sn-Bi-X low-temperature solder design with high ductility
發表編號:S26-3時間:14:00 - 14:15

Ahmad Kholik, Yu-chen Liu, Chih-han Yang, and Shih-kang Lin

Currently, the Sn-Ag-Cu (SAC) solder system has been widely-used in electronic packaging. The typical reflow temperature of 250℃ in applying the SAC solder as interconnections causes warpage issue in advanced packaging. The warpage issue causes the alignment fault between chips and boards, and thus decreases the reliability of the electronic products. Low-melting temperature solder material has been proposed as a solution in reducing the reflow temperature in order to solve the warpage issue. Material systems such as Sn-Bi, Sn-In, Sn-Zn are considered as potential candidates in replacing SAC materials. Among the all, Sn-Bi solder material has its potential for real applications due to the cost, and processing feasibility. Nevertheless, the segregation and coarsening of (Bi) phase causing brittleness leads to the mechanical property degradation of the solder. Typically, Sn-Bi-based solder exhibited an elongation decrease after the it was aged at elevated temperature in mimicking the thermal cycling test. Research has proposed that element doping in Sn-Bi solder is one of the ways to tailor the material properties. Elements doping effect such as In, Zn, Ga, Ag, Al, Ti, etc., have been studied. In this study, we proposed a Sn-Bi-X solder alloy which exhibited an ultimate tensile strength (UTS) of 38.1 MPa and elongation of 274.3 % after thermally aged at 80℃ for 3 weeks. The tensile test was performed at the strain rate of 0.33 mm/min. The as-cast alloy exhibited UTS of 42.3 MPa and elongation of 148.5 %. The elongation of the designed alloy did not degrade after the aging test. On contrary, the elongation was further improved ca. twice times and UTS only decreased in a minor manner. The solidus temperature was 79.4℃ while the liquidus temperature was 130℃. Series of scanning electron microscopic, electron backscatter diffraction, and x-ray diffraction were performed to study the microstructure evolution. The mechanism of the superior elongation of the designed alloy is pursued in the present work.

3D IC packaging design may take a village but starts with a netlist
發表編號:S26-4時間:14:15 - 14:30

Tarek Ramadan

The semiconductor industry is facing an inflexion point as higher cost, lower yield, and reticle size limitations drive the need for viable alternatives to traditional monolithic solutions, which are hitting or coming close to the limits of manufacturing and physics. Integrating multiple dies and substrates into a single package is an increasing focus and practice of the semiconductors industry. Compared to the traditional transistor scaling approach, advanced packaging promises improved form factor, cost, performance, and functionality as well. One common approach is the use of 2.5D-IC technologies to connect multiple dies side by side using an interposer which can be silicon-based or organic. Equally common is the use of fan-out wafer level packaging technologies, where multiple dies are connected through the package RDL routing.

For the past few years, the emphasis has been on the heterogeneous aspect of advanced packaging. That is, multiple dies manufactured using different technology nodes are integrated into a single package.
However, recently, slicing a big monolithic SoC into chiplets and connecting these chiplets through a silicon interposer is gaining significant traction as well. This approach supports a new integration paradigm in which designers can mix and match already-built blocks (hard IPs) into their products. Moreover, it shifts the attention back to silicon interposers, which had been considered by many a too-costly integration option given the technological aspects involved.
The full commercial productization of these advanced packaging options requires the assurance of both an acceptable yield and correct (as intended) functionality. This assurance, like that for integrated circuit (IC) designs, depends on the availability of proven and qualified methodologies and workflows that can be used by semiconductor design teams to build products with confidence. In the context of physical verification, designers need to confirm that the full assembly (available in a manufacturing format) is connected as expected (as compared to the design intent, which is captured in the system-level design before physical implementation). To run assembly verification, the designer should first be able to capture the 3D IC assembly connectivity as intended. This can be a challenge as each substrate of the assembly can be owned by a different design team.
As 3D IC assembly verification requires a system source netlist, a designer needs to make sure that he or she can capture the full, intended connectivity of the die, silicon interposer, and organic substrate. The silicon interposer is usually owned by an IC design team with an IC design background and uses IC design tools and formats. Meanwhile, the organic substrate is usually owned by the package design team that has a traditional package design background and related design tools and formats.
Typically, the organic substrate connectivity is captured in a CSV file that basically includes the package bump (x,y) locations, pin names and numbers, and net names. On the other hand, interposer connectivity can be captured in many ways. For years, the interposer design methodology has been considered borderline IC/package design.
However, recently, a significant number of designers have begun to build silicon interposers similar to how they build digital SoCs. This is done by using automatic place and route (P&R) methodologies, which means that the interposer connectivity is usually captured in a Verilog netlist format.
To capture both the connectivity of the silicon interposer (Verilog) plus the connectivity of the organic package (spreadsheet), a system-level connectivity planning and management platform is essential. Designers need an aggregation platform that can consume different connectivity formats, allow users to modify and assign connectivity (either interactively or batch), and, eventually, combine the different netlists and generate a single system-level netlist that can drive 3D IC assembly verification
In this paper, I will discuss and present a methodology, process and platform for the robust capture and definition of a complete 3D package assemblies netlist which will become the “golden” system netlist that can then be used to drive all downstream verification activities

Stretchable piezoresistive strain sensors based on gold nanoparticle films for highly sensitive human pulse sensing
發表編號:S26-5時間:14:30 - 14:45

Wei-Rong Yang

The principle of commercial pulse diagnosis devices is attaching a radial sensor to the artery position, where the arterial pulses introduce stress or strain to the sensor, causing periodic voltage change or resistance change. The pulse wave can thus be transduced and recorded in the form of electrial signals. In order to enhance waveform resolution, the improvement of sensor sensitivity is still an ongoing issue. Over a decade, intensive efforts have been devoted to build flexible sensors using conductive nanomaterials based on piezoresistive mechanisms. In this study, highly-sensitive piezoresistive strain sensors based on gold nanoparticle thin films deposited on a stretchable PDMS substrate by centrifugation were developed to measure arterial pulse waveform. By controlling carbon chain length of surfactants, pH value and particle density of the colloidal solutions, the gauge factors of nanoparticle thin film sensors can be optimized up to 677 in tensile mode and 338 in compressive mode, while the pressure sensitivity up to 350. Low pH and thin NP films produce positive influences to superior gauge factors. It has been demonstrated that nanoparticle thin film sensors on PDMS substrates were successfully applied to sense arterial pulses in different body positions, including wrist, elbow crease, neck, and ches.

Interfacial Analysis on Microelectronic Packaging: Voids Observation and Crystallographic Analysis at Bonding Interface on Fine-pitch Cu-Cu Hybrid Joints by Cut-and-view Techniques
發表編號:S26-6時間:14:45 - 15:00

Jia-Juen Ong

Lead (Pb) free solder has been used as bonding materials in microelectronics packaging known as transient liquid phase diffusion bonding (TLPDB) for the last few decades due to its excellent reliability, process cost, and form factors. To increase the performance of transistors, a larger amount of inputs/outputs (I/Os) is needed which is known as Moore’s law. Thus, the dimension of I/Os must be significantly decreased. In addition, solder microbumps have intrinsic issues such as side wall wetting, whiskers, bridging, eventually resulting in circuit failures. Recently, the potential in scaling with excellent electrical properties of Cu-Cu bonding has been reported. Furthermore, filling the molding compound into the gaps between Cu joints to prevent further oxidation has become a great challenge. Currently, metal/dielectric hybrid bonding could be one of the best solutions to fabricated ultra-high density I/O devices with excellent bonding strength and electrical properties. However, defects (voids) in the bonding interface are unavoidable due to the atomic diffusion in metals. It has been reported that the electrical resistance of devices is highly related to interfacial voids. Thus, interfacial analyzing tools for void observation at the bonding interface are crucial. In this study, we demonstrate a continuous etching quasi-in situ observation using focused ion beam (FIB), scanning electron microscope (SEM), and electron backscattered diffraction (EBSD). Results show the reliable data of void quantization and variation in size and distribution at the bonding interface.

Enhancing Cu/Sn3.5Ag/Cu transient liquid phase soldering mechanical properties with element addition
發表編號:S26-7時間:15:00 - 15:15

Zih-You Wu

Recently, the transient liquid phase (TLP) bonding process has become a promising method in advanced electronic packaging. Full intermetallic compounds (IMCs) joints provide good strength and reliable high-melting point phase after bonding. However, Kirkendall voids accompanied with Cu3Sn and the strong preferred orientation of Cu6Sn5 may deteriorate the reliability in conventional Cu/Sn/Cu bumps. To resolve these problems and further enhance the mechanical proprieties, Ni and Zn are used to modify microstructures of the TLP bonding. Moreover, microstructure, grain, and mechanical analyses are employed to elucidate the mechanisms behind the strengthening effect of Ni and Zn in Cu18Ni/SA/Cu and Cu18Ni18Zn/SA/Cu bump.


S27: Advanced Substrate/PCB Process and Manufacturing

Oct. 28, 2022 13:30 PM - 15:30 PM

Room: 504c
Session chair: Shu Huang, Division Director,ITRI / John Liu, Consultant, TPCA

IPC Test Method Standard - Measuring High Frequency Signal Loss and Propagation on Printed Boards with Frequency Domain Methods
發表編號:S27-1時間:13:30 - 14:00

Invited Speaker

Jimmy Hsu, Principal Engineer, Intel

- Background
- De-embedding challenges and the Eigen-value based de-embedding methodology
- Probing Solutions
- Accurate reporting of insertion loss performance by physics-based fitting
- Addressing the Quality of Reported Insertion Loss
- Environmental Impact on Insertion Loss
- Summary

RDL Copper Plating Process for Panel Level Packaging Application
發表編號:S27-2時間:14:00 - 14:15

Maddux Sy, Sean Fleuriel, Confesol Rodriguez, Kesheng Feng

Advanced packaging suppliers are having two primary challenges during IC substrate fabrication, meeting the requirements on copper plating performance and reducing the cost from manufacturing process. The requirements on plating performance include both high resolution and strict height uniformity within a die (WID) and within a panel (WIP), consistent deposit grain structure and great copper physical properties to meet reliability requirements. The plated features include fine lines, trenches and vias, whose top shape and coplanarity are critical to the product quality. A non-planar surface could result in signal transmission loss and introduce weak points in the connections. Therefore, copper plating solutions providing uniform, planar structures, without any special post treatment are highly desirable features from RDL plating processes. The copper plating solution can also reduce cost by plating two or three types of features in a single electrolyte, this flexibility allows fabricators to save on space and equipment
In this paper, an electroplating package, Systek UVF 200, is introduced to plate RDL under different current densities in vertical continuous platers (VCP) or high-speed panel plater. The plating uniformity and coplanarity of both RDL fine lines and vias was evaluated on a panel level.
The Systek UVF 200 package offered excellent coplanarity within a pattern unit or die for RDL plating. The variation in the plated height (or thickness) between fine lines, as low as 9 µm in width, and pads, was below 2.0 µm when using a current density below 3.0 ASD to obtain the plated copper thickness around 12 µm. For 14 µm wide lines, the plated copper thickness variation can be below 1.0 µm. Under higher plating CD, such as 4-6 ASD, the plating thickness variation can be below 2.0 µm. The variation of plated thickness across 510 mm x 515 mm panels was below 10%. The tops of the fine lines have defined, slightly domed shapes, these types of profiles have excellent conductivity.
Physical properties of the plated copper deposit are essential for the reliability of the finished product. A few key physical properties are tensile strength, elongation %, and internal stress. These properties show the tolerance of the deposit for thermal stress and warpage. The additives (wetter, brightener, and leveler) strongly influence the physical properties of the deposit. Copper deposited with the Systek UVF 200 package has tensile strength above 40,000 psi, elongation % above 18%, and internal stress below 1.0 Kg/mm2. The physical properties of the deposited copper did not change considerably during the bath aging, showing that the package has stable performance.

Printed Circuit Board (PCB) Routing Optimization with an Innovative Edge Connector for PCI-Express 5.0 and Beyond
發表編號:S27-3時間:14:15 - 14:30

Huafang Ju, Xiang Li, Jimmy Hsu, Shaohua Li, Thonas Su, Mo Liu, Kai Xiao

PCI-Express (PCIe) data rate continues to double generation by generation from Gen4 with 16Gbps, Gen5 with 32Gbps to Gen6 with 64Gbps in recent years. However, data center motherboard form factor and landing zone requirement remain the same, which implies all enablers in channel need be improved to meet the maximized board routing length. PCB and connector are important components in channel, in addition to perspective performance, board designers should also pay attention to connector pin field PCB footprint design, which can cause full channel solution space variation and PCB cost difference.
Surface Mount Technology (SMT) connectors are adopted for PCIe Gen5 to enhance the electrical performance, different from Plating Through Hole (PTH) connectors, SMT sits on PCB pad by reflow soldering, and the pin side lead-in/break-out has two routing directions: toe side entry from front of the pin contact and heel side entry from back of pin contact. The two options of footprint routing entry cause different pin-pad stub length because the bifurcation point between connector pin and PCB pad is not in the middle of the rectangular pad. Toe routing with shorter pin-pad stub is recommended. Heel routing led to the longer stub degrading channel solution space significantly.

The heel routing cannot be completely avoided in some designs where the connector must be placed on very edge of a board because of routing density, mechanical limitation, or other reasons, which implies the board space is not sufficient for toe routing. It usually occurs on some high-density baseboards, riser cards or Graphics Processing Unit (GPU) switch boards.

Two approaches are proposed in this paper to mitigate these longer stub design issues. The first is to apply PCB via in pad plating over (VIPPO) process to reduce the routing stub. The other is to adopt an innovative connector with a row of pins flipped to have the heel entry flipped to toe entry without routing direction changing.

In this study, PCIe Gen5 card electro-mechanical (CEM) connector is addressed as an example, and full channel simulation based on two connector riser topology shows that the reduction is greater than 10% on eye height and eye width with heel entry compared to toe entry. VIPPO and new innovative connectors are also analyzed in this channel and the two approaches show comparable electrical performance with toe routing. In terms of cost, VIPPO has about 7% PCB cost added by complex manufacture process, and there is no additional cost increase by adopting innovative connectors as a satisfactory solution, which has already been manufactured by two connector suppliers. PCB design optimization was conducted for SMT connector to meet this high-frequency connector design up to 32GT/s.

The inventive adhesion promoter system for ultra-fine line package substrates
發表編號:S27-4時間:14:30 - 14:45

Thomas Thomas, Christopher A. Seidemann, Wonjin Cho, Cedric Lin, Patrick Brooks

To ensure good adhesion between conductor tracks and dielectrics is very essential in package substrates manufacturing. Currently, surface roughening process is the predominant method for bonding enhancement, due to providing a strong mechanical interlocking between roughened conductor tracks and dielectrics. Driven by increase of design complexity and growing demand for high I/O in package substrates, the dimension of conductor tracks L/S is reduced gradually to 5/5 µm L/S and lower. The conventional approach to ensure good adhesion by only rely on mechanical anchoring is no longer suitable. Excessive etching of conductor tracks from the roughening process has detrimental effect on the line integrity, hence creates inevitable functional failure. A new way of bonding enhancement process needs to be developed, and this must be independent from the surface roughness. For this reason, various processes have been developed with organosilane as adhesion promoter, where a synergy of mechanical and chemical bonding occurs to improve bonding strength and thermal reliability. Nonetheless, introduction of organosilane on conductor surface prior to polymeric material lamination has failed to provide good resistance to thermal shock and chemical leaching. This work focuses on the development of a novel organic pre-coating prior to organosilane adhesion promoter to improve thermal shock and chemical resistance property of the interface, without negative consequence to the adhesion performance. Several surface analytical methods are used to derive the presence of nano structure and adhesion molecules on the conductor surface such as AFM, FESEM and FTIR. With the suitable chemical entity and concentration of organic pre-coating on the surface, the resistance against thermal shock and chemical leaching are significantly improved. A unique zero conductor line width reduction of the process is very suitable for ultra-fine line < 5/5 µm L/S package substrates manufacturing.

A Methodology to Resize the PCB Differential Pair Routing Automatically
發表編號:S27-5時間:14:45 - 15:00

Ian Chu

This paper describes and discusses the method used in the differential pair line layout of the printed circuit board (PCB) to resize its width and spacing when PCB stack-up type or material is required to change.

Formerly, while developing differential pair circuits of PCB there always came along with sudden requests to change PCB stack-up type, material, or the number of layers.

In the realization of these kinds of requests there are many problems encountered, which resulted in a lot of time spent by layout engineers to remove and reroute differential pairs manually.

To resolve the problems mentioned above, we devise a method named reference polygon. Comparing it with popular industrial layout tools, this reference polygon method not only has an intuitive operation to layout engineers who are asked to realize the requested values of impedance in each layer but also has a unique design, especially in resolving arbitrary degrees and serpentine line routing.

Keywords: PCB stack-up, Differential Pair, Reference Polygon

A robust collaborative demand fulfillment framework for demand planning and production planning to empower smart production in printed circuit board industry
發表編號:S27-6時間:15:00 - 15:15

Hsuan An Kuo

The global economic boom of automotive market has been starting to recover optimistically from COVID-19. The market recovery of automotive chip demand is expected to grow with high demand and cross among all regions including customer behavior, business revenue, and numerous aspects of corporate operations. The advanced technologies including cloud computing, artificial intelligence (AI), big data analytics, and Cyber Physical System (CPS) boost the technology diffusion of intellectual devices and automotive electronics, enhancing the demand of PCB products. It becomes an important issue for players in the supply chain to adopt the technology migration of embedded power printed circuit board (PCB) technology in PCB industry with a robust solution framework. Facing the dynamic global market, companies have to ensure the production planning decisions is capable of fulfilling customer demand on time to achieve higher profitability and competitiveness. With the shortening product life cycle and increasing supply chain complexity, it becomes a great challenge to derive an accurate forecast result. The overestimate of the demand results in the waste of the capacity costs and work-in-process (WIP) costs, while the underestimate of the demand decreases the customer satisfaction and revenue. To deal with the risk of oversupply, shortage and production costs from the forecast bias, this study proposed a collaborated decision framework that considers both demand forecasting and robust production planning model for production system resilience. For demand forecasting, this study incorporated statistical and computational intelligence forecast methods, which the inherent and non-stationary characteristics of the time series data can be captured by the proposed forecast model including autoregressive integrated moving average (ARIMA), exponential smoothing (ETS), long short term memory (LSTM) and support vector regression (SVR) as a combinational method for demand forecast. Based on the results from forecasted demand with related forecasted errors in the rolling planning horizon, both additive and multiplicative Martingale Model of Forecast Evolution (MMFE) are applied to adjust forecasted demand and generate a more accurate demand realization threshold as the input for robust optimization model. The robust optimization production planning model aims to minimize the risk of backlog costs, WIP costs and inventory costs in production planning. For validation, considering realistic demand scenarios, the study constructs a multi-paradigm simulation model to investigate the performance of the proposed approach with conventional solutions. Based on empirical scenarios, practical viability of the proposed approach was validated. The results have shown robustness and practical viability for the proposed model under demand uncertainty.

Environment-adaptable Printed-circuit Board Positioning using Deep Reinforcement Learning
發表編號:S27-7時間:15:15 - 15:30

Carlos Solorzano, Du-Ming Tsai

The Printed-Circuit Boards (PCB) industry has held one of the most advanced manufacturing technologies, as the size of electronic components tends to decrease. Visual inspection for quality control and automatic assembly are key to improve efficiency in manufacturing. Alignment or positioning is only the first stage in a manufacturing line for assembly or visual inspection tasks. A precise and fast object positioning can ensure the successful visual inspection between a test image and a golden reference image. Vision-based techniques and methods are commonly used in the industry for assembly and inspection tasks. Many methods have been proposed to tackle the problem, either by traditional machine vision or by deep learning techniques. The traditional machine vision methods rely on template matching or feature point correspondence. They are computationally intensive and are easily affected by illumination changes and noise. Deep learning models such as Convolutional Neural Networks (CNN) are computationally very efficient but are also sensitive against environmental changes. They need to be trained with all possible environmental conditions or scenarios. Samples must be collected manually, as some samples can not be simply augmented digitally. Synthesized lightning variations are generally linear, but real lightning changes are non-linear and dynamic. In this article, a deep Reinforcement Learning (RL) model based on the Actor-Critic style Proximal Policy Optimization (AC-PPO) algorithm is proposed. The proposed method is applied for the positioning of Printed Circuit Boards (PCB) in images. The model uses as the current environment the input sensed image and the reference template as a guide. It requires only a single manually marked template in the reference image. All possible training images are automatically and randomly generated during the neural network training without human intervention. The model outputs the estimated geometric transformation parameters of the input sensed image. The proposed RL model is shown to be adaptive to unseen environmental changes or conditions, including illumination, noise, de-focusing and template occlusion, compared with the CNN regressor. Experimental results indicate that the proposed model on average can achieve estimation errors less than 1 pixel in translation and 1° in orientation measurement, with fast evaluation for the real-time PCB positioning task.


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