Sessions Index

Bio:

Dr. Cadmus Yuan is currently a Professor in the Department of Mechanical and Computer-Aided Engineering at Feng Chia University. Dr. Yuan graduated from National Tsing Hua University in Hsinchu, obtaining his Ph.D. in Power Mechanics in 2005, with a major in Solid Mechanics. After graduation, he conducted postdoctoral research at the Technology University of Delft in the Netherlands. He is focusing on applying AI method and Finite Element Method (FEM) to semiconductor packaging design, reliability issues, and smart manufacturing technologies.

Abstract:

  With the advent of cutting-edge technologies such as artificial intelligence (AI), autonomous driving, and heterogeneous integration, electronic packaging has evolved toward more complex and miniaturized architectures—such as chiplet-based systems and high-density interconnects. These advances bring significant challenges to mechanical reliability, particularly concerning solder joint fatigue in plastic ball grid array (PBGA) packages under thermal and mechanical loads.
  To address such reliability concerns, finite element modeling (FEM) has become a widely adopted tool for virtual prototyping. While FEM offers high-fidelity simulations, it remains computationally intensive and requires domain expertise for material calibration, boundary condition settings, and result interpretation. These constraints render FEM impractical for early-stage design iterations that demand rapid evaluation over vast design spaces.
 This invited talk introduces a hybrid framework that integrates AI-based surrogate models with conventional FEM simulation workflows. Rather than replacing FEM, our framework leverages the complementary strengths of both approaches: AI models for rapid inference and exploration, and FEM for high-accuracy validation and critical case analysis. This co-existence strategy enables scalable, cost-effective reliability design in industrial settings.
  A deep neural network (DNN) architecture is proposed as the core surrogate engine. The model is trained on deterministic FEM-generated datasets and designed to capture multi-dimensional, nonlinear design-to-response mappings. Once trained, the surrogate model enables fast approximations, optimization via gradient descent (GD) or particle swarm optimization (PSO), and large-scale Monte Carlo simulations for sensitivity analysis and uncertainty quantification. The resulting insights can be used to filter and prioritize design candidates before passing them to FEM for detailed verification.
This talk will highlight:
The motivation and architecture of the AI-FEM co-design framework.
The methods to train the AI model with new training indicators
The application of the surrogate model in reliability optimization and uncertainty assessment within the AI-FEM loop.
By embedding intelligence early in the design process, this framework bridges physics-based modeling and data-driven inference, enabling more efficient and informed design decisions for next-generation electronic packaging.

 

Bio:
Wataru Doi received joined Murata Manufacturing Co., Ltd. in 2009. He specializes in sealing and bonding technologies for packaging. Since 2021, he has been involved in warpage control for 300 mm COW as part of the WOW Alliance at Tokyo Institute of Technology (Institute of Science Tokyo).

Abstract:
■Introduction
The combination of WOW (Wafer-on-Wafer) and COW (Chip-on-Wafer) has high potential for 3D manufactruing by using well-established BEOL technology [1]. In the previous study, we developed face-down bumpless COW using Via-last TSVs in order to reduce connection impeadance and total packaging volume as shown in Fig. 1 [2][3][4]. Further stacking using such COW technology is expected to enable high-density chiplet systems and is drawing increasing attention [5]. However, the prediction of warpage induced by each stacking layer has not been studied so far. This paper presents FEM-based evaluation of warpage behavior in a double-stacked 3D structure fabricated using a die-patterned waffle wafer, aiming to establish predictive guidelines for multi-layer COW integration.
Double-Stacked 3D Structure
Figure 2 shows the process flow for fabricating a double-stacked 3D structure using a waffle wafer: a) waffle wafer preparation by dry etching, b) mold resin coating, c) thinning back of the Si and resin layers, d) carrier wafer bonding, e) backside Si thinning of the waffle wafer, f) die bonding onto the backside of the waffle wafer, g) resin molding, and f) carrier wafer debonding. The wafer shape at each process step was monitored, and SEM cross-sectional observation was conducted after final carrier debonding in step h.
Warpage analysis
Figure 3 shows the top of view waffle pattern. The waffle wafer is patterned with trenches measuring 3 mm × 3 mm and 70 µm deep, with die-shaped patterns formed inside each trench on the wafer surface [6]. The silicon thickness from the trench bottom to the wafer backside was 705 µm before thinning and 130 µm after thinning. A large die bonded onto the backside of the waffle wafer has a size of 2.8 mm × 2.8 mm × 200 µm. In the FEM analysis, the temperature was varied from 125 °C to 25 °C, with the resin molding temperature assumed as the stress-free reference state.
■Results and discussion
Figure 4 shows the wafer shape at each step during the stacking process. Since there was no supporting substrate, wafer rigidity was reduced, resulting in significant warpage at step h) due to the remaining thick mold layer. Nevertheless, a double-stacked 3D structure was successfully achieved, as shown in Fig. 5. Except for the secondary molding steps, i.e., f) and h), wafer warpage was measured and compared with simulation results, as shown in Figure 6. Up to step e), which corresponds to Si thinning, the simulation predicted wafer warpage with approximately 5% accuracy, indicating that the FEM analysis is effective for warpage prediction. In the case of secondary molding (step g), the measured wafer warpage differed from the simulation by about 20%, which is attributed to non-uniform mold thickness.
■Conclusion
A double-stacked 3D structure using a waffle wafer is demonstrated for the first time to enable prediction of wafer warpage in multi-COW stacking applications. FEM analysis allowed estimation of wafer warpage with approximately 5% accuracy during the stacking process. These results show that warpage can be predicted in advance, facilitating process design for multi-layer COW stacking.

 

Bio:
Master of Material Science and Engineering, NCTU

Abstract:
To achieve miniaturization in module level and board level, component pitch and terminals are getting
finer, denser, and smaller, in which the solder joint are getting less to provide a reliable joint strength, thus
encapsulation is required to protect the joint to achieve reliability requirement. As wireless products begin to
adapt System in Package (SiP) product architecture which use different board material (substrate, substrate
like and FR4), chip design and encapsulation methods (underfill, transfer molding and compression molding).
To achieve products with high stability and reliability, where molded underfill (MUF) by transfer molding
(T-Mold) or compression molding (C-Mold) has been recognized to provide robust reliability and
miniaturization for high density and fine pitch components. Due to the high process temperature (175C) and
high mold flow pressure (5~8Mpa), the thermal and mechanical stress is not only sever to sensitive
component but also requires BT substrate as a MUST. Unfortunately, the lead-time and cost of BT substrate
and the mold tools usually become a bump in the road to innovations, especially in emerging or hi-mix
low-volume early applications. Therefore, a method of low temperature, low pressure and quick lead time
encapsulation is required. In this paper, a vacuum printing encapsulation (VPE) is developed with liquid
printable compound. Three wireless products were selectd with different module sizes and PCB structures
(BT substrate, substrate like and FR4) as test vehicles. Reliability tests (MSL3 and TCT) and function test
(FCT) were conducted to verify the developed VPE for SiP capable of achieving the comparable
performance as the standard T-Mold and C-Mold. It also demonstrates the advantages of the developed VPE
in lead-time saving up to 12+ weeks from mold tools and BT substrate preparation compared with standard
T-mold or C-mold, which provides a miniaturization competence of time-to-POC, time-to-delivery,
time-to-quality, time-to-cost and consequently.

 

Bio:
Hualong Fu is currently pursuing a master's degree at the Institute of Microelectronics of the Chinese Academy of Sciences. His research focuses on fundamental research on the reliability of advanced packaging, especially in the field of fracture mechanics.

Abstract:
The redistribution layer (RDL) enables electrical interconnections between internal and external pins, reducing package size. The fracture resistance of PI-Cu interface in RDL is crucial for interconnection reliability in wafer-level packaging. However, existing studies lack a quantitative evaluation of the location-dependent CZM fracture parameter of PI-Cu interfaces during RDL fabrication, which hinders process optimization for RDL. To address this gap, this study compared and analyzed the shear fracture mechanical behavior of PI-Cu interfaces across various wafer regions using shear testing, combined with simulation-based inversion methods. The results demonstrate that the PI-Cu interface in central wafer region exhibits a mean shear strength (τ) of 109.67 MPa and critical energy release rate (Gc) of 19.5 J/m², both values exceeding the edge. The degree of dispersion of these parameters follows the same trend, confirming that the central interface possesses stronger fracture resistance but greater performance variability. Additionally, the CZM parameters for the central and edge regions were characterized: the maximum τ was 3.4 MPa, the stiffness was 250 MPa/mm, and the relative shear separation displacement was 0.0112 mm, indicating differences from the edge region. This research provides support for optimizing the PI-Cu interfaces.

 

Bio:
I have worked at ASE for over 5 years, specializing in mechanical simulation of advanced package technologies.

Abstract:
With the rapid advancement of high-performance computing and heterogeneous integration, advanced packaging technologies continue to evolve to meet the increasing demand for high I/O density and superior electrical performance. ASE’s Fan-Out Chip on Substrate-Bridge (FOCoS-B) is a promising solution. This structure integrates multiple chiplets through an embedded bridge within a fan-out module, which is then mounted onto a high-density organic substrate. The architecture enables fine-pitch interconnects while offering excellent signal integrity and design flexibility.
Due to the complex material stack and multi-layer assembly process, mechanical reliability especially warpage control has become a critical challenge in FOCoS-B packaging. This study focuses on the warpage behavior at two key manufacturing stages: the wafer-level process and the post-dicing fan-out module step. Finite Element Analysis (FEA) is used to simulate thermal-mechanical deformation and assess key contributing factors including structural and material conditions. Structural factors consider top die thickness, bridge die thickness, and different fan-out RDL stack-up designs. The material factors involve epoxy molding compound (EMC), underfill (UF), and wafer-level carrier. A design of experiments (DOE) approach is applied to systematically analyze the impact and interaction of these variables.
During the wafer process, the properties of the EMC and carrier are crucial and expectedly have a significant impact on warpage. After singulation into individual modules, the combination of the top and bottom EMC becomes even more important. Inappropriate combinations of materials and structure may lead to severe warpage and stress concentration, particularly around the embedded bridge area, posing potential reliability risks.
This study provides key insights into warpage control and mechanical behavior in FOCoS-B structures and serves as a design guideline for improving process yield and long-term reliability in next-generation fan-out packaging.

 

Bio:
Professional Profile: Currently serving as a Manager at the Industrial Technology Research Institute (ITRI), I hold a Ph.D. in Materials Science from National Chiao Tung University. I bring over a decade of hands-on experience in advanced materials analysis, semiconductor device development, and integrated IC packaging technologies. Areas of Expertise: Nanomaterial characterization, including thin-film defect control, thermal stability, and microstructure analysis Semiconductor devices and circuit design, with a focus on flexible LTPS-TFT and advanced thin-film integrated passive and active components IC packaging materials and process development, including Fan-Out Panel Level Packaging (FOPLP) and advanced IC substrates Proven record of innovation with 43 granted patents, 45 academic publications, and 27 technical reports My work bridges research and industry, combining deep technical knowledge with practical engineering solutions to advance semiconductor and packaging technologies.

Abstract:
To meet the demands of high-end IC packaging, the advancement of IC packaging will focus on the re-distribution layer structure in wafer-level packages (WLP) and panel-level packages (PLP). Enhancing computing power requires integrating multiple chips into a single module, which involves establishing high-density connections for communication signals between chips. Thus, the chip-first approach is preferred for achieving these high-density traces. However, scaling line width and via with good reliability is a significant challenge for PLP due to undercut issues and adhesion with Copper. Additionally, the chip placement and molding processes can destabilize IC spacing, leading to die shift, which may disrupt communication signals. To address these issues, adjust seed layer thickness and improve the adhesion between seed layer and dielectric for fine line RDL with good reliability, along with digital dynamic correction during lithography to compensate for die shift. This research successfully demonstrates the feasibility of this structure using low temperature sputtering and Digital Lithography Technology (DLT). The technology has been verified to provide patterning compensation for the RDLs in the chip-first IC packaging structure. The results indicate that the maximum displacement of the chip which can be corrected a horizontal displacement (XY) of 50 μm and an angular displacement (θ) of 0.3° in 4 chips packaging structure. Furthermore, in this case, we also have studies about die shift compensation at high frequency signal (2GHz ~ 20GHz). The result shows the signal loss will be decreased by dynamic tuning ground signal trace width and angle with Digital Dynamic Connection (DDC™) technology. In addition, the 3D4M RDL stacking has good reliability in panel level package structure. Those results show the great potential of high resolution multi-RDLs for chip-first FOPLP application. Moreover, besides its applicability to high-end panel-level packaging in the future.

 

Bio:
Yu-hao Lo is a first-year M.S. student at the Academy of Innovative Semiconductor and Sustainable Manufacturing, NCKU, under the supervision of Prof. Jun Mizuno. His research focuses on microfluidic cooling, bonding technology, and thermal analysis. He previously interned at Tokyo Electron and participated in an exchange program at Tohoku University’s MEMS Laboratory, gaining international and industrial experience in semiconductor processes.

Abstract:
With the rising power density in heterogeneous chiplet packages, thermal management has become a critical challenge for ensuring reliable operation. High-power ASICs with thermal design powers exceeding 400 W demand localized and efficient cooling beyond the capability of conventional air-cooled solutions. This work proposes a microfluidic cooling structure mounted directly above two 400 W ASICs and four 15 W HBM2E modules within a 50 mm × 40 mm package, totaling nearly 900 W of heat dissipation. To enable reliable high-temperature integration, the structure is bonded using Au–Au diffusion bonding. Two device types with identical microchannel geometry were fabricated: one on a silicon substrate using photolithography and deep reactive ion etching, and the other on copper using precision mechanical milling. CFD simulations showed that the Cu–Cu structure achieved better cooling performance, with a maximum surface temperature of 74 °C, compared to 92 °C for the Si–Si structure, consistent with copper’s higher thermal conductivity. Thermal testing was performed by placing the Cu-based device on a 100 °C ceramic heater and recording temperature decay using four thermocouples. Time constants ranged from 5.3 to 63.8 seconds depending on location, with the fastest cooling observed at the center of the channel. Infrared imaging confirmed directional temperature gradients consistent with fluid flow. 3D X-ray imaging verified that both bonded devices had continuous microchannels without collapse, though the Si-based device exhibited edge delamination. These results demonstrate a high-power microfluidic cooling concept using Au–Au bonded structures. Si-based thermal validation is ongoing to confirm simulation trends.