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S20:Test, Quality, Inspection and Reliability

Oct. 27, 2022 15:40 PM - 17:40 PM

Room: R503
Session chair: Jeffrey Lee, IST / Yu-Jung Huang, Professor, ISU

High Density Conductor Reliability Validation for More Edge Computing
發表編號:S20-1時間:15:40 - 16:10

Invited Speaker

Irving Lee, Manager, UL GmbH

Advanced Interconnection Stress Testing Mechanism


 
The impact of Sn-Oxide on the solder wetting of immersion tin and how to overcome possible solderability defects to ensure constant solder wetting performance
發表編號:S20-2時間:16:10 - 16:25

論文編號:EU0101
Britta Schafsteller, Bernhard Schachtner, Anja Streek, Kenneth Lee, Hubertus Mertens, Gustavo Ramos

Immersion tin is a final finish which is widely used in the printed circuit board (PCB) industry. It provides a cost competitive surface protection with excellent corrosion resistance, and has the capability for multiple reflow soldering. The tin is deposited on copper by immersion reaction with a typical layer thickness in a range of 0.8 – 1.2 µm. On top of the tin layer an oxide layer is formed, which can influence the properties of the final finish. During the assembly process an intermetallic compound (IMC) grows connecting the copper substrate and the tin of the solder alloy. The growth of the IMC is a complex function of temp and time.
The IMC formation and well distributed pure tin remnants is a key factor for reliable solder joint. With increased aging of the immersion tin deposit, the role of the tin oxide layer becomes of particular interest for aged or reflowed immersion tin layers and regulator for properties of solder and immersion tin in liquidus process at reflow step. Due to the IMC formation the tin layer is facing increasing internal which is potentially released via the oxide covered surface. The quality and thickness of the tin oxide layer impacts the solder wetting performance of the final finish, the risk of whisker formation and in particular the stability and appearance of the layer after reflow aging.
In this paper an introduction on typical failure mechanisms and root causes for solder wetting defects of immersion tin will be given. Such defects can become e.g. visible as solder dewetting in certain areas of the soldered pads or as partial shiny appearance of the tin surface after reflow cycles. The mechanisms introduced in this paper are supported by correlating tests to identify the possible root causes for the solder wetting defects.
In this study various methods are presented which allow the determination of the tin oxide layer thickness. Different factors are investigated on their impact on the tin oxide layer formation and various approaches are studied in order to modify the thickness of the oxide layer. Based on the test results the properties of the tin oxide layer could be identified as critical parameter for the immersion tin layer performance. The application of a dedicated post-treatment solution can modify the tin oxide layer and, in this way, improve the performance of the immersion tin deposit in regard to appearance and solderability. This is confirmed by optical inspection, different types of solderability tests as well as whisker evaluation.


 
Robust and Accurate Measurement Methodology for High-speed Channel Electrical Characterization
發表編號:S20-3時間:16:25 - 16:40

論文編號:TW0052
Jimmy Hsu, Fred Chou, Alex Wei, Johnny Hsieh, Adolph Cheng

As communication technology transits to 5G generation, it drives the development of AI ecology, such as new smart factories, smart warehousing, smart real-time monitoring platforms and other applications, which also tests the quality detection capability of high-speed channels in the data center printed circuit board(PCB), such as the loss of high-speed channels capability of measurement and impedance measurement and segmental analysis.
The PCB manufacturers usually check the impedance by time-domain reflectometer (TDR) and channel loss of the PCB by vector network analyzer(VNA) according to the IPC standards [1] [2]. It is critical to have multi-zone analysis ability of the TDR impedance profile in the design and manufacture accurate perspective, such as how to identify correctly break out with the narrow trace routing, plating through hole (PTH) via and main routing impedance.
The conventional TDR instruments are widely used by PCB manufacturers in the impedance measurement, but the resolution and accuracy are influenced by cables, probes or fixtures which has a huge impact on multi-zone impedance analysis.
In this paper, VNA with the calibration technology is proposed to not only analyze TDR impedance with multi-zones but also measure channel loss for quality risk assessment. The precision coaxial air lines are adopted as primary reference standards to assure impedance measurement verification, and traceability mechanism is conducted into the comparison experimental of impedance resolution capabilities for accurate and robust measurement. [3-5]
In the comparison experimental of impedance resolution capabilities, qualitative analysis method is conducted to verify cables of different lengths, and different instruments in the same type of VNA and TDR in order to compare the analytical capabilities. Through the experimental results, VNA demonstrates the better analytical ability because of the calibration technology and robustness by small error variation between different instruments. In addition, VNA has the advantage of providing measurement information of channel loss for quality risk assessment.
The scope in this study is focused on the analysis of the changes in the measurement values of the instrument itself. Therefore, future research will address the difference between the measured values of the VNA instrument and the TDR instrument, the parameter setting changes of the VNA to convert the TDR value, and the variation of different device under test (DUT).
REFERENCES
[1] IPC-TM-650 TEST METHODS MANUAL “Characteristic Impedance of Lines on Printed Boards by TDR” ,IPC ASSOCIATION CONNECTING ELECTRONICS INDUSTRIES
[2] IPC-TM-650 TEST METHODS MANUAL “Measuring High Frequency Signal Loss and Propagation on Printed Boards with Frequency Domain Methods”,IPC ASSOCIATION CONNECTING ELECTRONICS INDUSTRIES
[3] B.O. Weinschel, “Air-filled coaxial lines as absolute impedance standards,” Microwave J., pp. 47–50, vo, 7, Apr. 1964.
[4] I.A. Harris and R.E. Spinney, “The realization of high-frequency impedance standards using air-spaced coaxial lines,” IEEE Trans. Instrum. Meas., vol. 13, no. 4, pp. 265–272, 1964.
[5] International Vocabulary of Basic and General Terms Used in Metrology, 2nd Ed. International Organization for Standardization, Geneva, Switzerland, 1993.
[6] L. Essen and K.D. Froome, “The refractive indices and dielectric constants of air and its principal constituents at 24,000 Mc/s,” Proc. Phys. Soc., vol. 64B, no. 10, 1951, pp. 862–875.
[7] K.H. Wong, “Using precision coaxial air dielectric transmission lines as calibration and verification standards,” Microwave J., vol. 31, pp. 83–92, Dec. 1988.


 
Determination of Dielectric Constant and Dissipation Factor of Printed Circuit Board by Microstrip With Ring and Straight-Line Resonator Measurements
發表編號:S20-4時間:16:40 - 16:55

論文編號:TW0102
Chien-Chang Huang

This paper presents the determination of dielectric constant (DK) and dissipation factor (DF) of a printed circuit board (PCB) by microstrip structure for its easy fabrication as a test coupon in manufacturing, as well as the mature empirical formulas to extract DK and DF from measured data of microstrip propagation constant γ. The ring and straight-line resonators (SLRs) are utilized to measure γ and different results are observed. The explanations of the data deviations with the modified approaches are proposed in this paper to improve the consistency. With the measured γ, the DK extraction can be extracted by an iterative process where the propagation constant γ is calculated based on an initial DK using the microstrip empirical formulas with dispersion effects, and the process is continued until reaching the acceptable error between calculated value and the measured γ. The DF is computed based on the solved DK with conductor loss. The proposed method is examined by the PCB material of RO3003 using probing technique up to the fifth order of resonant modes in the frequency range of 18 GHz to 90 GHz.


 
Electrochemical analysis of initial oxide layers on copper surface
發表編號:S20-5時間:16:55 - 17:10

論文編號:TW0130
Yu-Cheng Chang

Copper has been a widely used conductor and metallization material in form of electroplated or sputtered
films, as well as cold-rolled lead frames or clad sheets, in microelectronics and MEMS devices due to the
combination of low resistivity and low power loss. However, surface copper oxide formation during
fabrication or assembly processes increases electrical/thermal resistivities or even causes device malfunction.
The common methods to analyze surface oxide layer are XPS, TEM and XRD (X-ray diffraction) techniques.
Unsatisfactorily, sample preparation for those analytical means is time-consuming. Relevant instruments
are sophisticated and costly. In this study, coulometric reduction method was adopted to investigate the
phase and thickness of surface oxide layer of sputtered copper. The samples subjected to citric acid wash
and room temperature storage were investigated. Repeated reduction tests in NaOH solution was also carried
out to explore the very early state of the copper surface. According to the reduction potential ranging from -
0.62 to 0.65 V, the initial oxide formed in NaOH solution was CuO with the thickness of around 1.1~1.2 nm.


 
Copper Surface Roughness Analysis in Mathematical Morphology Algorithm for the Insertion-Loss Validation
發表編號:S20-6時間:17:10 - 17:25

論文編號:TW0107
Li-Chi Chang

Insertion loss of a testing vehicle is widely referred for the material estimation, the differential pair and single-end striplines are generally employed for the high-speed digital applications. In addition to the matte side, the shiny side with the surface treatment of the inner layer is the critical issue for the insertion-loss improvement. In general, the inner-layer roughness is determined by the cross-section scanning electron or optical microscope photo with the manual defining of the average line. Therefore, the tolerance is produced from personal operation or gage repeatability and reproducibility (Gage R and R). In this study, a numerical morphology algorithm is proposed for automatically detecting the roughness of the striplines. Basing on the algorithm and operating flow, the detected Rz and Rq values of the copper-foil roughness are applied in 3D simulation tool for the insertion-loss validation and comparison.
Keywords: differential, single-end, cross-section, numerical morphology, and insertion loss.


 
Drop Reliability of Direct Cu-to-Cu bonding
發表編號:S20-7時間:17:25 - 17:40

論文編號:TW0129
Yu-Kuang Chen

Portable electronics have become one of the main applications for semiconductor devices, thereby the drop
test has been regarded as an important evaluation for electronics reliability. Direct Cu bonding is considered
an ideal way to achieve inter-chip vertical connections for TSV (through silicon via), due to size
miniaturization and low electrical resistance. In this study, drop testing of packages comprising sputtered
copper on Si chips joined with electroplated copper on Al2O3 substrates assembled by thermal compression
bonding was performed. Experimental results show that pre-treatment using Xenon flash can be
accommploshed in a very short time, but a remarable improvement of drop resistance for direct-copper bonds
can be achieved. As for the package with no flash pre-treatment and those treated with 20 time exposure, the
drop life was less than 5 times. Notably, packages subjected to flash exposures of 5, 10, 15 times all
withstanded drop test for over 30 times, which were much stronger than those bonded using SAC307 solder
pastes (drop life was 10 times or below). The enhancement in joint reliability can be ascribed to the increase
in compressive surface residual stresses, which accelerate diffusion of copper atoms, and reinforce direct Cu
bonding. This finding is very crucial for 3D packaging for portable usages.


 


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