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"Recent achievements in the research of heterojunctions fabricated using surface activated bonding (SAB), one of the practically useful direct wafer bonding technologies, are discussed. The response of bonding interfaces to post-bonding annealing is focused. These junctions reveal excellent stability against high-temperature processes (typically 1000 °C in the case of junctions made of widegap materials) despite differences in coefficients of thermal expansion between bonded materials. The electrical and mechanical properties of bonding interfaces are improved by annealing. These results show that novel advanced devices are likely to be realized by applying wafer processing steps to SAB-based junctions. Characteristics of III–V//Si multijunction solar cells, diodes made of narrow-gap/wide-gap junctions, metal-foil based low-loss interconnects, and GaN-on-diamond high electron mobility transistors that are fabricated by processing SAB based junctions are described. Prospects of SAB as wafer process technologies are also discussed."

 

To improve the output current quality and efficiency of an electric vehicle drive system, this study introduces a variable switching frequency global control strategy. Utilizing Matlab/Simulink, the motor and controller system are simulated to automatically identify the optimal switching frequency for different operating points. Once the frequency table is determined offline, it can be used to operate all global operating points at their optimal switching frequency through a lookup table.
The variation in switching frequency impacts both current harmonic distortion and switching losses. Lowering the switching frequency can reduce switching losses but may also degrade current quality. The control strategy proposed in this study automatically adjusts the switching frequency to ensure that the electric vehicle drive system maintains an optimal balance between switching losses and output power quality under varying load conditions.

 

A FOPOP (Fan out package on package) which adopts redistribution layer (RDL) technique to replace conventional substrate-based POP has benefits of thinner profile, better electrical and thermal performance. It has been used as high-end AP for smartphone in recent years. Wafer warpage control during wafer form fabrication process is important, Poor wafer warpage would impact the process pression adversely and even interrupt the process when exceeding wafer handling capacity of the machines. Moreover, package warpage is becoming more challenges due to thinner package thickness. Poor package warpage would affect quality results of SMT and stacking DRAM. Thus, the optimization of the material selection and design parameters becomes criteria to the wafer and package warpage control.　
In this paper, Finite Element Analysis (FEA) simulation is performed to predict wafer and package warpage. Birth and dead method which considers process continuity is used while predicting wafer warpage. For package warpage, various structural parameters include RDL thickness, Cu stud height and die thickness are simulated. Then simulation results are analyzed by statistical analysis software to identify critical parameters impacting package warpage. Moreover, warpage prediction formula could be derived by performing the regressions analysis. Hence the package warpage could be optimized as early as in the design stage via the warpage prediction equation.

 

Chiplet packaging using fan-out (FO) redistribution layers (RDL) or Si interposers is one of primary choices of packaging technology for meeting the demands in high-performance computing applications. In typical chiplet package designs, the Si dies are embedded in epoxy molding compound (EMC) or underfill and connected to polymer or Si-based redistribution interconnect, and then further mounted on traditional laminate substrate. Due to the increased density of dissimilar materials interfaces such as EMC-Si, underfill-Si, Cu-polyimide (PI) in the chiplet packages, the risks of cracking or debonding failure are higher under stresses experienced during packaging processes or in-use conditions. One of the primary failure mechanisms of packaging during the assembly solder reflow process is the moisture absorption related interface debonding or the pop-corning effect. At reflow temperature, the mismatch in the coefficients of thermal expansion (CTEs) between the dissimilar materials would lead to high thermal stresses at interfaces. In addition, the vapor pressure builds up at the interface defects would likely to further increase the driving force for interface debond. For the purpose of evaluating the risk of debonding or pop-corning failure during reflow process, it is important to give a quantitative estimation of the hygrothermal stress and the related debond driving force.
In this paper, a fracture mechanics model for the driving force of the debonding of Si sidewall-underfill interface in a FO chiplet package under solder reflow condition is presented. The numerical finite element (FE) based model considers the coupled hygro-thermo-mechanical response of the chiplet package under moisture sensitivity level test (MSL) condition. The model simulates the transient moisture diffusion and the subsequent vapor pressure development in the polymeric materials, and then evaluates the related hygroscopic and thermomechanical stresses in the package. In addition, the fracture mechanics parameters for the interface debond including the strain energy release rate and the phase angle are obtained from a 3-D virtual crack closure procedure. From the simulation results for a FO two-die package, it was shown that the primary debond driving forces of the Si-underfill interface at elevated temperatures are the CTE-mismatch related thermal stress and the crack-face vapor pressure. On the other hand, the moisture swelling does not contribute much to the debond growth. The estimated debond driving force would exceed the moisture-weakened fracture toughness of the interface if the defect size reaches a certain threshold. In addition to the comprehensive procedure that models the coupled hygro-thermo-mechanical driving force for interface debond growth at reflow temperature, a simplified model for evaluating the debonding risk was also presented. The simplified model ignores the transient moisture diffusion process and adopts an equivalent coefficient of thermal expansion for considering both thermal and moisture effects. By comparing to the results of the comprehensive model, it was shown that the simplified model is feasible as a first-order evaluation of the crack driving force under reflow condition.

 

New technology developments, such as artificial intelligence (AI) and fifth generation (5G) wireless networks, require high-speed systems to perform high-speed data calculations. As data rates continue to increase rapidly, both signal integrity (SI) and power integrity (PI) are intertwined and have become key factors to meet the bandwidth growth requirements of various applications. To achieve a robust design, both SI and PI should be treated jointly to meet high-performance electronic systems requirements. However, when temperatures rise, material properties will also change.
In this study, an Electrical-Thermal co-simulation methodology analyzing SI and PI performance in both package and printed circuit board (PCB) designs was used to account for different materials’ temperature-dependent behaviors. This paper will describe in detail SI and PI performance variations for IO nets in both package design and the PCB impact due to temperature.

 

This study utilizes the MTS Acumen micro-force tensile machine to test three commonly used probe materials: Tungsten (W), Rhenium Tungsten (ReW), and P7 (Paliney 7). The materials' properties were evaluated under different probing environments and speeds in a thermal chamber to ensure proper functioning under various test conditions. An initial mathematical model of geometric parameters was established using MATLAB. Considering the probe diameter, the model applies Castigliano's second theorem combined with a planar coordinate system to calculate the deflection at each probe node, predicting potential interference among probe layers. Additionally, the study identifies non-interfering intervals for five key geometric parameters of cantilever probes: insert angle, bending angle, taper length, beam length, and tip length. These parameters significantly impact the contact force and the length and depth of the probe marks on the pads. Furthermore, the probing behavior of multilayer cantilever probe cards was simulated using ANSYS. Coupled with a genetic algorithm (GA), the five geometric parameters were optimized to achieve uniform contact force and consistent pad probe marks across probe layers. The genetic algorithm helped to refine the design of the probe card by evaluating various configurations to find the optimal geometric setup. The findings of this study provide valuable insight into the design and application of probe cards, ensuring higher accuracy and reliability in wafer probing. The findings provide valuable information for the design and application of probe cards.

 

The rapid development of communication and electronic products has driven electronic packaging structures to evolve towards lighter and thinner characteristics to meet product demands. At the same time, these structures require higher performance and reliability and need to accommodate more I/O (input and output) connections within the same structural size. In flip-chip structures, the I/O connections are formed in an area array, connecting the chip to the substrate through solder balls and transmitting electronic signals between them. However, due to the mismatch in the coefficient of thermal expansion (CTE) between the materials of the chip and the substrate, significant changes in environmental temperature or thermal cycling conditions could cause different thermal strains in the chip and substrate. The resulting excessive deformation differences can subject the solder balls to severe shear stress, leading to serious deformation or even breakage of the solder balls, ultimately causing the entire package to fail. Therefore, in typical flip-chip structures, underfill is applied around the solder balls to reduce the stress caused by the CTE mismatch, effectively enhancing the structural reliability of the solder balls. Although under-fill is the most common reinforcement on solder joint reliability, its techniques have some issues that should be a concern, such as process complexity, reworkability, material selection and cost, and the void induced by capillary flowing.
This study focuses on the side-fill adhesion reinforcement and utilizes the finite element method (FEM) for structural analysis to discuss the impact of various structural factors of side-fill structure on the reliability of components, thereby improving process efficiency. Different filling forms and side-fill profiles as shown in Figure 1 and Figure 2, provide additional mechanical support. The study involves obtaining the relevant geometric dimensions, material mechanical properties, and thermal cycling test parameters of the experimental vehicle. These parameters are effectively identified to fully understand the experimental vehicle and the information related to this study. In addition, this study will present the solder reliability improvement for lead-free solder (SAC305) used in Wafer Level Chip Scale Package (WLCSP) under temperature cycling test (TCT) conditions over a temperature range of -40℃ to +90℃. Based on the obtained information, FEM modeling is carried out, and the reinforcement and failure mechanisms of the side-fill structure are verified through theoretical and simulation methods.
The simulation results show that using side-fill encapsulation to protect the solder balls reduces the increment of stabilized equivalent plastic strain by approximately 100% compared to none of any adhesive as shown in Figure 4. The reinforcement of the sidefill structure with the four-corner pattern exhibits a significant effect. For moderate reliability products, the side-fill can significantly reduce the cost of materials while achieving a double or more reliable lifespan.