Oral Sessions


S6:Advanced Packaging for Data Center/ Server Applications by Atotech

Oct. 26, 2022 15:40 PM - 17:40 PM

Room: R504b
Session chair: Eddy Chen, Atotech

Future Packaging Trends and Drivers for Datacenter
發表編號:S6-1時間:15:40 - 16:10

Invited Speaker

E. Jan Vardaman, President and Founder, TechSearch

Trends in datacenter growth and packages used for CPUs in datacenter, includes a discussing of the package options used by different companies, future needs including power delivery and thermal dissipation, drivers for next generation packaging including co-packaged optics.

Advanced Packaging implications to Substrates
發表編號:S6-2時間:16:10 - 16:40

Invited Speaker

Dilan Seneviratne, Principal Engineer, Director DSP Area, Intel

Conventional thinking of Advanced Packaging centers around bump pitch and IO density scaling. However, with the aggressive demands driving the increased computational needs in data centers, more features need to be considered and developed. This talk will address what features and capabilities are needed on high density interconnect substrates to meet the Advanced Packaging needs.

Advanced Substrate Challenges for Heterogeneous Integration
發表編號:S6-3時間:16:40 - 17:10

Invited Speaker

YH Chen, Vice President, Unimicron

Heterogeneous integrations are driven by Moore’s Law, and advanced packaging plays a critical role for semiconductor supply chain. Unimicron covered most less than 7nm IC carrier and foresee the high-end substrates will be continuously shortage. Heterogeneous integration of high-end products existed from 2.5D planar interconnect (Si interposer, EMIB) to 3D die-to-die stacking (WoW, SoIC, Foveros).
Substrate technology is driven by extreme body size/high layer counts, heat dissipation, low loss material…etc.

IC substrate scaling to enable higher IO density - Challenges and solutions
發表編號:S6-4時間:17:10 - 17:40

Invited Speaker

Kuldip Johal, Global OEM Director New Technology Pathfinding, Atotech

Heterogenous integration continues to adopt many options such as Silicon interposer, different formats of embedded Silicon and high-density fan out. All these integration routes have the objective of increasing IO density. The challenge is that many of these options are costly, and in response the advanced packaging industry continues to look for lower cost options. The laminate-based IC substrate remains to be the most cost-effective solution, however, there are challenges to increase IO density with this approach. There are 2 options to increase IO: first, one can increase layer count, which is already challenging due to yield issues, and second; one can continue IC substrate scaling to finer pitch interconnects. The focus of this presentation is to review the key challenges and solutions associated with IC substrate scaling and their impact on the various processes.


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