Oral Sessions

Growing HPC market and 3DIC integration complexity present challenges for advanced packaging technology and manufacturing. Seamless integration of testing with advanced Si and assembly process is critical to unleash the full potential of chiplet archtectures. 3DFabricTM intelligent Fab with AMHS automation, full production traceability, big data analysis for precision process control and optimized manufacturing flow will be also presented.

Bio:

Education:
Ph.D. in Materials Science, University of California, Santa Barbara, USA美國聖塔芭芭拉加利福尼亞大學材料科學博士

Experience:
Senior Director, Advanced Technology Quality and Reliability, TSMC台積公司先進技術品質暨可靠性資深處長
Senior Director, Head of Quality and Reliability for Technology & Manufacturing Group, Intel美商英特爾公司技術暨製造群品質暨可靠性主管暨資深處長


Jun He’s Biography：
Dr. Jun He is Vice President of Quality & Reliability(QR) as well as Advanced Packaging Technology & Service (APTS) at Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC). His responsibility spans across TSMC foundry eco-system and the Company’s backend business and operations management. Within the Q&R scope, his function covers incoming materials qualifications, reliability and certification of new process technology & design IP, manufacturing quality as well as enabling customers for their product qualifications and ramp. Besides overseeing all TSMC advanced packaging and testing manufacturing, his backend team is also accountable for key building blocks including bump/passivation/RDL process innovations and test technology development. Seamless collaboration and joint development with external partners across material, OSAT and substrate supply chain is one of his focus areas to enable customers’ product innovations at system level.

Prior to joining TSMC, Dr. He was a senior director at Intel Corporation, leading overall quality and reliability of process technology development and manufacturing. His scope included research & development of Si, advanced packaging and test along with Intel worldwide manufacturing operations.

Dr. He holds over 40 patents globally and published over 50 papers in international conferences and peer-reviewed technical journals. He received his B.S. degree in Physics and Ph.D. in Materials Science from University of California, Santa Barbara.

 

Chiplet architectures are fundamental to the continued economic viable growth of power efficiency of AI, 5G and edge computing. The slowing of Moore’s law has also placed advanced packaging at the critical juncture of technology-architecture intersection driving unique product capabilities. New heterogeneous architectures like 2.5D Fanout and 3D Hybrid bonded architectures driving AMD’s industry leading advanced technology roadmap to enable power, performance, area, and cost (PPAC) will be discussed. Other topics including Chiplets for AI, challenges and solutions for large chiplet modules etc. will also be discussed. We will specifically focus on how advanced 3D packaging is enabling industry’s best AI architectures.

Bio:
Dr. Raja Swaminathan is CVP, Packaging instrumental in the development of AMD’s industry leading advanced packaging roadmap. Raja has been a leader in silicon-package-system architecture definition and a co-design expert with extensive experience introducing new technologies and innovation across the silicon-packaging spectrum at Intel, Apple and AMD. He’s helped enable PPAC (power, performance, area, and cost) improvements as well as introduction of novel heterogeneous architectures throughout his career: EMIB, Apple’s Mx package architectures, 3D V-Cache, Elevated Fan-Out Bridge, High Performance Fanout to name a few. Raja received his Bachelors’ from IIT Madras and PhD from Carnegie Mellon University and has over 40 US patents in the field. He is an IEEE Senior Member and is on the technical advisory board for multiple semiconductor startups.

 

This presentation introduces the results and learning from an iNEMI project focusing on the shear testing of fine line patterns in integrated packages to evaluate their adhesion strength. In the project, the team utilized test vehicles with copper-cladded FR4 core and ABF, and copper islands of different widths were subjected to shear testing. The results demonstrate that the shear force increases with trace width, indicating a correlation between adhesion strength and trace size. Additionally, a factorial study was conducted to assess the impact of various test parameters on the collected data. The study highlights the significant influence of shear direction, shear height, and shear speed on the measured shear values. Future investigation aims to establish a standardized set of test parameters to consistently understand force variations concerning size, to achieve a better understanding of adhesion behavior in advanced integrated circuits.

Bio:
WANG Tzu-Hsuan is currently the Sr. Deputy Manager at Unimicron Technology Corp. Carrier R&D dept. and in charge of advance substrate process development, such as “2.1D/2.3D Substrate”, “Semi-like process development”, “RDL fine line expand”, and other CSP/BGA process modification & new process development. He received a master’s degree in 2014 from Tatung University of Material Engineering. In this iNEMI project, Unimicron takes care of DIC sample preparation and adhesion test study on shear test.

 

This talk presents the recent results from the iNEMI project on High Density Interconnect Socket Warpage Prediction and Characterization. The dimension of high-density interconnect socket for CPU and GPU become bigger with the increase of interconnect pin counts. The dynamic warpage control during reflows the socket onto the printed circuit board is a challenge for large sockets. Injection molding simulation is a powerful tool to predict the dynamic warpage and guide the design modification. However, the mechanical properties of liquid crystal polymer (LCP) are different from general plastics. To improve the simulation accuracy, modified methodology and material modelling for anisotropic polymer matrix with glass fiber would be required.
Three LCP material grades are used for mold trial on two socket designs – one without core out while the other with core out. Dynamic warpage of bare housings is measured using a temperature profile between room temperature and 250℃. The injection molding simulations are performed by Moldex3D and compared with the experimental measurement results. The simulation results also show the dynamics warpage prediction would be influenced by the anisotropic properties of the LCP matrix.

Bio:
Dr. Chang is a senior engineer at Moldex3D, a company that provide simulation solutions of plastic injection molding. His major work is supporting customer trouble shooting, design modification, and manufacture better plastic product via simulation tools in automobile, optics, connector, semiconductor, and so on. He is a core team member and simulation expert in the iNEMI “Package Warpage Prediction and Characterization” project phase 5 and “High Density Interconnect Socket Warpage Prediction and Characterization” project phase 2.

 

This talk presents recent advances in the iNEMI “Reliability & Loss Properties of Copper Foils for 5G Applications” project as well as techniques for the electrical characterisation of metallic foils, developed by QWED in response to the needs identified in the above project. At mm-waves, considerations of electrical performance and PCB durability may often lead to contradictory requirements with respect to copper foil materials and chemical pre-bond treatments. For example, decreased surface roughness will typically decrease conductor loss but may compromise PCB durability.
The iNEMI consortium is performing a rigorous study, based on copper foils from different manufacturers, where surface roughness and loss properties of the foils are independently evaluated. An original contribution from QWED resides in providing easy-to-use intruments, based on mmWave resonator heads, for measuring the effective conductivity (or surface resistance) of copper foil samples per se. Such techniques alleviate the need for manufacturing a test circuit (such as a strip-line segment) and naturally deliver the loss due to the copper, separated from any substrate losses, as no substrate is involved in the measurement. The resonator heads are designed and calibrated with the use of full-wave computational modelling with QWED’s own QuickWaveTM software. The conference talk will explain the physical fundamentals of the developed methods, illustrated with the results of copper foil measurements in the 13- 40 GHz range. Extensions to higher frequencies are underway and will be signalled. The presented testing methods will help copper foil manufacturers improve manufactured products quality and accelerate new product development. New and better foils will contribute to advancements in PCB manufacturing and overall 5G technologies.

Bio:
Dr. Malgorzata Celuch is President and Senior Scientist at QWED, a high-tech SME which she co-founded in 1997. Her background (Ph.D. 1996 from the Warsaw Univeristy of Technology) is in Computational Electromagnetics and she is lead co-author of QuickWaveTM multiphysics simulation software commercialised by QWED. Since early 2000s, her research focuses on the development of methods and instruments for precise measurements of materials in microwave and mmWave ranges.
Dr. Celuch is author of 170+ scientific peer-reviewed papers and 6 monograph chapters, and recipient of 10+ awards for excellence. She has been team leader in international R&D projects, under the European Framework Programmes and the International Electronics Manufacturing Initiative, currently: M-ERA.NET “I4BAGS” and iNEMI “5G Copper Foils”. She is active in IEEE (Vice-Chair of TC MTT-) and the European Materials Modelling Council (member of BoD). She serves as an expert for the European Commission.

 

This presentation will introduce the iNEMI project output on thin-sheet material characterization in mmWave range. To characterize the properties of packaging materials, substrate, and PCB, etc., is one of the most fundamental and critical challenges to solve to widely deploy mmWave technology. iNEMI project team has over 26 companies collaborating from 2020 to investigate the best practices of commonly acceptable and appropriate measurement methods in existing industrial standards. But there is still lake of a real “standard” for researchers and manufacturers to make judgement for material development, measurement validation, material acceptance and quality assurance. Then the iNEMI project started to explore standard reference material (SRM) for dielectric permittivity and loss tangent in the mmWave regime. In this presentation, we will show the results of round robin experiments and show the progress toward SRM development. There are still issues to overcome for SRM development that will be discussed in this presentation. In addition, the NIST (National Institute of Standards and Technology) Office of Advanced Manufacturing supports the team to define the roadmap of the work. The audience who are interested in the SRM development and its roadmap are welcome to join in this project which helps to enhance mmWave applications.

Bio:
Chang-Sheng Chen has experience on RF, microwave and mm-wave circuit as well as the antenna design with system-in-a-packaging. He and his team built the “Sub-THz System Laboratory” which facilitates various mm-wave measurement instruments that can provide a wide variety of customized testing service from PCB substrate materials, RFICs, antennas, and even the whole system such as 5G mobile phone to and satellite transceivers. The “Sub-THz System Laboratory” has been certificated under ISO17025 that can be a neutral third-party testing laboratory.

 

Outline:
1.Requirements for AI package
2.HBM
3.High-density interposer
4.Large area substrate

Bio:
E. Jan Vardaman is president and founder of TechSearch International, Inc., which has provided market research and technology trend analysis in semiconductor packaging since 1987.  She is the author of numerous publications on emerging trends in semiconductor packaging and assembly. She served on the NSF-sponsored World Technology Evaluation Center (WTEC) study team involved in investigating electronics manufacturing in Asia. She is a senior member of IEEE EPS and is an IEEE EPS Distinguished Lecturer. She received the IMAPS GBC Partnership award in 2012, the Daniel C. Hughes, Jr. Memorial Award in 2018, the Sidney J. Stein International Award in 2019, and she is an IMAPS Fellow. She is a member of MEPTEC, SMTA, and SEMI. Before founding TechSearch International, she served on the corporate staff of Microelectronics and Computer Technology Corporation (MCC), the electronics industry’s first pre-competitive research consortium.

 

Outline: AI Market Trends, Impact on Semiconductor Industry, Packaging Platforms & Materials Enabling AI

Bio:
Rozalia has a broad cross-industry and functional experience in the electronics & semiconductor industry and a rewarding multicultural experience, having worked and lived in various countries around the world. A large part of her career (25 years) was directly involved and supporting Advanced Packaging where she had several leadership & executive roles with various organizations across the supply chain:
- Electronic Materials:
o Research Scientist and Advanced Packaging R&D Program Leader with Rohm and Haas Electronic Materials in Long Island New York
o Executive Director Corporate Strategy and New Business Development with Dow & DuPont, in Marlborough, Massachusetts.
o Terecircuits: Advisory Board Member
- Equipment:
o Principal Engineer and Global Director of 3D Interconnect with Semitool in Kalispell, Montana, Director of Technology Pathfinding and Transfer with Applied Materials in Santa Clara, California
o Sr. Director of Customer Applications Technology Group, Operations & Metrology with Lam Research in Villach, Austria
- Device Manufacturing: Director of Technology R&D with Maxim Integrated Products in San Jose, California
- Market Research & Strategy Consulting: Yole Developpement (CTO and Advanced Packaging, Semiconductor Manufacturing Director) in Lyon, France
- Substrates: AT&S (CSO and VP Strategic Marketing & Business Development ) in Leoben Austria, Shanghai China and Penang, Malaysia (where she is currently located)

Rozalia is actively involved in various industry activities. Past & current activities include: Member of the Board of Governors for IEEE Electronics Packaging Society, ECTC Executive Committee member, General Chair of 2022 ECTC (currently Sr. Past General Chair), Chair of the Heterogeneous Integration Roadmap WLP Technical Working Group, Executive Chair of System in Package China Symposium, Advisory Board Member 3DinCites and IMPACT Taiwan, IMAPS VP of Technology, General Chair IMAPS DPC, Program Director EMC3D Consortia, General Chair Global Semi & Electronics Forum, Technical Advisory Board Member SRC, Chair of the SEMI Strategic Materials Conference, Executive Committee Member of ESTC and 3D Summit Europe, and several other committee memberships. Rozalia has over 175 presentations & publications, including 3 book chapters on 3D Integration and received several industry awards including 2006 R&D 100 Award for development of SnAgCu electroplating technology for wafer bumping and IMAPS 2020 Leadership Award.
Rozalia has a M.Sc in Chemical Engineering from Polytechnic University Timisoara (Romania), a M. Sc. In Management of Technology from KWU (USA) and a Global Executive MBA from IE Business School (Spain) in partnership with Brown University (USA), Fudan University (China) and Insper University (Brazil)

 

.

 

.

 

Thermal stress in Cu pads at temperatures from -55C to 150C
- Effective Thermal Expansion Coefficient of Cu pads in SiO2 vias.
- Thermal cycling tests.
- Electromigration tests.
- High temperature storage tests.

Bio:
Prof. Chih Chen is currently the chair professor in Dept. of Materials Science and Engineering, National Yang Ming Chiao Tung University (NYCU).
Professor Chen discovered electrodeposition of (111)-oriented nanotwinned Cu, and reported it in Science 336, 1007-1010 (2012), and transferred the technology to Chemleaders, Inc, Taiwan for mass production in 2016. Therefore, he received the 2016 National Innovation Award, 2018 & 2023 Outstanding Researcher Award from National Science & Technology Council Taiwan, TMS 2018 Research to Practice Award from The Minerals, Metals & Materials Society (TMS, USA).

 

Driven by AI and 5G, advanced packaging technology focuses more on homogeneous integration and heterogeneous integration of Chiplets to meet high computing performance, low latency, and high-density interconnection. Fan out wafer level package (FOWLP) efficiently enable higher I/O counts for high performance edge computing by re-distribution organic layers (RDL).
Therefore, this study is that we propose a fan out multi-chip module (FO-MCM) with chip-first process for the homogeneous integration. Compared with FO-MCM chip last solution, due to the short process, it can save materials and processing costs and provide customers with lower cost options and better high frequency signal integrity.

 

In the packaging industry, Fan-out Panel Level Packaging (FOPLP) is considered advanced technology. It can achieve heterogeneous integration platform and reduce cost though extending utilization area of larger manufacturing format

Electroplating (ECP) copper in redistribution layer (RDL) plays an important role of FOPLP system that it determines the electrical and mechanical properties of packaging structure. However, RDL thickness uniformity control in large system is very difficult. Furthermore, product with similar plating open ratio only suitable in the same shielding/sharing parts, these limit the utilization area of FOPLP product

The study provide an efficient solution via optimal ECP shielding/sharing parts determination and well-designed modulating pattern that not only improve RDL thickness non-uniformity from nearly 30% to under 15% but also provide a universality ECP hardware suit for 17-66% plating open ratio which cover each product.

 

Since the Meta, Amazon, Google and Microsoft are the popular social media and search website related with our daily life, the artificial intelligence (AI) with cloud computing become one of the most importanrt for semiconductor industury. The cloud computing, high performance computing and artificial intelligence solutions require big data analysis processing with faster connections than ever, and all of these will need to have advanced technology supporting.
The rise in energy costs and the increasing demand for sustainability to reduce environmental impacts further increase people’s desire for high performance and high efficiency computing. The complex dataset has been tremendously grown on commercial application and widespread adoption of deep learning and neural networks. The advanced node with System on Chip (SoC) chip size extension may the simplest design solution for good electrical performance, but the low yield rate will cause very expensive cost. The split die integration in package is the best solution to increase gross die with wafer good yield rate for cost effective. The demand for higher functionality devices drives integration technologies to overcome limitations in Moore’s Law and the Fan Out Multi Chip Module (FO-MCM) package can take the role for Cloud computing and consumer applications that calls from Cloud to Edge.
Today, the consumer product always request not only thiner and power stamina but also high speed and massive connectivity for data transmission. The FO-MCM package can do the homogenous integration and heterogeneous integration for each of different application because the cloud computing and edge computing need to meet the high performace and good electronic performance design requirement. That is the reason FO-MCM package solution can be the presentative for homogenous integration and heterogeneous integration.

In this paper, we would like to discuss what the advantage for FO-MCM package and why this package can be used for different applications. The package will demonstrate the homogenous integration package and heterogeneous integration package solutions for Edge and Cloud computing applications.

Key words: artificial intelligence (AI), Fan-out Multi Chip Module (FO-MCM), System on Chip (SoC)

 

Recently, panel level packaging becomes promising in the global market from increasing request in the future. The advantages of panel level packaging are low cost, high utilization area, high performance and productivity benefits. However, large panel also face many challenges, die shift, warpage , coefficient of thermal expansion(CTE), Due to size and area effect, warpage issues caused more serious than wafer level during process significantly, using simulation modeling of 600X600mm large panel , put into the same material ,epoxy mold compound (EMC) , polyimide(PI), Copper(Cu), release film, silicon die with copper pillar in the structure and major on trend of warpage behavior.
Based on M-series design rule on 600X600mm large panel. The key factors of warpage , EMC thickness, coefficient of thermal expansion(CTE), flexural modulus, fan out ratio , and focus on redistribution layer(RDL), after cure process , finally compare with based on embedded wafer-level ball-grid array (eWLB) panel level. Fig1.show model of 600mm panel level, based on M-series/eWLB structure, 2 passivation layer , 2 metal layer(2P2M).The simulation of all parameter work in the ANSYS software. And import material properties into the model.
On the basis of design rule, possibility of request, and machine limit, selecting EMC thickness (include die) 0.275mm,0.565mm,0.675mm .On CTE study, fixed EMC CTE1,2(ppm/°C) for multiple increasing ,1.0X, 1.5X, 2.0X, 2.5, 3.0X, because of continuous material properties and most of the EMC .The flexural modulus is also critical factor on warpage , fixed EMC >Tg,

 

As the wavelength of an electromagnetic (EM) wave becomes comparable to the physical size of an electronic packaging, antenna-in-packaging (AiP) which integrate an antenna into a packaging is a suitable solution for future 5G and internet of things (IoT) applications. Since a fan-out antenna-in-packaging (FO_AiP) incorporates microstrip antennas with a fan-out packaging structure, it takes the advantages of low profile, simple, low weight, and better electromagnetic performances [1]~[2]. To introduce design flexibility and to improve the radiation properties of the antenna in a FO_AiP, a self-designed, embedded glass with single- or double-sided redistribution layers (RDLs) has been introduced into the packaging structure (Figure 1). With the new design, an aperture-coupled microstrip patch antenna was successfully integrated with the FO packaging for 60 GHz, millimeter wave applications [3]~[5]. However, the 3 mm by 3 mm planar antenna dimension in our previous designs are relatively large for future antenna arrays.
In this study, the size of a single glass embedded FO_AiP was minimized to 2 mm from 3 mm without reducing its performances. To this end, the ANSYS HFSS software was employed for electromagnetic characteristic simulations on the FO_AiP structure designs. According to the experiences from our early studies, 6 parameters including substrate length, micristrip and slot length, slot and patch position, and cap height were first picked as the design factors. A single-factor analysis was next performed to characterize the radiation performances of the antenna used for 60 GHz. For design optimization, a consecutive procedure was followed by individually switched the design factors at each step with the best design from the previous step. Based on the return loss S11 = -10 dB criteria, an FO_AiP structure with 3.96 GHz bandwidth and 5.5 dB gain at 60 GHz was finally proposed.

Keywords : FO_AiP, glass-embedded FO packaging, size reduction.

 

Fan-Out Panel-Level Packaging (FO-PLP) has emerged as a high-usage efficiency and cost-effective solution for advanced packaging. However, the challenge of excessive warpage significantly impacts its yield and reliability. To address this issue, this study focuses on analyzing the warping behavior using the Finite Element Method (FEM). Additionally, Process Modeling technology is employed in the simulations to enhance their realism and alignment with actual processes.
The primary objective of this study is to investigate the factors contributing to the emergence of asymmetrical patterns in PLP. Various influential factors are taken into consideration, including geometrical uncertainty, material uncertainty, working platform inclination, and the influence of vacuum release paths
While simulations offer advantages in terms of time and cost, inconsistent results may arise due to variations in modelling approaches used by different researchers in finite element analysis. To overcome this challenge, the study proposes the utilization of artificial neural network (ANN) algorithms for warpage prediction in FO-PLP. The methodology involves constructing finite element models of different scales and establishing a training database based on these models. Subsequently, the ANN model is optimized by fine-tuning hyperparameters to obtain the most accurate predictive model.
The proposed ANN model is expected to provide precise predictions of FO-PLP warpage in a shorter time compared to conventional simulations and experiments while ensuring reasonable accuracy. By harnessing the capabilities of machine learning, this study aims to overcome the limitations of traditional simulation methods and enhance the efficiency of FO-PLP warpage prediction. The findings of this research are anticipated to contribute to optimizing and improving the FO-PLP process, thereby enhancing the yield and reliability of advanced packaging applications.

 

Power modules play a critical role in the efficient and reliable operation of various electrical systems, ranging from renewable energy systems to electric vehicles. The demand for higher power density, increased efficiency and improved thermal management has led to the use of silicon carbide (SiC) MOSFETs. To take advantage of the excellent switching characteristics of SiC at very low losses, the use of new packaging technologies is required. Embedding MOSFETs in PCB structures offers numerous advantages, including lower parasitic inductance, improved heat dissipation, and enhanced switching performance.
Various concepts for realizing modules with embedding technology are discussed. Design, fabrication and performance of realized modules up to 900 V and 850 A are presented.

Bio:
Andreas Ostmann, born 1966 in Berlin, studied Physics and received his Ph. D. in Micro System Technologies at the Technical University of Berlin. Since he joined Fraunhofer IZM in 1992, his research focus is on advanced packaging technologies. He is head of the department System Integration and Interconnect Technologies. His research group is involved in the developed of large-area processes for chip embedding, System-in-Package and advanced substrates. Andreas is author of a large number of publications and holds several patents on advanced packaging technologies.

 

Power electronic (PE) converters in EVs determine a large part of the vehicle’s efficiency and power output, with trends moving toward smaller, high-power-density components. Power electronic devices are the critical elements in electronic converters for functions and costs. The Department of Energy (DOE) in the US has set an efficiency target of 98% and a power density target of 100 kW/L for automotive PE by 2025. SiC inverters have had a higher peak power and power density compared to Si devices [2]. The increase in power density and decrease in size can lead to poor heat dissipation and thermal stress, which in turn leads to additional failures of power converters. Because electric vehicle power modules must adapt to harsh environments and meet 15-year life requirements, thermal management becomes a critical challenge. Thermal solutions of power modules can be implemented as indirect, direct, or double-sided cooling methods and can have a large impact on the performance of the system [3]. The optimum thermal design of SiC power modules has significant effects on system performance. The thermal performance of the direct cooling SiC power module with the pin fin heat sink is studied by numerical and experimental measurements [4, 5, 6]. However, improving the thermal performance of the power module requires optimization of the heat sink design.
In this paper, we studied the thermal design of the 1200V, 400A SiC power module for EV/HEV applications by numerical simulation and experimental measurement. The SiC power module has 3 phases of topology. SiC semiconductor devices are soldered on the AMB ceramic substrate, interconnected by aluminum wire bonding. The AMB ceramic substrates are soldered to the heat sink, as shown in Figure 1. We studied the optimum design of the circular pin fin by Multi-parameter Optimization (HEEDS) method. The parameters are pin diameter, pin pitch, and pin height. We compare the thermal performance of the shapes of pin fin, including circular fin, droplet fin, and oval. The flow patterns of the liquid jacket are another important factor of thermal performance. Two different flow types serial and parallel are studied. The thermal performance of the plate fin was also analyzed and compared with the pin fin. Finally, the experimental measurement of heat sinks is conducted to measure the thermal performance of heat sinks.

 

Power electronics and devices are essential technologies to enable an efficient electrical energy distribution, usage and generation. In the last few years, due to current silicon-based power devices showed several limitations, wide band gap (WBG) i.e. silicon carbide (SiC) and gallium nitride (GaN) semiconductors are replacing silicon-based semiconductor for the higher performance and temperature applications in the field. WBG devices show superior performances in terms of device operation in harsh environments such as higher temperatures, voltages and switching speed than silicon-based technology. In power devices, the reliability of the devices and module package is the critically important to guarantee the normal operation and lifetime of the devices.
Recently, silicon nitride (Si3N4) ceramic has attracted attention due to its inherent performance (e.g. excellent mechanical properties, high chemical stability, low dielectric constant, and superior wear and thermal shock resistance) and the improved performance such as high thermal conductivity, making it a candidate as the next-generation substrate material for high-power electronic devices. In many of these applications the ceramic/metal composite substrates not only provide electrically conducting paths with low resistivity and electrical insulation between circuit layers and heat sinks, but also provide thermal paths between heat sinks and chips.
Furthermore, Si3N4-active metal braze (AMB) ceramic/metal components substrate has been widely used to manufacture the package substrates for high-power and high-current density electronics such as insulated gate bipolar transistors (IGBT) modules. In the fabrication process, a functional metal with low electrical resistivity, such as copper (Cu), is bonded to a ceramic substrate thus facilitating the transmission of electrical energy and signals for electronic components or chips. However, with the rapid development of modern power electronics, the miniaturization and integration of electronic devices induced the increased power density that puts forward a high requirement for thermal properties and mechanical reliability of substrates used.
In this study, we investigate the effect of the microstructures and surface roughness of the Cu surface on the Si3N4-active metal braze (AMB) ceramic/metal components substrate were carried out respectively by optical microscope (OM), scanning electron microscope (SEM) and 3D optical profilometer. In this way, the influence of substrate roughness with different physical and chemical surface treatment could be understood better. On the other hand, we also study the wire pull testing as well as the bond adhesion of surface roughness by varying surface treatment of the Cu. This study can help us understand how the confinement influences the properties of Cu. Thus, this article investigates the influence of surface roughness and morphologic effects of silicon nitride active metal brazing substrates following different surface treatments.

 

Silicon Nitride (Si3N4) is one kind of ceramic materials which have excellent mechanical properties, low thermal expansion coefficient, and better oxidation resistance. In the past, Si3N4 are commonly used to be materials in military industry, aerospace technology, integrated circuit and micro mechanical structure. With the stronger development of third generation semiconductor and electric vehicle industry in recent years, there are more and more high-power application. Si3N4 become the potential materials in high power module because of good thermal and mechanical properties.
Direct plated copper (DPC) is a technique to build up metallization on ceramic substrate. At first laser via drilling on ceramic substrates, then go through physical vapor deposition, lithography, copper plating, photoresist removal, etching and surface finishing treatment. Today DPC substrate are widely used in critical heat dissipation application, for example high-power LED, RF microwave communication, laser system, and semiconductor equipment, etc. The common ceramic materials in DPC are aluminum oxide (Al2O3) with fracture strength 500 MPa, fracture toughness 3 MPa･√m and aluminum nitride (AlN) with fracture strength 450 MPa, fracture toughness 3 MPa･√m. Si3N4 has higher fracture strength 800 MPa and fracture toughness 6.5 MPa･√m than Al2O3 and AlN, that means Si3N4 is the better materials to be thinner substrate with lower heat resistance and less substrate broken rate during DPC manufacturing.
The purpose of this study is to apply DPC techniques on Si3N4 ceramic materials. The study started from laser via drilling, and then went through a series processes including physical vapor deposition, lithography, copper plating, photoresist removal, etching and final surface finishing treatment. After whole DPC flow finished, several analysis and test are done on the finished DPC product. Verification items including appearance, electrical test, cross section observation, X-ray via image, wire pull test, tape test, knife test and high temperature reflow test.
Final results showed Si3N4 DPC substrate has normal appearance, there is no cosmetic issue after whole DPC flow. The via resistance are lower than 0.008 ohm, there is no via open defect. Good via filling, copper plated on Si3N4 via side wall is consistent, and there is no plating via void. Wire pull test, tape test, and knife test all show good adhesion between metallization and Si3N4 interface, no delamination or peeling off happened. High temperature reflow results also did not show delamination or peeling off, that means Si3N4 DPC substrate can survive at working temperature 260°C and 310°C, even underwent 3 times reflow profile.
By this study, we confirmed that Si3N4 can be DPC ceramic materials. With its excellent mechanical properties, low thermal expansion coefficient, and better oxidation resistance, Si3N4 DPC substrate would be a good choice for high power application in third generation semiconductor and electric vehicle industries.

 

High voltage devices are gaining more attention and widely used in many applications especially on automotive that requires higher reliability performance. The reliability performance of molding compounds for two types of products with different polarities from the same family are compared during HTRB testing at 150 °C in this study. The device vehicles identified for this study are transistors from a typical high-power (350-500V) Cu-wire bonded plastic molded leaded package. During High Temperature Reverse Bias (HTRB) test, high electrical fields are applied on the device, this tends to drive the transport of ionic elements from the encapsulation materials such as molding compounds towards the die which may cause an accumulation of charges at the highly active areas like ball bond IMC, die top passivation and mold compound layer interface.
This paper investigated the ion migration in molding compounds towards the ball bond IMC and die passivation depends on the applied bias direction of the two product types resulting to two different failure signatures observed. Furthermore, critical mold compound material properties and their role on the ball bond IMC degradation and device leakage current on die passivation and mold compound layer interface due to ionic movement during high voltage test conditions were discussed. Typically, a mold compound with high glass transition temperature (Tg) would be preferred for high voltage application, however the trade-off would be on the delamination performance. Therefore, a balance between high voltage reliability and delamination resistance is desirable and a key consideration for future package development. An experimental design was conducted to validate the performance of different molding compounds capable of delamination-free package at T=0 and after MSL1 on selected device vehicles for investigation and analysis.
High voltage HTRB reliability test results showed that failure signature on devices where positive bias was applied resulted to IMC ball bond degradation while devices where negative bias was applied resulted to a leakage current failure. Higher leakage current failures were found to be driven by the increase in voltage applied while ball bond degradation was more driven with the increase in temperature and test duration. The failure mechanisms from the failed units were further studied and discussed in this paper. HTRB leakage current and breakdown voltage graphs were analyzed to identify the electrical characteristics during failure analysis. Cross-section and SEM images were gathered to visually inspect the samples, EDX was then performed to identify presence of ionic accumulation on active areas, while ball bond inspection was conducted to compare the failure signature between the positive and negative biased high voltage devices. Overall results from this study provides a better understanding on the behavior of molding compounds and failure mechanisms related to molded leaded packages for high voltage applications.

Keywords: Molding Compound, High Voltage, HTRB, IMC, Leakage Current

 

Recently, power semiconductor devices and power modules have various applications with a high market growth rate and industrial value. However, there are still some issues that have not been fully addressed. For example, the power loss generated by the internal power semiconductor devices of power modules during system operation can cause significant temperature rise, and high temperature can seriously affect the performance and reliability of the power module structure [1-4]. Therefore, accurate power loss calculation is crucial in power module development. This study attempts to establish an electromagnetic-circuit co-simulation (ECC) model to evaluate the power loss of the developed SiC/Si integrated hybrid power module (as shown in Fig. 1) during the three-phase operation. The developed SiC/Si integrated hybrid power module is used as a variable frequency drive (VFD) in a servomotor system. The topology of the developed SiC/Si integrated hybrid power module is shown in Fig. 2, which includes a brake circuit with a Si IGBT and Si diode, a three-phase rectifier composed of 6 silicon diodes, and a SiC inverter consisting of 12 SiC MOSFET devices. To accurately evaluate the switching transients of the devices, the temperature-dependent characteristic curves from the datasheet are considered in the ECC model. Moreover, the influence of parasitic inductance, resistance, and capacitance on the switching transients and power loss is considered by integrating the electromagnetic simulation. The ECC model is shown in Fig. 3. The ECC model comprises four main components, namely the three-phase resistive load, SiC inverter, three-phase rectifier, and AC input. The three-phase operation of the SiC inverter in the developed SiC/Si integrated hybrid power module is controlled by the effective utilization of space-vector pulse width modulation (SVPWM) of the voltage, combined with delta-shaped resistive load to generate the output power of 12 kW. To reduce the effect of noise on the output waveform (Fig. 4), an LC filter is incorporated between the AC output of the SiC/Si integrated hybrid power module and the three-phase resistive load. Additionally, the effectiveness of the ECC model has been validated through the output waveform result from the open-loop three-phase inverter operation experiment with operating the SiC inverter in the developed SiC/Si integrated hybrid power module [5]. The power loss results calculated from the ECC model consist of switching loss and conduction loss of the SiC MOSFETs, reverse recovery loss and diode conduction loss of the body diodes, and the diode loss of the Si diodes in the three-phase rectifier (Table 1). Finally, the parametric analysis investigates the impact of temperature on the power loss of the developed SiC/Si integrated hybrid power module during three-phase operation.

 

In the development of electric vehicles and 5G communication technology has led to increased interest in high-power devices, prompting advancements in materials and designs for various applications. Wide bandgap (WBG) semiconductor materials like silicon carbide (SiC) has lots of advantage against to silicon such as higher breakdown voltage, affordability of high junction temperature, and higher thermal conductivity. Therefore, it is considered a promising substitute for silicon in high-power devices.
However, as these devices operate, they generate a significant amount of heat, often reaching temperatures above 250 °C. Effective heat dissipation becomes crucial for ensuring device reliability. Die attach thermal interface materials (TIM) play a significant role in bonding the chip to the DCB (direct copper bond) substrate and the substrate to the heat sink in high-power devices, facilitating heat transfer. Traditional die attach TIM, such as solder and polymer-based materials, are unable to withstand such high operating temperatures and have lower thermal conductivity.
Therefore, new TIMs need to be developed. Metal such as silver and copper are good choice because of the high melting temperature and thermal conductivity. Thus, double-sided highly <111>-oriented nanotwinned copper foil is fabricated using electroplating process. The highest surface diffusivity and lowest oxidation rate make it a good choice for diffusion bonding. High bonding bonding quality can be seen using FIB. Only few seam and viod in the bonding interface which is inevitable since the high roughness of copper substrate. Furthermore, high bonding strength above 15MPa can be obtained in the bonding condition at 250 °C for 30 minutes under 30 MPa with the copper substrate. In contrast, the bonding is failed when there is not double-sided highly <111>-oriented nanotwinned copper foil sandwiched in between which shows the great potential for die attached TIM

 

• Technical roadmap of advanced semiconductor package
• Evaluation platform for liquid encapsulant development
• Evaluation of liquid encapsulant in flip chip package and wafer level package
• Summary

Bio:
Chih Hao Lin received her Ph D degree of Material Science and Engineering from National Yang Ming Chiao Tung University in 2021 He is currently an Researcher of the Materials and Chemistry Laboratory, Industrial Technology Institute His research area focus on the development and evaluation of Optical electrical, semiconductor and compound semiconductor encapsulant materials.

 

1. Power chip and its application in EV.
2. The purpose of power chip embedding PCB.
3. The construction and process of power chip embedded PCB.
4. SiC chip embedded PCB and its processing difficulties.

Bio:
Jason Lee got his master degree from chemical engineering department of Tsing Hua university in 1987. He worked for PCB industry in military shop and Boardtek Electronics for 42 years. After his retirement in 2022, he kept working for Boardtek, ITRI and EMC as a consultant. His main interest is in PCB technologies for RF, high speed digital, high power and thermal simulation.

 

In the near future, electrical and mechanical design will be integrated, and a design environment that smoothly links with analysis will become important. Based on this idea, I will introduce ZUKEN’s 3D design environment "Design Force".

Bio:
Personal name
- Masaomi Suzuki

Job title
- Business Development Manager

Career
-Working in overseas business for 24 years at ZUKEN as:
Application Engineer
Project manager working with global major customers
Product marketing
Application Engineer Manager at Zuken Taiwan
Asia-Pacific Regional Engineering Manager at Zuken Singapore
Business Development Manager at Zuken Inc. (Japan)

Specialized field
-Schematic & PCB design
-Package design
-Electro-mechanical collaborative design

 

1. Introduction
2. Activities of International Standard for device embedded substrate at IEC
3. Conclusions

Bio:
Yoshihisa KATOH
・He received Ph. D. degree from the Shizuoka University, Japan in 2011.
・Since 2019 he is guest professor at the Institute of Microelectronics Assembling and Packaging at the Fukuoka University, Japan.　
・Since 2012 to 2018 he was professor at the Fukuoka University.
・He is vice chairman of the Committee of EPADs (Embedded Passive and Active Devises ), at JIEP (The Japan Institute of Electronics Packaging).
・He has been working on device embedded substrates and high density wiring of Printed Wiring Board throughout his working career in companies and university.
・He is chairman of ""The research committee of standardization for device embedded technology"" in Japan.
・He is co-convener of IEC TC91 WG6.

 

.

 

Bio:
Ksenija Varga is business development manager at EV Group where she focuses on new application development of maskless exposure technology. Apart from business development, Ksenija is involved in strategic projects with focus on semiconductor tool development for future technologies. Prior to EV Group, Ksenija was working at FujiFilm Electronic Materials with Head Quarter in Belgium. Ksenija holds doctorate degree in natural sciences/chemistry from University Innsbruck in Austria. After University, Ksenija started her career as R&D project leader in the chemical industry and held several positions in R&D, business development and account management.

 

Die to wafer Hybrid Bonding plays a key enabling role in the assembly of advanced Heterogeneously Integrated products. This assembly technology is now in production with key suppliers and significant growth is projected. The Cu to Cu Hybrid bonding process has a die placement accuracy of <200nm using a room temperature process followed by a batch thermal anneal. The presentation will cover the driving factors supporting the growth of die to wafer Hybrid bonding as well as the equipment and process used to enable this assembly operation.

Bio:
Tom Strothmann is the Vice President of Besi North America. He joined Besi in 2018 to manage their North American operations and to promote Besi’s Advaced Packging equipment. Before joining Besi, he worked with K&S to commercialize their TC Bonders and for STATS ChipPac, promoting Fan-in and Fan-out WLP. Prior STATS ChipPAC he was VP of Business Development for FlipChip International, founding the startup of FlipChip Millennium Shanghai Co. Tom has over 25 years’ experience in process engineering and business development for Wafer Level Packaging products.

 

In recent years, as the amount of information handled increases significantly on a global scale due to the growing adoption of AI technologies across various industries and applications, there is an urgent social demand for enhanced performance and efficiency in systems of CPUs and HBMs for data centers. 3D chiplet integration technology is attracting attention as a promising technology that can satisfy the aforementioned social demand.

Various benefits for dry etching can be obtained by superimposing RF of different frequency on the 13.56 MHz RF normally used in the ICP formation. We have developed a plasma source effective for silicon etching, and invented a TSV etching technique called the "Dual TSV process". Our new silicon etching technique achieves the minimization of aspect-ratio dependent etching lag, and thus contributes to fabricating TSVs of two different diameters at a uniform depth, which enable high-density wiring by reducing the area occupied by TSVs in the wiring area. The same plasma source can also be used to enable plasma dicing based upon non-Bosch etching method.

To date, plasma dicing is commonly performed by Bosch method, resulting in formation of scallops on the side surface. Fine deposits adhering to the scallops are expected to be a source of particles. By using our newly developed plasma source and the non-Bosch etching method, dicing with smooth sidewalls has been realized. So far, blade dicing and laser dicing have been widely used, but the generation of particles can cause a decrease in the yield of die to wafer or die to die bonding. The problem of particles is becoming more and more critical regarding the advanced chip-package interconnections based upon hybrid bonding. Our non-Bosch dicing technique potentially contributes to the reduction of particles and thus the yield enhancement of hybrid bonding.

This presentation will introduce ULVAC's efforts to improve device performance with 3D chiplet integration technology and the new novel silicon etching technology described above.


Bio:
Taichi Suzuki received the master degree in Electrical and Electronic Engineering from University of Yamanashi, Japan, in 2008.
From 2008 to 2020, he used to be engaged in R&D of MEMS manufacturing processes in ULVAC, Inc. He has been engaged in R&D of etching systems for TSV up to the present since 2020. He enjoys Kyudo (Japanese archery).

 

It is well known that the carbon nanotubes (CNT) intrinsically have superior axial thermal conductivity. In the past, many research efforts attempted to apply CNT in electronic packaging to enhance the thermal performance of devices or modules. Nevertheless, even after 3 decades of presence of CNT, people still could not implement meaningful applications of CNT in the packaging of microelectronics. The present research intends to propose an innovative approach to make use of the superior axial thermal conductivity of CNT for heat conduction, in particular, for the thermal management application in 3D stacked IC packaging. We propose firstly to bond two substrates together with a fixed gap in between. This configuration will form two parallel surfaces. Subsequently two large areas of CNT will be grown simultaneously from the two parallel surfaces into each other. This face-to-face fabrication will bring CNT from the two sides to contact and eventually become interlaced. The interlaced CNT will provide better mechanical contacts and even allow some CNT from two sides to fuse together, becoming continuous CNT. These phenomena will certainly enhance the heat conduction between the two parallel surfaces. The configuration of parallel surfaces with a fixed gap happens to be the actual situation of 3D stacked chips. It is foreseeable that the outcome of the present research may lead to a revolution to the thermal management in 3D stacked IC packaging.

Bio：
Ricky Lee received his PhD degree in Aeronautical & Astronautical Engineering from Purdue University in 1992. After one year of post-doctoral research at Purdue, he joined the Hong Kong University of Science & Technology (HKUST). During his career of tenure-track faculty at HKUST, Dr Lee once was on secondment to serve as Chief Technology Officer of Nano & Advanced Materials Institute for two and a half years. Currently Dr Lee is Chair Professor of Smart Manufacturing Thrust and Acting Dean of Systems Hub at the HKUST Guangzhou Campus HKUST(GZ). He also has concurrent appointments as Executive Director of Shenzhen Platform Development Office, Director of Electronic Packaging Laboratory, and Director of Foshan Research Institute for Smart Manufacturing at HKUST. Dr Lee has been focusing his research on the technology development for electronics/optoelectronics packaging and additive manufacturing. The topics of his R&D interests include wafer level packaging and heterogeneous integration, 3D printing for microsystems packaging, LED packaging for solid-state lighting and applications beyond lighting, lead-free soldering and reliability analysis. The research outcomes of Dr Lee’s group have been documented in numerous technical papers in international journals and conference proceedings. He also co-authored 4 books and 10 book chapters. Due to his technical contributions, Dr Lee received many honors and awards over the years. In addition to being the recipient of 15 best/outstanding paper awards and 7 major professional society awards, Dr Lee is Fellow of IEEE, ASME, IMAPS, and Institute of Physics (UK). He is also Editor-in-Chief of ASME Journal of Electronic Packaging.

 

The Post-Moore and More-than-Moore paradigms necessitate advancements in packaging technology to increase the density of I/O connections [1]. Achieving this requires the fabrication of smaller microvias in a build-up substrate. Currently, the size of microvias in advanced semiconductor package is 40 µm, which is achieved by CO2 laser processing. However, the diffraction limit of light restricts the achievable focus size because of the long wavelength of the CO2 laser (9.3 μm), making it impossible to drill microvias with smaller diameters. Consequently, the development of a next-generation drilling technique is necessary to meet the demands imposed by Moore's Scaling law.
Photolithography-based microvia fabrication, known as photovia, is a candidate for miniaturization of via holes. However, there are significant barriers associated with changes in materials and equipment. Therefore, laser-based solution would be of great interest for next-generation semiconductor packaging.
One promising solution to address this issue is the use of a deep ultraviolet (DUV) laser with a wavelength at 266 nm for laser-via fabrication instead of the CO2 laser. In our previous work, we demonstrated the fabrication of sub-6 μm via holes with a 75% taper ratio on Ajinomoto build-up film (ABF) by employing DUV laser processing, aided by an artificial intelligence parameter search system [2,3]. However, the Moore's law demands the achievement of even smaller diameters in next-generation build-up substrates.
In this work, we improved the optical system and realized sub-4 µm microvias on ABF. To achieve this, we used a DUV laser light source produced by Spectronix Co., which was integrated into a specially designed Mitsubishi Electric laser processing machine. This system consists of a galvo-mirror and an f-θ lens, enabling high-speed processing. Through an extensive search for laser drilling conditions across multiple parameters, we successfully achieved sub-4 μm microvias on a 5 μm-thick ABF. Notably, our drilling method eliminates the need for sample preprocessing, such as applying additional coatings on ABF, which is typically required to create small microvias. The drilling process for each via took less than 100 μs.
We evaluated microvia by using scanning electron microscope (SEM) image with the backscattered electron imaging mode. No debris or deposits are found around the hole. The hole diameter on the surface in the horizontal axis is measured to be 3.83 μm, whereas that at the bottom is 2.76 μm. This corresponds to a taper ratio of 72%. Likewise, the hole diameters on the surface and bottom in the vertical axis are 3.77 μm, and 2.65 μm, corresponding to a taper ratio of 70%.
In conclusion, we demonstrated the fabrication of sub-4 um microvia using an improved DUV laser processing system. In the future, we plan to investigate the fabrication of smaller vias by further improving the light focusing conditions.
[1] R. Mahajan et al., "Embedded Multi-die Interconnect Bridge (EMIB) -- A High Density, High Bandwidth Packaging Interconnect," 2016 IEEE 66th Electronic Components and Technology Conference (ECTC), Las Vegas, NV, USA, 2016, pp. 557-565, doi: 10.1109/ECTC.2016.201.
[2] Y. Kobayashi et al., "Cyber-Physical System of laser micro processing for semiconductor package fabrication," 2022 17th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT), Taipei, Taiwan, 2022, pp. 1-4, doi: 10.1109/IMPACT56280.2022.9966708.
[3] Yohei Kobayashi, Takashi Takahashi, Tomoharu Nakazato, Haruyuki Sakurai, Hiroharu Tamaru, Kenichi L. Ishikawa, Kazuyuki Sakaue, and Shuntaro Tani, "Fully Automated Data Acquisition for Laser Production Cyber-Physical System,"IEEE Journal of Selected Topics in Quantum Electronics, vol. 27, pp. 1-8 (2021)

 

As the speeds of mobile communication systems continue to accelerate, the demand for semiconductor technologies that are able to transmit vast quantities of information at high speeds with low latency is also increasing rapidly. Advanced back-end processes that can integrate multiple semiconductor devices in three dimensions are becoming increasingly important to the realization of this goal.
The flip chip bonding technique with its low connection inductance is mainly used to perform semiconductor chip mounting for high-speed communications. Current flip chip bonding methods use controlled collapse chip connection (C4) and Cu pillar bumps, but because of the difficulty involved in making connections with a pitch of less than 20 µm and the poor reliability of the intermetallic compound that forms in the bonding layer, alternative bonding technologies are required. Copper-copper bonding technology, which connects copper electrodes to each other directly, is attracting attention as a solder-free bonding technology.
In recent years, there have been numerous reports of mass production and development of the hybrid bonding method as a fine-pitch copper-copper bonding technique. The main problem with this method is that contaminant particles can cause bonding defects, leading to sophisticated particle control requirements. In chip on wafer (CoW) processes in particular, where bonding occurs after dicing, unprecedented particle countermeasures are required because of the numerous particles generated during dicing. Another problem with this method is that copper-copper diffusion bonding requires high temperatures of 350–400°C, which raises concerns about both warpage and reliability.
In this study, we have developed a polymer hybrid bonding process in which copper paste and a photosensitive adhesive are used to create a new copper-copper bond. The process involves formation of apertures in a photosensitive adhesive by photolithography, filling of the apertures using copper paste, planarization of the surface, and then bonding at 200–250°C. The copper-copper interface is sintered and the photosensitive adhesive is bonded using a resin curing system that enables chip bonding to be performed at relatively low temperatures. Use of the polymer adhesive provides a greater process margin against particle contamination than typical hybrid bonding methods that use inorganic materials such as SiO2. At present, 20-µm-pitch bonding is possible and we are working on realizing even narrower pitches in the future.
This presentation will introduce the unique features of the copper paste and the photosensitive adhesives and provide the results of polymer hybrid bonding using these materials to confirm the innovative nature of these bonding processes and materials.

 

The demands for radio frequency (RF) of up-coming 5G electronic applications are gradually rising, arising recently from the need of smaller and thinner package in internet of things (IoT) and electronics devices. 3D system in package (3D SiP) including double side molding and antenna in package (AiP) could meet the above requirements. Dual side surface mounting technology (SMT) and double side molding are performed in this study to achieve miniaturization of 3D SiP module. A cost-effective and alternative molding process is completed by vacuum printing encapsulation systems (VPES) instead of common transfer molding. In this study, there are two kinds of double side molding structures, conformal and compartment molding, are employed with EMI shielding. Both molding architectures adopted conductive material as a dam to ensure electrical connectivity of side wall and sputtering metal layer to acquire EMI shielding effectiveness. To verify the reliability response of the molding structure, pre-conditioning and thermal cycling test (TCT) are performed. A successful double side molding structure done by VPES with PCB warpage of 0.5 ~0.6 mm has been achieved in this work. Moreover, the dual side molding could reach the package requirements of 5G IoT module.

 

Based on the requirements of high-end IC packaging, the future of advanced IC packaging lies in the re-distribution layer structure for wafer-level package (WLP) or panel-level package (PLP). In order to enhance computing performance, it is necessary to package multiple chips (multi-chip/multi-die) into a module, which requires connecting the communication signals between chips (chip connection/die connection) through high-density traces. Therefore, the chip-first process is a preferable method due to the demands of high-density traces.
However, the chip pick-and-place and molding processes often affect the stability of IC spacing, resulting in a phenomenon known as die shift. This die shift can lead to the loss of communication signals between chips or failure. To overcome this challenge, it is necessary to apply dynamic die shift correction during lithography step. In this research, we have successfully demonstrated such feasibility in our test vehicle by applying a robust Digital Dynamic Connection (DDC™) technology, based on a high-resolution maskless Digital Lithography Tool (DLT). The technology has been verified to provide patterning compensation for the RDLs in the chip-first IC packaging structure. The results indicate that the maximum displacement of the chip can reach a horizontal displacement (XY) of 50 μm and an angular displacement (θ) of 0.3° with high throughput (>30 panel per hour, PPH in high-volume manufacturing mode for 2μm resolution) in 4 chips packaging structure. There are 3 RDLs in this test vehicle stacking with two different dielectrics including PSPI and Photo-Sensitive Build up Film (PSBF). In this case, the resolution of PSPI and PSBF are up to 5μm and 7μm respectively by using DLT. Besides, the Line width of Cu trace is around 5μm, and then the adhesion between PSPI and PSBF is 5B. Those results show the great potential of high resolution multi-RDLs for chip-first FOPLP application. Moreover, besides its applicability to high-end wafer-level and panel-level packaging in the future, this technology may also find opportunities for implementation in next-generation display devices.

 

Traditionally, wafer dicing is carried out by the blade sawing, which is a high-efficiency and cost-effective production process. In case fragile materials or multiple layers stacked on the dicing lanes, laser grooving will be performed to remove the surficial layers firstly and then the blade saw will cut through the remaining thickness of the wafer to prevent defects induced. This hybrid laser grooving & blade sawing have been employed for decades successfully.
But when the chip size is getting smaller and thinner as well as electrical layers becoming thicker, the traditional dicing process faces challenges, including insufficient die strength, early-failure happened after IC packaging and low-productivity of small chips, …etc.
Plasma dicing has the inherent features of removing defects and dicing all lanes simultaneously, which can overcome the aforementioned challenges of low-quality and low-productivity. Accordingly, this study proposes a process of hybrid laser grooving and plasma etching, which can be employed for fabrications of WLCSP/WLP or discrete components. Compared with the traditional dicing process, the average die-strength is raised up to 1.6-folds at least for WLCSP/WLP and the productivity is raised up to 10-folds for small chips(<0.5x0.5mm2) with backside metal layers deposited. With these advantages, the dicing requirements for the advanced IC packaging can be fulfilled.

 

In view of low processing temperature and short processing time, ultrasonic bonding was developed in this study to join Ni/Pd/Au pre-plated finish (PPF) lead frames and Cu films together. Optimization was also systematically accomplished through the design of PPF (metal coating thickness and roughness), and plasma source gas, as well as bonding process parameters. Experimental results show that thin Pd layer/thin Au layer was the best combination to bond with Cu. Plasma pretreatments effectively increased the surface energy especially those beaing H2. Among the adopted plasma gases (N2, N2-H2, Ar, and Ar-5%H2), N2-H2 was the one which can reach the topmost joint strength. Derived from all the results, it can be concluded that an increase in surface energy and surface roughness, as well as a lower surface hardness, contribute to better bonding performance.

 

The presentation will discuss on the improvement actions being implemented to address the challenges encountered on enabling PressuredSintering Die Attach Technology from Characterization, Development, and Qualification stage. Aims to be the reference of all incoming new Power Modules products in Panel/DBC form with same DA Technology.

Bio:
Senior Package Development Engineer at onsemi Malaysia. 6 years’ experience in the development of Power Integrated Module (PIM) technology. Innovating PIM in various market needs involving industrial modules, inverter, and EV for automotive applications.

 

Parasitic inductance and temperature are critical factors in power module design, impacting switching stability and system integrity. This study presents a novel double pulse test platform capable of assessing power module switching behavior under high current (>1000A) and low temperature (-40°C) conditions. The platform facilitates the evaluation of parasitic parameter effects on power module and DESAT protection designs in the gate driver board. Notably, our work demonstrates the occurrence of self-sustained oscillation effects during the turn-on transient of the low-side transistor, contrasting the traditional turn-off transient. Experimental results showcase the successful operation of the designed platform and gate driver board, enabling comprehensive switching assessments at 1100A and -40°C. This study provides valuable insights to designers, assisting in mitigating unintended phenomena during switching transients in practical systems.

 

Over the past years SiC power devices have received increasing attention due to their superior performance compared to traditional silicon-based devices. However, the defect density in SiC wafers remains high.
In this report we explore the role Raman spectroscopy can play to identify different types of defects in SiC wafers and devices. We focus on two prominent bands: The peak 776 cm-1 is related to local residual stress and can be used to identify basal plane dislocations (BPD). The peak at 970 cm-1 is sensitive to the doping concentration and can be used to judge electrical uniformity of the SiC wafer without contact.

 

Thanks to the popularity of AI chatbots, the demand for high computational power chip is unprecedentedly strong in order to accelerate the development of the generative AI models required for this kind of training application. Therefore, the performance of AI computing chips is getting higher and higher, and two major characteristics could be observed from this trend. One is the package size keeps increasing, the other one is that the power consumption is larger than ever before.
One of the common issues with huge package is the warpage concern. To make sure the warpage of huge package can be as good as possible, lid-type package would be preferred. However, for large-size packages, there is another risk of using metal lid as a heat spreader, which is the high probability of thermal interface material (TIM) delamination caused by the out-of-sync warping of the substrate and lid. Therefore, for high power chip, in the pursuit of lower package thermal resistance, it’s often to choose ring-type as it removed the lid and TIM, but the tradeoff would worse warpage, which would impact yield of system level assembly. In this study, we proposed a package with embedded liquid cooling channels to fulfill the requirement for both warpage and thermal performance. With the embedded liquid channels, the heat generated by chip could be dissipated efficiently and superior thermal performance was expected. In order to understand and verify the thermal and warpage performance of this innovative package, the detailed package model was established to investigate its thermal and warpage behaviors. Through simulation and modeling, a series of parametric study on flow rate and liquid channel pattern had been executed. It was found that we were able to achieve up to 1000W cooling capability with a package size of 62.5x62.5 mm2 and in the meantime, the max warpage value was well below 10 mils which was qualified for the standard criteria of surface-mount reflow process for BGA packages. Besides conducting package simulation, the validity of the package mechanical model was also verified by shadow moire measurement. The results showed that the difference between the model and the warpage measurement on different heat spreaders is lower than 5%.
By adopting the proposed package with embedded liquid channels, system manufacturers can be free from the trouble caused during the assembly process of installing advanced heat-sink or the cold plate of liquid cooling. Moreover, this innovative package would be especially suitable for AI server as the trend of liquid cooling was drastically prompted by AI data center in recent years.

 

The emergence of electric vehicles has promoted the need for power modules. Having a small volume and reliable power module is wanted in these applications because the smaller and lighter products are more commercially competitive. Along with this need, the packing methods for power modules are transforming. Unlike the previous silicone gel encapsulation, PCB embedded packaging and Fan-Out Panel-Level Packaging eliminate the outer case and form an integrated product, saving much volume. These packaging methods contain many copper/epoxy bonding interfaces, which are easy to fail. To widely apply these packaging methods, the reliability of the copper/epoxy bonding has to be confirmed.
This paper investigated the bonding reliability between the encapsulated epoxy and a copper substrate under 85°C/85% RH Accelerated Life Test (85/85 test). A C1020 copper substrate and a two-part liquid epoxy (bisphenol A type epoxy resin and an anhydride harder, ratio 100/80) were used. It consists of 71.5 wt% silica filler to adjust its thermal expansion coefficient. Then, we fabricated the package by compression molding. The bonding strength between substrates and encapsulation epoxy was measured before and after the 85/85 test. Unlike many previous studies, the bonding strength doubled after 240 h 85/85 test and kept even after 1000 h. The fracture surface of the copper side and epoxy side was characterized by various methods.
We characterized the fracture surface of the copper side with SEM. It shows that the copper surface was oxidized gradually with the increased time in the 85/85 test. The epoxy suffers hydrolysis during the 85/85 test, which reduces the strength of the epoxy chain. The oxidation of the copper surface and the hydrolysis of epoxy breaks the copper/epoxy bonding formed during the encapsulation. Also, we observed that many gaps were produced between silica fillers and the epoxy body, indicating the bonding between the epoxy and silica filler was weakened by the water absorption. These factors should reduce the bonding strength.
However, why did the bonding strength increase after the 85/85 test? We found that besides the factors for bonding strength reduction, there is also a factor for bonding strength increase. SEM images show that the oxidized copper formed crystal structures on the copper surface, and these crystal structures can bond with the silica inside the epoxy, which produces a mechanical interlocking effect. On the fracture surface many silica fillers stripped out of the epoxy body were found on the fracture surface of the copper side. We supposed this should be the reason for the bonding strength increase after the 85/85 test.
Our study revealed a new phenomenon for the copper/epoxy bond under the 85/85 test. Since recent epoxy contains a large percentage of silica fillers, this phenomenon should become highly possible for other epoxies. This knowledge will contribute to future power module design and materials development.

 

This study attempts to develop a 1700 V/100 A 9.6 kW SiC power MOSFET module (briefly termed ITRI SiC power module, as shown in Fig. 1(a)) for use in onboard charge (OBC) of electrical vehicle (EV), and besides, predict the power cycling reliability of the solder joint under water cooling. To achieve this goal, a power cycling characterization framework is proposed. The proposed power cycling characterization framework combines accelerated power cycling (APC) experiments and three-dimensional (3D) APC numerical model that integrates a computational fluid dynamics (CFD) thermal analysis for calculating the transient temperature distribution and a thermal-mechanical finite element analysis (FEA) for determining equivalent inelastic strain increments. In addition, a physics of failure (PoF)-based lifetime prediction model is constructed through conducting a series of APC experiments on a commercial 1200 V/25 A SiC power MOSFET module (briefly termed commercial SiC power module) (see Fig. 1(b)) under various junction temperature swings (∆Tj), the coefficients of which are derived by fitting the experimental lifetime data to the simulated equivalent inelastic strain increments (see Fig. 2). The constructed PoF-based lifetime prediction model together with the proposed APC numerical model is further applied to explore the solder joint lifetime of the ITRI SiC power module. The effectiveness of the proposed power cycling characterization framework is further confirmed through comparing the APC numerical lifetime result with the APC experimental data (see Table 1). At last, parametric study of the ITRI SiC power module under an actual application condition is performed to assess the influence of several key parameters on its solder joint reliability (see Fig. 3).

 

Due to the vigorous development in energy and automotive electronics industries, the demand for high-power devices is increasing. However, there are several challenges in power device packaging, including heat dissipation, mechanical stress and reliability. As a result, the selection of a suitable die attach material has become one of the issues that need to be addressed in order to ensure a well bonding. The die attach material selection involves several aspects, including effective thermal management, coefficient of thermal expansion difference between materials and maintaining good reliability in an extended period of time at high temperatures.

Nanoporous (NP) materials possess high specific area and high porosity, which aid in bonding and helping to absorb internal stress within the material, respectively. These characteristics contribute to improving the bonding quality and increasing reliability. Moreover, NP copper can prevent the diffusion of bulk atoms into other materials, which is often observed in the silver paste. Hence, we chose copper, which is known for its well electrical and thermal conductivity, as the NP material in this study. A co-electrodeposition process is used to electroplate copper-zinc films onto copper substrates of different roughness. Subsequently, we dealloyed the zinc atoms, leaving behind a NP
copper structure with nearly no residual zinc atoms.

Previous studies have shown that nanotwinned copper (NT-Cu) exhibits good conductivity, electromigration resistance, and higher mechanical strength compared to regular copper. When NT-Cu is used as a bonding material, good bonding quality can be achieved at a much lower temperature. At the same time, the bonding interface remains certain mechanical properties and reliability. Accordingly, the as-fabricated NP copper would be bonded to different silicon substrates in this study to observe the effect on bonding. Silicon substrates with regular copper, highly (111)-oriented Cu seed, and highly (111)-oriented NT-Cu structures would be tested in the study. The bonded samples will undergo tensile tests and temperature cycling tests to assess their mechanical strength and reliability. Finally, we would electroplate NP-Cu on DBC substrates and bonded it with SiC to recreate the structure of actual high-power devices.

Based on the results of different bonding structures, we can deduce that the presence of an NP copper layer brings certain benefit on the bonding quality, and the roughness of the NP copper side directly affects the bonding condition. Furthermore, the presence of (111)-oriented NT-Cu effectively improves the reliability and overall mechanical strength. Through the structure of nanoscale pores and NT grains, we provide a promising die attach material that is applicable to high-power components operating in demanding environments.