Oral Sessions


Plenary I - Kamheng Lee,Senior Director,TSMC

Oct. 26, 2022 10:20 AM - 11:10 AM

Room: R504abc
Session chair: Chih-I Wu, VP, ITRI

Advancement in the 3DFabric Technology and Manufacturing

Plenary speaker

Kam Heng Lee,Senior Director, Deputy Head of APTS, TSMC

As silicon technology scaling continues, heterogeneous integration of silicon chiplets gains increasing significance to not only enhance yield, but also to increase design flexibility, reusability, and overall performance. The speech will touch on the TSMC’s efforts in the development of 3DFabric advanced packaging technology, covering 2D, 2.5D and 3D integration to deliver industry-leading performance. It will also touch on the transformation of backend manufacturing to adopt advanced automation to deliver a robust manufacturing process for advanced packaging.

Kam is currently the Deputy Head of TSMC Advanced Packaging Technology and Service. He joined TSMC earlier this year in March 2022 from Intel, where he served for 27 years in various roles in technology development, product development and high-volume manufacturing. Previously, he held the role as the Vice President and General Manager in Intel’s product engineering development group. At TSMC, Kam is actively working with his colleagues to advance the TSMC advanced packaging and testing technologies to serve its foundry customers.


Plenary II- ST Liew ,President ,Qualcomm Taiwan

Oct. 26, 2022 11:10 AM - 12:00 PM

Room: R504abc
Session chair: K. N. Chiang, Chair Professor, NTHU

Advancing 5G to power the Connected Intelligent Edge

Plenary speaker

ST Liew, VP & President,Taiwan & SEA, Qualcomm

5G is now mainstream and poised to connect billions of smart devices to the cloud. Building on our broad technology portfolio, Qualcomm is a leader in the advancement of 5G to power the connected intelligent edge. We’re at the intersection of key trends to accelerate digital transformation.

The growth of the edge is driving demand for our technology and creating new opportunities for innovation for the ecosystem across industries. With continued expansion of 5G mmWave and the evolution toward 5G advanced, we are moving toward a world where everyone and everything can be intelligently connected.

ST Liew is a Vice President of Qualcomm Technologies, Inc. and the President of Qualcomm Taiwan and South East Asia, Australia, New Zealand. ST was born in Malaysia and was educated in Malaysia, Singapore and the UK. His permanent home is Singapore.
In this role, ST is responsible for leading all business and operational functions for Qualcomm in the region. Prior to this role, ST served as the Vice President and President of Qualcomm Taiwan.
ST has more than 30 years of experience leading businesses and R&D in the telecommunication industry. Most recently ST was the President of Acer’s new Business Group SPBG that focused on R&D and Sales of non PC lines of product for the global market while living in Switzerland and later in Taiwan.
Before joining Acer, ST was in Motorola for over 18 years leading Regional R&D Teams and later in Product planning, business Teams across the world in products ranging from Mobile radios, Pagers, Data terminals to Cellular phones. ST has lived in China, Korea, USA and India during his tenure.
Liew received his MBA from the National University of Singapore, and holds a BSc. in Electrical and Electronic Engineering from the University of Leeds, UK.


S1: Packaging Innovations by SPIL

Oct. 26, 2022 13:10 PM - 15:10 PM

Room: R504a
Session chair: Yu-Po Wang,SPIL/ Kuoming Chen,UMC

Investigation of Moisture-Induced Warpage of Chip-on-Wafer in 2.5D IC Package
發表編號:S1-1時間:13:10 - 13:40

Invited Speaker

Inderjit Singh, Sr. Director,AMD

2.5D multi-chip packaging technology places multiple SoC dies and chiplets on a silicon interposer wafer so that better interconnect density and performance can be achieved. Individual chips are bonded through micro-bumps on a silicon interposer forming a chip-on-wafer (CoW) module. Excessive moisture-induced warpage of CoW die could lead to C4 bump failure in on-substrate assembly process. The risk is even higher in a case where a CoW module has stacked dies like HBM or SoIC, which are built with several kinds of polymer materials, on top of the silicon interposer. A two-step finite element modeling was performed: 1) moisture diffusion within polymer materials in a CoW module was simulated; 2) then hygro-thermomechanical simulation was performed to predict the warpage during reflow. Absorption / desorption test and CHS measurement were performed to characterize the moisture properties of the polymetric materials in a chip-on-wafer module. Different HBM structures, material overflow of the polymer which the stacked dies were built with, and storage humidity condition were simulated and discussed.

Advanced Package Platform "VIPACK" - FOSiP
發表編號:S1-2時間:13:40 - 14:10

Invited Speaker

Jeff Kuo, Corporate R&D / Wafer Level SiP, ASE

- Package Innovation Driven by Market
- Roadmap of FOSiP
- FOSiP Technology Building Blocks
- Next Innovation of Package Portfolio
- Summary

Development of Hybrid Bonding Technology, Innovative Applications and Platform for 3D IC
發表編號:S1-3時間:14:10 - 14:40

Invited Speaker

Kuan-Neng Chen, Chair Professor, National Yang Ming Chiao Tung University(NYCU)

1. Introduction
2. Hybrid Bonding Technology
3. Innovative Applications based on 3D Stacking Technology
4. Innovative Monolithic 3D IC
5. Conclusions

Challenges and solutions for IC substrates
發表編號:S1-4時間:14:40 - 15:10

Invited Speaker

Matsumoto Masaaki, General Manager of Semiconductor Materials R&D center, Panasonic

End-use applications ultimately dictate the construction and the properties requirements for IC substrates. Panasonic Electronic Materials has a portfolio of innovative and high reliability substrate materials, including copper-clad laminates and prepregs to meet the latest industry challenges. At this session, we will review our materials, technology, and development direction.


S2:High Speed PCB for Edge Computing Applications by Atotech

Oct. 26, 2022 13:10 PM - 15:10 PM

Room: R504b
Session chair: Eddy Chen,Atotech

Impact of increasing data speeds and the influence to the PCB requirements.
發表編號:S2-1時間:13:10 - 13:40

Invited Speaker

Scott Hinaga, Technical engineer, Cisco

As channel speeds increase from 56 to 112GBps and beyond, new PCB materials and structures are required which pose challenges for PCB shops and CCL makers alike. This presentation will touch on signal integrity drivers at the bare board and laminate material levels which will be critical in developing routers and switches at 800G and above.

A Key aspect of Edge Computing, the 3D chips impact on PCB’s & Interposers
發表編號:S2-2時間:13:40 - 14:10

Invited Speaker

Joe Dickson, SR VP Product Operations & Innovations, Wus

A Brief Overview of Why???
• Examples of strategies for Interposers
• Wus new manufacturing ideas for new market
• Chip technologies are moving off the baseboard to Interposer type PCB’s and substrate SOP’s
• Design examples of next generation PCB/Interposer processes that will enable this technology

Challenges and manufacturing solution for high-speed networking PCBs
發表編號:S2-3時間:14:10 - 14:40

Invited Speaker

Patrick Brooks, Global Product Director- Surface Treatment Technology(STT), Atotech

The new generation of telecommunication network called 5 G has been actively entering the market and expanding in rapid speed. This trend has driven the electrical frequency that used in electronic devices continues to elevate. Thus, reshaped the manufacturing of modern PCB moving toward extraordinary high performance bonding process which required ultra-low loss of signal integrity, whilst meeting industrial standards for adhesion reliability. This presentation will cover challenges in bonding enhancement for high-speed networking PCB and its solution to manufacturing process. Moving toward advanced hybrid bonding system which the chemical interaction between dielectrics and conductor is also considered, rather than solely rely on the mechanical anchoring of rough surface.

Advanced PCB Lamination Material Development for High-Speed Networking Application
發表編號:S2-4時間:14:40 - 15:10

Invited Speaker

Jim Kenny, Business Development Manager, Panasonic

Information technology is dramatically improved these days. Ultra-highspeed application such as fifth-generation mobile communication system(5G) and wireless communication such as GPS and Bluetooth is getting more popular. In near the future, plenty of data traffic will be covered by them. In addition, we expect 6G and satellite communication will be developed and global standards to be set in near the future. We can expect Internet of things (IoT) which all of devices are connected each other is coming soon. In the future, Internet of Everything (IoE) will also come to the world. At that time, the number of device and traffic speed will dramatically increase.
The Printed Circuit Board (PCB) is required to have high speed signal, be high-density capable and support high-layer counts. In addition, PCB is required to be environmentally friendly.
We introduce our approaches to achieve electronic properties required and to satisfy future application demand.



Oct. 26, 2022 13:10 PM - 15:10 PM

Room: R504c
Session chair: Takeyasu SAITO,Osaka Prefecture University/ Lewis Huang, Senju

Energy Harvesting by Daily Humidity Cycle
發表編號:S3-1時間:13:10 - 13:34

Invited Speaker

Yusuke Komazaki, Researcher, National Institute of Advanced Industrial Science and Technology (AIST)

To power enormous numbers of IoT devices, energy harvesting has great importance. In this presentation, we will present our hygroelectric cell (HEC) technology, which enables ubiquitous energy harvesting by humidity change, based on the combination of concentration cell and deliquescent solution.

Plasma technique for advanced package product
發表編號:S3-2時間:13:34 - 13:58

Invited Speaker

Daisuke Hironiwa, Plasma technique for advanced package product, ULVAC

As electronics devices becomes more high performance, energy efficient, and diversified, more complex and finer packaging structures and more diversified materials are being actively studied.
Against this background, plasma technology is being actively employed in the manufacturing process of high-density packaging products.
In this presentation, I will introduce various plasma processing technology for advanced package product.

Design of Strong Interfaces by Use of Materials Informatics Based on Molecular Simulation
發表編號:S3-3時間:13:58 - 14:22

Invited Speaker

Tomio Iwasaki , Dr.,Hitachi, Ltd.

In order to introduce environmentally compatible and biocompatible materials into future devices, it is necessary to ensure the adhesion between such materials and surrounding materials. Therefore, we have developed a materials informatics design technology that improves the adhesion strength between environmentally friendly and biocompatible materials and metals, ceramics, and resins. In this technology, the material composition that enhances the peeling energy is derived by analyzing the peeling energy data by the molecular simulation by the orthogonal array and the response surface methodology. We will introduce an example of designing ceramics and metals with excellent adhesion strength to DNA materials, which are being studied as environmentally compatible and biocompatible materials, using this technology. In addition, we will introduce an example of designing a peptide material with strong adhesion strength to resin for devices.

Investigation of bonding strength improvement mechanism for sintering Ag by Zn / Ag plating
發表編號:S3-4時間:14:22 - 14:46

Invited Speaker

Ryohei Ueyama

In recent years, effective use of electric energy is an important issue from the viewpoint of global environmental protection. Therefore, power modules, which are key parts of power electronics technology, are strongly required to be highly efficient and highly reliable. These power modules are now required to have a high level of reliability under severe temperature conditions, mainly in the field of automotive equipment. In addition, due to the European RoHS regulations, practical application of sintered Ag bonding materials is required as a substitute for conventional Pb-based solder. Although this sintered Ag bonding material has higher thermal conductivity than solder, it requires a high-pressure process to increase its strength, and there is a risk of damaging the device. Therefore, Zn, which has a large solid solubility limit in Ag, is diffused to improve the strength of sintered Ag joints at low-pressure process.

Recent Development of Fine Pattern Capable RDL Materials
發表編號:S3-5時間:14:46 - 15:10

Invited Speaker

MasaoTomikawa, Director, Toray Industries Inc.

Fine pattern capable positive and negative tone PSPIs were developed. The materials shows good electro-insulation reliability under Bias HAST condition.


S4:Advanced Packaging Ⅰ

Oct. 26, 2022 13:10 PM - 15:10 PM

Room: R503
Session chair: Chih Hang Tung, Deputy Director, TSMC/Tz-Cheng Chiu,Professor, NCKU

Additive Manufacturing Technologies for Custom-made Electronic Packaging
發表編號:S4-1時間:13:10 - 13:40

Invited Speaker

Ricky Shi-Wei Lee, Chair Professor, HKUST

Photolithography has been the main stream technology for microelectronics fabrication for decades. Although it offers high throughput for mass production, sophisticated facilities such as lithography systems, photo masks, and etching benches are required. For prototyping and small/medium production, photolithography may not be the ideal choice in terms of cost and lead time. With the advancement of printing technologies in recent years, additive manufacturing (AM) has become a competitive option for prototyping and small/medium production. This presentation will introduce the development of AM and its advantages for microelectronics fabrication. Examples of applications in chip level re-distribution layer and bumping will be given. Potential opportunities for future printed electronics will be discussed.

A Laser Release Temporary Bonding Tape for Hybrid Bonding Having High Thermal Resistance and Excellent Thickness Uniformity
發表編號:S4-2時間:13:40 - 13:55

Izumi Daido, Ryoichi Watanabe, Toshio Takahashi, Masateru Fukuoka

There has been strong demand to increase I/O bandwidth for higher performance of semiconductor packages. Hybrid bonding is a very important interconnect technology to increase the I/O bandwidth as a next generation HPC technology and 3D interconnection. Hybrid bonding process doesn’t have bumps on the interconnect interface, so it can fabricate very fine pitch interconnects such as under 5 micrometers, also it has very low interconnect resistance because of Cu-Cu direct bonding.
However, hybrid bonding needs very high temperature, so a lot of studies have been done by many researchers but it still needs 250-300 degC or more for Cu diffusion to perform robust joint. Therefore, not only process equipments but also process materials are required to have thermal resistance during the bonding process.
In response to such requests, a Temporary Bonding De-Bonding (TBDB) tape for hybrid bonding having superior thermal resistance is introduced in this paper. TBDB tape can support a wafer through an overall process. In TBDB process for hybrid bonding, a carrier substrate with a TBDB tape is bonded to a wafer. The backside of the laminated wafer is grinded so that the thickness of the wafer reaches a target value. Then, chemical treatments (CVD, CMP) and thermal treatments (hybrid bonding) are performed. Finally, the completed wafer is removed from TBDB tape and the carrier. The performance requirements of TBDB tape for hybrid bonding are mainly high thermal resistance, easy removal from a wafer and thickness uniformity (Total thickness variation, TTV).
TBDB tape with high thermal resistance for hybrid bonding can support a wafer on the carrier substrate without delamination at the high temperature. However, conventional tapes are delaminated during thermal process. To improve thermal resistance, the adhesive in this TBDB tape is composed of a resin having higher thermal resistance than conventional resins. Generally, thermal resistant resins are so rigid that it strongly adheres. Such characteristic might make it difficult to remove a tape from a wafer after the thermal process. However, this TBDB tape has both thermal resistance and flexibility because the adhesive is composed of soft and hard segments. Therefore, it can be removed easily.
For further easy removal of TBDB tape from a wafer, the adhesion strength of the tape is controlled by UV crosslinking of adhesive and addition of low polarity components. The adhesion strength is decreased by UV crosslinking and localization of low polarity components on the tape surfaces. These effects make it possible to suppress the increase of the adhesion strength during thermal process and be easily peeled off from the wafer.
TTV is important for high reliability of hybrid bonding. Flatness of grinded die or wafer surface is key for reliable D2W (Die to Wafer) interconnect. The flatness of each dies has dependency by not only grinding tool but TBDB thickness uniformity. This TBDB tape has superior thickness uniformity comparing with conventional TBDB tape.
This TBDB tape has high thermal resistance that is applicable to hybrid bonding process. It enables many thermal processes to fabricate high performance semiconductor packages.

Nano-Artifact Metrics Chip Mounting Technology for Edge AI Device Security
發表編號:S4-3時間:13:55 - 14:10

Hitoshi Masago

We studied the effect of surface treatment on the bonding strength for establishing the technology of the quad flat package (QFP)/Quartz glass bonding method. This bonding technique is neccessary to prevent physical attacks such as counterfeiting and modification of edge AI devices with Nano-artifact Metrics (NAM) chips. We investigated the relationship between surface roughness and tensile strength by applying surface treatments for QFP such as VUV and Ar/O2 plasma.

Effects of Shielding Materials on EMI Performance for 5G Wi-Fi Applications
發表編號:S4-4時間:14:10 - 14:25

Shen-Yu Yang

Electronic communication devices used in many fields such as the internet, military, electronic industry, medical care, and electronic payment are growing rapidly. However, these demands lead to a new type of pollution called noise or radio frequency interference (RFI) or electromagnetic interference (EMI), which may interfere with equipment performance and cause equipment shutdown. As a result, there is a great need for electromagnetic waves shielding and other components in the module would not be disturbed by outer electromagnetic waves. The influence factors of EMI shielding include forming process, coating thickness and material. In this study, silver and copper are the metals adopted in EMI shielding due to their excellent properties of electrical conductivity and magnetic permeability. We focus on the effects of coating thickness and different processes including sputter, screen printing and spray. 2.4 GHz/5 GHz Wi-Fi module is utilized for EMI shielding test. The results of EMI block are measured by Keysight N9010B equipment to check electromagnetic waves shielding capability by dBm value at 4.8GHz (2nd harmonic), 7.2 GHz (3rd harmonic) and 6.43 GHz (noise). Besides measurement by using functional products, radiation simulation is used to simulate antenna efficiency under designed coating thickness of EMI shielding layer. The results of simulation and experiments show that coating thickness is the key factor to affect EMI shielding effectiveness. Moreover, processes of screen printing and spray are applicable and would be cost-effective alternates compared to sputtering.

Plasma-Activated Cu-Cu and Al-Al Direct Bonding for Electronics Packaging
發表編號:S4-5時間:14:25 - 14:40

Liangxing Hu, Simon Chun Kiat Goh, Yu Dian Lim, Peng Zhao, Michael Joo Zhong Lim, Weiyang Miao, Van Quy Dinh, and Chuan Seng Tan

In this paper, we report Ar/N2 plasma-activated Cu-Cu/Al-Al direct bonding conducted at room temperature in ambient environment. Surface characterizations are performed on the Cu and Al surfaces before and after plasma exposure, revealing that the plasma-activated surfaces remain in an “activated” state for up to 6 hours compared to the as-deposited Cu and Al surfaces. Subsequently, the plasma-activated dies are bonded. The bonded dies are examined for the bonding quality. The results show that a high-quality bonding is achieved. This reported bonding technology would be suitable for high-throughput CMOS-MEMS 3D integration and electronics packaging.

Metal-metal bonding is a promising semiconductor bonding technique, which has been widely developed to produce vertically electrical connections, provide mechanical support, and form hermetically sealed encapsulation [1]. Metal diffusion (thermo-compression) bonding, eutectic alloy bonding, and transient liquid phase diffusion bonding (TLPDB) are highly used in 3D integrated circuits (ICs) packaging [2]. The latter two bonding methods, which are based on solder materials, may be faced with inter-metallic compound (IMC) issue. On the contrary, metal diffusion bonding, such as Cu-Cu/Al-Al, is absent of IMC issue. However, Cu and Al are prone to rapid oxidation. To tackle this issue, Cu and Al surface treatments such as specialized chemical mechanical polishing (CMP), chemical treatment, surface assembled monolayer (SAM), and plasma activation, have been reported [3-7]. Among these methods, plasma activation is favorable as the process does not leave behind any residue [8-17]. In this paper, we report the plasma-activated Cu-Cu/Al-Al direct bonding conducted at room temperature in ambient environment.

Si wafers are patterned and deposited with 10 nm thickness of Ti as adhesion layer, followed with 100 or 200 nm thickness of Cu or Al via electron-beam evaporation, respectively. Afterwards, the wafers are diced into small dies with dimensions of 2 mm × 2 mm and 10 mm × 10 mm. Thereafter, the Cu or Al surface of the diced dies is exposed to Ar/N2 plasma. During the plasma process, Ar plasma are firstly applied to remove surface contaminants and native oxides, N2 plasma are subsequently applied on the Cu or Al surface to form an ultra-thin layer of nitride for passivating the Cu or Al surface and achieving low temperature bonding. Finally, the “activated” dies are pre-bonded in ambient environment in clean room (18ºC and 40% humidity) and are annealed at 300ºC to enhance the bonding strength.

The evolution of water contact angle (θ) with varying time for both the as-deposited and the Ar/N2 plasma-activated Cu or Al surface is performed. The results for Al are shown in Fig. 1. Compared to that of the as-deposited surface (~60º), the water contact angle of the Ar/N2 plasma-activated surface (~10º) is lower initially, revealing that the activated surface is more hydrophilic. Subsequently, the water contact angle of the Ar/N2 plasma-activated surface increases gradually until it is comparable to that of the as-deposited surface. The results show the metastability and degradation of nitride layer, revealing that the nitride layer remains in an “activated” state for up to 6 hours post plasma exposure. In addition, the bonded dies are assessed for the bonding quality and the bonding interfaces are shown in Fig. 2. The results show that a high-quality bonding is achieved.

In this paper, Ar/N2 plasma-activated Cu-Cu/Al-Al direct bonding conducted at room temperature in ambient environment is reported. Surface analysis reveals that the plasma induced metastable nitride surface is more hydrophilic than the as-deposited surface and the plasma-activated surface remains in an “activated” state for a duration of 6 hours post plasma exposure. In addition, the bonding interfaces of the bonded dies are examined, the results show that the dies are well bonded. This bonding technology would be suitable for high-throughput CMOS-MEMS 3D integration and electronics packaging.

Authors acknowledge funding support from A*STAR (A18A4b0055) under the “Nanosystems at the Edge” program.

Low Thermal Budget Cu/SiO2 Hybrid Bonding Using Highly <111>-oriented Nanotwinned Cu with Low Contact Resistivity and High Bonding Strength
發表編號:S4-6時間:14:40 - 14:55

Jia-Juen Ong

Fine-pitch hybrid bonding with dielectric layer (PECVD SiO2) and metal layer (nanotwinned Cu (nt-Cu)) was fabricated in both die and wafer level bonding process. The pitch and diameter of the nt-Cu microbumps were 20 m and 8 m, respectively. They were electrodeposited on a Tantalum (Ta) adhesion layer. Highly <111>-oriented nt-Cu was successfully electrodeposited in the trench which was etched using a damascene process. The dishing between the Cu and SiO2 layer could be precisely controlled within 3 nm. Prior to the bonding, the top and bottom dies were treated by a 20-W Ar plasma for 120 s to remove the native oxide layer on the Cu joints and to modify the SiO2 surface. Thus, their hydrophilicity could be increased. The relationship between surface contact angle and plasma power was also investigated. We found that the 20-W Ar-plasma was the optimized parameter to effectively remove the oxide layer and obtain the lowest hydrophilicity of the nt-Cu and SiO2.
After the pre-bonding at room temperature and ambient pressure by dripping DI water droplets at the bonding interface, thermal compression bonding (TCB) was conducted at 200 C for 1 h in vacuum with a compressive pressure of 3 MPa. Post-bonding annealing without external pressure was then carried out. The electrical properties of Kelvin structure and daisy chains with 2500 and 50 bumps were also studied using a 4-point probe method. Results showed that a contact resistivity of 10-9 -cm2 was obtained. This is the lowest value found in literature as bonded at a temperature below 300 C. Such a low contact resistivity achieved was mainly due to the lowest oxidation rate and highest surface diffusivity of the <111>-oriented Cu, as well as the twist-type grain boundaries at the bonding interfaces Die shear tests with a shear speed of 100 m/s and a shear height of 200 m were subsequently executed. Results showed that the bonding strength is exceed 30 MPa, which was greater compared to that in some recent studies. Additionally, three-dimensional (3D) X-ray was then used to characterize the bonding quality of the electrical structure. To observe the microstructure and bonding quality of the Cu joints, cross-sectional analysis was conducted using focused ion beam (FIB) and scanning electron microscope (SEM). High resolution transmission electron microscope (HR-TEM) was also employed to examine lattice arrangement of the bonding interface.

Large area Cu-to-Cu Bonding for Heat Pipe Applications
發表編號:S4-7時間:14:55 - 15:10

Guan-You Shen

As the performance requirement continues to increase, the power in the devices also continues to increase, resulting heat dissipation is a big issue for high performance devices, such as high performance computing devices. In this study, large area Cu-to-Cu bonding can be achieved by thermo-compression process at 250°C with high bonding strength exceed 30 MPa. Percentage of (111) orientation at the surface can be increased to 49% on regular Cu foils for electroplated nanotwinned Cu (nt-Cu) films. Due to the high surface diffusivity of (111) surfaces, high bonding strength of 30 MPa can be achieved at 250°C for 30 min for the bonded films with 4.5 cm2 bonding area. We provided a simple and efficient highly (111) diffusion bonding process for large area bonding especially for heat pipes, which needs high thermal conductivity materials to dissipate the heat away.


S5: High Density Fan-out Packaging Solution for Chiplets by ASE

Oct. 26, 2022 15:40 PM - 17:40 PM

Room: R504a
Session chair: Chen-Chao Wang,ASE

Development Trend of Advanced Packaging for HPC
發表編號:S5-1時間:15:40 - 16:10

Invited Speaker

Mu Hsuan Chan, Department manager, SPIL

Disaggregate & integrate to Satisfy Power, Performance, Area and Cost by Chiplet Technology

Low temperature direct bonding in atmosphere using highly (111)-oriented nanotwinned Ag thin films
發表編號:S5-2時間:16:10 - 16:40

Invited Speaker

Fan-Yi Ouyang, Professor, NTHU

In the development of 3D IC technology, metal-to-metal direct bonding has been regarded as an important technique to enable heterogeneous integration. In this talk, we proposed to adopt highly (111) oriented nanotwinned Ag films as bonding materials due to their good electrical and mechanical properties. The twin spacing and hardness of Ag films is around 9 nm and 1.9 GPa, respectively. The Ag-to-Ag direct bonding using highly (111) oriented nanotwinned Ag films and bumps can be achieved by thermo compression bonding process at 180–200 ℃ under air atmosphere within a short time. The bonding ratio could be higher than 90 %, and the bonding strength could reach over 100 MPa in the shear test. Furthermore, the nanotwinned structure still remained after bonding process, demonstrating good thermal stability of nanotwins. Meanwhile, the Ag-to-Ag bonding samples could provide good specific contact resistance. The corresponding bonding mechanism would be discussed in more details in this work.

Planning and Assembly Verification of Heterogeneous Packages
發表編號:S5-3時間:16:40 - 17:10

Invited Speaker

Rony Wang, Account Technology Manager, Siemens EDA

Heterogeneous Package is more complex than general package and design & verification is more challenged. We will discuss how to use planning, design, and verification tools to solve heterogeneous package issue and sign-off verification platform in the topic.

Thermal Solution for High Power FOCoS Package
發表編號:S5-4時間:17:10 - 17:40

Invited Speaker

HX Huang, Deputy Technical Manager, ASE

In recent years, integrated circuits (ICs) have exhibited the trends of high performance, small size, and heterogeneous integration. Heterogeneous integrations are commonly used today to extend Moore's law beyond the limitations. The FOCoS is the most popular semiconductor package structure which providing a promising cost-effective heterogeneous design for higher bandwidth, processor clock speeds and power densities applications.
Thus, developing the integrated thermal management from package level to system level is needed to ensure the performance and reliability of high power FOCoS ICs. In this presentation, several analysis of package to system level thermal solutions and prediction tools will be introduced for future high performance devices.


S6:Advanced Packaging for Data Center/ Server Applications by Atotech

Oct. 26, 2022 15:40 PM - 17:40 PM

Room: R504b
Session chair: Eddy Chen, Atotech

Future Packaging Trends and Drivers for Datacenter
發表編號:S6-1時間:15:40 - 16:10

Invited Speaker

E. Jan Vardaman, President and Founder, TechSearch

Trends in datacenter growth and packages used for CPUs in datacenter, includes a discussing of the package options used by different companies, future needs including power delivery and thermal dissipation, drivers for next generation packaging including co-packaged optics.

Advanced Packaging implications to Substrates
發表編號:S6-2時間:16:10 - 16:40

Invited Speaker

Dilan Seneviratne, Principal Engineer, Director DSP Area, Intel

Conventional thinking of Advanced Packaging centers around bump pitch and IO density scaling. However, with the aggressive demands driving the increased computational needs in data centers, more features need to be considered and developed. This talk will address what features and capabilities are needed on high density interconnect substrates to meet the Advanced Packaging needs.

Advanced Substrate Challenges for Heterogeneous Integration
發表編號:S6-3時間:16:40 - 17:10

Invited Speaker

YH Chen, Vice President, Unimicron

Heterogeneous integrations are driven by Moore’s Law, and advanced packaging plays a critical role for semiconductor supply chain. Unimicron covered most less than 7nm IC carrier and foresee the high-end substrates will be continuously shortage. Heterogeneous integration of high-end products existed from 2.5D planar interconnect (Si interposer, EMIB) to 3D die-to-die stacking (WoW, SoIC, Foveros).
Substrate technology is driven by extreme body size/high layer counts, heat dissipation, low loss material…etc.

IC substrate scaling to enable higher IO density - Challenges and solutions
發表編號:S6-4時間:17:10 - 17:40

Invited Speaker

Kuldip Johal, Global OEM Director New Technology Pathfinding, Atotech

Heterogenous integration continues to adopt many options such as Silicon interposer, different formats of embedded Silicon and high-density fan out. All these integration routes have the objective of increasing IO density. The challenge is that many of these options are costly, and in response the advanced packaging industry continues to look for lower cost options. The laminate-based IC substrate remains to be the most cost-effective solution, however, there are challenges to increase IO density with this approach. There are 2 options to increase IO: first, one can increase layer count, which is already challenging due to yield issues, and second; one can continue IC substrate scaling to finer pitch interconnects. The focus of this presentation is to review the key challenges and solutions associated with IC substrate scaling and their impact on the various processes.


S7: 3D Embedding

Oct. 26, 2022 15:40 PM - 17:40 PM

Room: R504c
Session chair: Weita Yang, Industrial Technology Research Insitute

Evaluation plateform of advaced semiconductor encapsulant materials
發表編號:S7-1時間:15:40 - 16:10

Invited Speaker

Chih-Hao Lin, Manager, Industrial Technology Research Insitute

Advanced semiconductor packaging is widely used in 5G, AI, high-performance computing and other fields. The packaging forms include high-density flip-chip packaging and fan-out wafer level packaging. As the number of I/Os of packaging modules increases significantly, and the pitch and gap are getting smaller and smaller, there is a great challenge for the properties of encapsulant materials. However, the evaluation of encapsulant materials are strongly needed application-side’s cooperation and the evaluation process is complicated and time-consuming, resulting in a long material development time. In response to the needs of developing advanced semiconductor encapsulant materials, a rapid evaluation platform is established, including material property evaluation, preparation of flip chip test vehicles with hundreds to thousands of I/Os, complete assembly process, reliability evaluation and failure analysis. Conducting rapid evaluation of advanced semiconductor encapsulant materials could understand the issues of the material that might be faced on test vehicles, quickly improve or optimize material properties to meet application requirements and strengthen the opportunity that new materials imported into semiconductor packaging application.

Embedded substrate using 4um fine pitch silicon interconnection IC
發表編號:S7-2時間:16:10 - 16:40

Invited Speaker

Hyunho Kim, Chairperson, Korea Packaging Integration Association

As the smartphone and tablet PC markets grow rapidly, high-performance, multifunctional, and high-speed signal transmission of devices are required, and at the same time, small form factor is essential. Semiconductor packages are driving high-tech as core components, and FCCSP and SiP are leading the trend of thin and small in the application processor, baseband, RF-FEM - Radio Frequency Front-end Module, GPU, and AI market. Thin substrates are being adopted to reduce the thickness of key packages according to the trend of lightness, thinness, and shortness, and especially in SiP, IC active chips and thin passive components tend to be packaged together, so technology to reduce the thickness of packages is a key trend in mobile devices.
In this paper, the limit in the existing manufacturing line is 14um pitch by the circuit embedding method, and below that, facilities, materials, and lines configuration of a new concept are absolutely required. As a countermeasure, a single-layer fine pitch part may be formed in the fine pitch silicon interconnection IC to be mounted on a cavity substrate, the actual die may be connected to the fine pitch silicon interconnection IC, and the IC chip and the cavity substrate may be interconnected. The fine pitch silicon interconnection IC has the strength of being able to sufficiently respond to markets with a 4um circuit pitch or less by proceeding with a semiconductor fab process. Key developments of fine pitch silicon interconnection IC mounting technology include z-axis chip mounting technology in cavity structure of different depth, fine pitch silicon interconnection IC embedding technology, development of cavity substrate/fine pitch silicon interconnection IC bonding technology, and formation of high modulus solder resist(HSR) layer circuit formation. Due to the characteristics of the construction method, the circuit of the HSR layer cannot be formed by the circuit embedding method and the circuit can be formed by the mSAP method, and an embedding substrate manufactured by the embedding of the 4um fine pitch silicon interconnection IC was developed.

Introduction of Reserch Center for 3D semiconductors, and activities of International Standards for embedded device
發表編號:S7-3時間:16:40 - 17:10

Invited Speaker

Yohihisa Katoh, Guest Professsor, FUKUOKA-University

2.Activities of International Standard for Embedded Device at IEC

System Level Co-Design Platform for 3D SiP & 3D electronic module
發表編號:S7-4時間:17:10 - 17:40

Invited Speaker

Masaomi Suzuki, Business Development Manager, Zuken Inc.

In the near future, electrical and mechanical design will be integrated, and a design environment that smoothly links with analysis will become important. Based on this idea, I will introduce ZUKEN’s 3D design environment "Design Force".


S8:Advanced Design, Modeling & Testing I

Oct. 26, 2022 15:40 PM - 17:40 PM

Room: R503
Session chair: Kuoming Chen, Director,UMC / Chang-Chun Lee,Professor, NTHU

A comparative study of single-phase immersion cooling between FC70 and PAO6
發表編號:S8-1時間:15:40 - 16:10

Invited Speaker

Chi-Chuan Wang, National Yang Ming Chiao Tung University

The present study investigated the single-phase immersion cooling in a 1U server with FC70 & PAO6 with the following outline:
1. General background for immersion cooling.
2. FC70 & PAO6
3. Effects of inlet location, flowrate, fin pitch of the heat sink, and supplied power on the thermofluids performance.
4. Summary

LAB Flip Chip Reflow Process Robustness Prediction by Thermal Simulation
發表編號:S8-2時間:16:10 - 16:25

Ching-Ho Chang, Ruey Kae Zang

Mass reflow (MR) soldering is a very popular and stable process in the industry. The applications of MR include flip chip, ball mounting, surface mount technology (SMT), and even reliability tests. More recently, laser assisted bonding (LAB) uses a laser beam as a thermal energy source to focus solder melding on the die area. Compared with traditional MR, this type of localized heating provides several advantages in flip chip assembly. However, the standardized process or best-known method (BKM) for laser power and duration currently does not exist.
According to the previous research, part of the laser beam will be reflected from the surface of the material. In this study, the optimization method was used to find the absorption rate of die by infrared (IR) imaging. The absorption rate was correlated under different devices and scenarios. To fit the instantaneous temperature distribution of the IR image, a transient thermal simulation model with the detailed trace was used. A heat flux is applied on the die surface and part of the substrate to represent the laser beam.
The simulated results of the temperature distribution in the chip area and the distribution on substrate matched the IR image. From the data analysis, the power density required in the simulation is related to not only the power itself but also to the emission time and the substrate area directly exposed to the laser beams. To predict the LAB parameters for a customer cosigned substrate, this study proposes a generic substrate structure that can be used in the LAB process setting without using actual substrate designs. Without the inner trace layout of the substrate, the error margin for the maximum die temperature is expected to increase from within 5% to within 7%.
From the current inspection data, the solder temperature target for parameter setup should be 266°C. The ideal solder temperature range (above 243°C and below 276°C) is established for the laser parameters setup of a future New Product Introduction (NPI). This work provides a methodology that: a.) is capable of predicting localized die temperature using the LAB process, b.) is capable of defining index of solder joint conditions, c.) establishes LAB power and emission time prediction capabilities, and d.) evaluates mechanical stress with localized heating distribution effects.

Thermal Assessment for Chiplets System-in-Package
發表編號:S8-3時間:16:25 - 16:40

Yu-wei Huang

Due to the development trend of portable electronic products are inclined to be thin, small, and well-functioning, the system-in-package (SiP) has been one of the essential packaging architectures in recent years. Because of high-density integration, the thermal management of the system board has been a crucial issue prior to the successful implementation of SiP. The primary heat sources of portable electronic products are resulted from central processing unit (CPU), memory, communication chips, and batteries. Generally speaking, the operating temperature of the CPU with the graphics card is preferably below 90 oC. Therefore, it is necessary to ease the heat generation that can effectively maintain the components’ performance.
However, for the portable electronic products, the heat generation requires to transfer to the external surface of the module/system sufficiently. Then, through passive cooling mechanism, the heat generation can be transferred to the environment through natural convection and radiation. Due to numerous components on the system board, there may be other practical considerations. Moreover, the system's overall module and housing design significantly impact the operating temperature. Therefore, this study only considers the thermal design points and the feasibility of this architecture. This research proposes a novel SiP (system-in-package) architecture, referring to Intel's Lakefield, the industry's first 3D stacking and foveros packaging mobile products. Retains the dimensions and face-to-face bonding technology between the computing chiplet and the base chiplet, changing the memory module from the original PoP (Package on Package) form to a more integrated C2C (Chip to Chip) form. Also, refer to the number of I/Os and TSVs per component and adjust to apply to this architecture. This study used an equivalent technology on the micro-bumps to simplify the model and speed up the simulation time. The research shows that the heat conduction results of the bump layer using the volume equivalent model are highly consistent with the actual model. Therefore, applying this equivalent layer results in this SiP architecture. To further investigate the thermal impact of this architecture, a heat source of 7W was given to the module, referenced from Lakefield's thermal design power (TDP). The logic chiplet is the most significant heat source in the architecture and is the area most in need of heat dissipation. Furthermore, Ellison empirical equation is used to evaluate the natural convection and radiation. It has been verified by simulation that the heat is transferred to other parts of the module through solder paste, thermal via, copper plate, and graphite film to improve the state of heat accumulation on the chip, which can significantly reduce the chip temperature. Thermal vias and metal plates can help package modules dissipate heat vertically and horizontally, respectively. Through the heat dissipation design, the maximum temperature of the chip and the module can be maintained below 90oC to ensure the regular operation of the chip. After the heat dissipation design of this architecture, even if it works in the TDP state and uses passive heat dissipation, it can have reasonable temperature control.

Thermal Performance of Single-Phase and Two-Phase Immersion Cooling in Data Center
發表編號:S8-4時間:16:40 - 16:55

Chun-Kai Liu, Tan-Yi Chang

The boosting of digital technology (e.g., Internet of Things, artificial intelligence, big data, 5G, cloud computing) demonstrates an increasing need for data centers. This increase has triggered the growth of data center infrastructure as processing, storage, and communication system in the digital world. The data center itself has contributed 1.5% to the total world electricity consumption and this is expected to increase with time. The proportion of energy used in the data center covers 52% for information technology (IT) equipment, 38% for cooling, and 10% for supporting devices. One of the problems faced by these centers over the years is the cooling of the electronic components. Thermal management of data center systems is a key bottleneck to technology [1]. Single-phase liquid cooling is limited to low heat transfer coefficients (<2 kW/m2 K) [2] while two-phase cooling such as flow boiling suffers from hydrodynamic instabilities. Immersion cooling has emerged as a potential solution to overcome these barriers by enabling the boiling of a cooling fluid directly from electronic components, thereby removing thermal interface materials and packaging constraints encountered in the aforementioned approaches [3]. The thermal performance of two-phase immersion cooling is studied by numerical [4] and experimental measurement [3]. The high heat transfer coefficient of two-phase immersion cooling can increase the heat flux of components.
In this paper, we study the thermal and flow characteristics of electronic components in single-phase and two-phase immersion cooling by CFD software STAR CCM+. The heated electronic components are mounted on PCB and immersed in the tank filled with dielectric liquid FC40, as shown in Figure 1. The heating power is 50W for each electronic component. FC40 has a boiling point of 165℃. On the other hand, in the two-phase immersion cooling, pool boiling and condensing of dielectric liquid are generated in the liquid tank. The dielectric liquid FC72 with boiling point 56℃ is used, as shown in Figure 2. The VOF Multiphase Rohsenow Boiling Model is adopted to study the pool boiling behaviors. The results show that natural convection can be found in single-phase immersion cooling. The highest temperature of the heated electronic component is 98.13℃ and the temperature difference of the components is 4.25℃, as shown in Figure 3. In two-phase liquid cooling, the liquid is boiling on the component surface and condensation in the cooling tube, as shown in Figure 4. Due to the phase change of liquid, the difference in volume fraction of vapor above the components can be found above the components. Latent heat release of the liquid in boiling increases the heat transfer of electronics components. The highest temperature of the electronic components is 68.71℃ and the temperature difference of the components is only 0.39℃, as shown in Figure 5. Two-phase immersion cooling has better thermal performance than single-phase immersion cooling.

Research on Grid Search Method of Support Vector Regression in Reliability Prediction of Wafer Level Packaging
發表編號:S8-5時間:16:55 - 17:10

C. H. Lee, C. Y. Chang and K.N. Chiang*

Due to the increasingly developed and demanding accelerated thermal cycling of integrated circuits is crucial to reduce the development time of electronic packaging. Therefore, developing effective methods for shortening the development time has been a demanding issue for designing the new electronic packaging. Using the finite element method (FEM) to predict electronic packaging reliability is efficient. However, the accuracy FEM model is to be completed by experts who have a strong background in mechanical engineering. Thus, the recent work focuses on applying artificial intelligence (AI) algorithm, which only needs the input geometry features (the die and stress buffer layer thickness and the pad size, etc.) to predict electronic packaging reliability. For AI models, the optimal parameters of models influence their performance. Thus, finding the optimal parameters of the AI model is vital for the training process. This research used a regression AI model, Support Vector Regression (SVR), trained by the massive structure-reliability database of wafer-level packaging (WLP) created from FEM results, to investigate the grid searching methods for finding its optimal parameters. Grid search algorithm is a classic method for finding the optimal parameters of the AI model, which divides the range of parameters into certain parts and then calculates each data part to find the optimal parameters. This total searching time is very time-consuming. To find the optimal parameters of SVR more efficiently, we adopted the most typically used radial basis function (RBF) kernel. The reason is that the variables of hyperparameters in the RBF kernel are less than the polynomial kernel and have the behavior of the linear kernel and the sigmoid kernel for specific parameters. Furthermore, this research will investigate different grid searching methods, including grid search algorithm and bisection methods, to find the optimal parameters of the SVR model. After that, we proposed the new grid searching method, the fast grid searching method by plane fitting, which used the least-squares method to establish the convex function by the previous results data. The convex function provides the searching path gradient to update the hyperparameters of the SVR model. The gradient descent approach is most common to update the parameters, which is widely adopted in finding the optimal parameters, to calculate the update parameters. According to the calculated results, the fast grid searching by the plane fitting method can significantly reduce the grid searching time, whether in large or small training datasets. It can obviously be seen that the fast grid searching by plane fitting can efficiently decrease the time-consuming of searching the optimal parameters in SVR, and it can be available for quickly searching.

Quantified tabbed lines and ground void impact on real DDR5 eye margin
發表編號:S8-6時間:17:10 - 17:25

Dirack Lai

Tabbed lines have been proposed to reduce or eliminate far-end crosstalk (FEXT) and impedance management with the ground void beneath SMT connector landing pad implementation for DDR5 channel from simulation and tabbed transmission line measurement by a VNA or TDR. In this paper, a method to quantify the tabbed lines and ground void impact on real DDR5 eye margin is proposed. This method starts with the test board design with fours zones of tabbed, non-tabbed, void and non-void ground and follow up with impedance check by a TDR. The final step is to perform four zones memory margin result as comparison to quantify the tabbed lines and ground void impact on real DDR5 eye margin. The quantified results could be good indicators for tabbed lines implementation decision and ground plane void patch mechanism.

TSV Parasitic Extraction in Heterogeneous Integrated 3DIC Systems
發表編號:S8-7時間:17:25 - 17:40


The TSV (Through Silicon Via) is one of the crucial components in making complex 2.5D and 3DIC systems. The TSVs enable short and wide vertical connections between the top and bottom stacked dies and allow for ultrahigh density and bandwidths, as well as for lower power consumption for data transmission. That is especially significant in logic–memory communication where speed and bandwidth are crucial for efficient memory data access. TSVs are also used on the interposers as a vertical connection between the 3DIC dies and the package. The through-silicon-vias introduce new parasitic components into 3-D ICs and those parasitics can have a significant impact on system performance due to their impact on delay, noise, power consumption, and area. Accurate extraction of TSV parasitics, as well as TSV interactions, is important for achieving desired system design PPA requirements. This paper discusses various TSV types and TSV arrangements, and the approaches used in dealing with the TSV parasitics. Those approaches include pre-characterized TSV parasitic models and parametrized tables for TSV couplings, as well as various approximations of the substrate, either as dielectric or as conductor, used to simplify TSV extraction. All of those approaches have their advantages and disadvantages which will be discussed in detail and compared. The main contribution of the paper is that it presents a novel methodology of dealing with the TSVs that can go through multiple dies and the methodology to accurately extract TSV parasitics as well as their couplings with the neighboring metal lines and with the other TSVs. We demonstrate our methodology on a PSMC memory on a logic test case with two types of TSVs, one of which is going through both die. Taking the holistic approach of the memory on a logic system, with one LVS and one PEX deck set, would be impractical due to the two sets of devices fabricated in different technology. Instead of using the holistic approach, we show how to efficiently separate memory and logic die by dividing the long TSVs that go through both dies and how to then accurately extract the TSVs parasitics that consist of the parasitics of the TSV themselves and the couplings between the TSV and the metal lines and the TSV to TSV parasitics. The results show that the couplings between the TSVs through the substrate are frequency-dependent and that the other simplified approaches can be considered as the special cases of our general approach.


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