Poster Sessions


Poster Session(Packaging)

Oct. 26, 2022 15:10 PM - 15:40 PM

Room: Foyer area
Hsu YuLin

A simulation model of the G3.5 Panel-Level-Package copper plating cell is established. This model is equipped with a left-right moving anode array unit and 12 adjustable independent anode zones. The distance between the anode and the substrate is only 25mm. We completed the visualization simulation results of various flow field enhancement designs, such as 1. A perpendicular injects array design to the substrate surface. And 2. A sidewall injection, and 3. U-shaped injection designs are parallel to the substrate. We tested these turbulence flow field data and compared them with measurement data in the plating cell. In the electric field optimization, we adopted a 2-level DOE approach to reduce the number of simulations and obtain a set of the current setting of the 12 anode zones. In addition, optimize the current ratio within the anode's left-right moving range of +/- 10mm. After thoroughly reviewing the electric and flow fields simulation results of this moving anode cell design. We validated the electroplating cell design and the optimized process parameters on the G3.5 glass substrates under different ASD conditions. Obtained the best U% is 11% on G3.5 blanket glass substrates. And the difference in plating film thickness distribution between simulation result and process verification is 6%.

Shih Ping Chang

Flux and other organic solvents are added to the solder during die bonding in advanced packaging process. The primary function of fluxes and other organic solvents is to remove oxides and provide clean solder surfaces in integrated circuit packages. Typically, specific organic acids are added to the flux to enhance chemical activity. To prevent flux residues, cleaning procedures must be performed to reduce residues. Therefore the paper will target different sources of ionic contamination include overall surface/specific location/residue to establish a Rule for the selection of ion residue testing machines for different ion pollution sources These include surface ion residue testing machines, surface cleanliness testing machines and ion chromatography machines.

Hsin Yu Chang

As the demand of high-speed wireless communication (5G) and connections to everything (IoT) arises, the operational frequencies of antennas were increased. For the past few years, the PCB market has been evolving toward high density, multi-layer and miniaturization. Hence as the connections of electric elements increase, it inevitably demands smaller diameter vias. As a result, the conventional mechanical drilling is no longer capable of fulfilling the industrial need. By the time the PCB industry moves to the next generation called Substrate-Like Process(SLP), high pulse energy(HPE) pico-second laser is considered able to meet the calls for miniaturizing the hole diameter and line separation down to 10 microns. HPE pico-second laser drilling is a non-contact process which exhibits lower temperature therefore smaller heat affect zone, while avoiding risks such as broken blade. With these advantages, it further encourages domestic facility industries to achieve independent R&D in via process technology for next generation. For high optical stability, utilized in 5G materials, there are some real time detectors in this optical system. It includes position sensing detector, power sensor and beam profiler. All of these real time detectors are utilizing for ultra-fast laser system stability. After the laser processing, it is important to do the real time verification for via quality with non-destructive inspection. The ultrafast laser for material processing concentrates the pulse energy into the scale of picosecond or femtosecond temporal duration. The high peak power would induce nonlinear multiphoton fluorescence, material modification and photoablation with higher pulse energy. With the increase of processing resolution and complexity, we would propose the real time method by integrating with multiphoton excited fluorescence microscopy (MEFM) to directly monitor the processed structure in specimen for verification and analysis. In this paper, we would show the setup of FPGA-based MEFM and adopt the single photon counting (SPC) technique for high signal-to-noise (SNR) images. The image spatial resolution is submicron level. To the need of the high bandwidth electrical components and applications in industry, companies are developing different kinds of composite materials and insulators together with the technology of different kinds of laser processing methods and protocols including direct writing, drilling, and modification with etching-assistance. Glass, ABF and polyimide (PI) are important materials for the insulation layer in 5G material design and the narrow electrical routing structures are especially required to be confirmed after processing. We have shown the MEFM can detect the axial-resolved images of the laser modified surface on the silicon glass and the laser-cut structure on the PI film without damaging the specimen. The result shows the potential ability for rapid 3D examination of the laser drilling specimen.

T. Y. Ouyang, Y. T. Hung, O. H. Lee, S. Y. Li, W. L. Chiu, T. Y. Hung, S. H. Wu, and H. H. Chang

The through-silicon-via interposer is recommended to enable 3D integrated circuit integration. However, the electrical design and manufacture of high-density TSV is a challenge and has low fabrication capability. In this report, we have demonstrated a novel concept about a pre-fabricated high-density TSV interposer. A commonly reusable TSV design can eliminate the concern of the compatible issue to interconnect with the RDL trace. A 3% open ratio TSV with the diameter-to-depth aspect ratio 1:10 over 300 mm wafer is ultimately produced based on the modification of the dry Si etch parameters and subtle electroplating conditions to achieve a straight and void-free TSV. The pass-through current density on the TSV array can be effectively enhanced for a high I/O pin count application. The signal can reserve the integrity and possess an 8 Gbps transmission rate at 20 GHz high frequency. A pre-fabricated high-density TSV interposer can effectively reduce the production time and promote the throughput in 3D integrated circuit applications.


In order to increase (Inputs/Outputs) I/Os and reduce power consumption, solder micro-bumps have been adopted as vertical interconnects in 3D IC technology. As bump size shrinks continuously, the effect of intermetallic compounds (IMCs) becomes more pronounced. Growth of IMC at top and bottom side of bump is homogeneous when isothermally reflows. However, growth of IMC becomes asymmetric when a temperature gradient is applied. Cu atoms at hot end will diffuse to the cold end that leads to higher IMC growth rate at cold end, which is known as thermo-migration. Cu/SnAg/Cu and Ni/SnAg/Ni solder micro-bumps with 30 µm diameter are used in this work. Isothermal reflow of micro-bumps at 260 ℃ is carried out as controlled samples. On the other hand, reflow under various temperature gradients is implemented. Different number of silicon wafers are put on the top die to change the temperature gradient in solder. In this study, growth rate of IMCs in Cu/SnAg/Cu and Ni/SnAg/Ni solder microbumps is measured. Since the bump height is only 12 µm in solder micro-bumps, IMC growth has a great impact on resistance change. In addition, we observe significant thermomigration in Cu/SnAg/Cu solders, but not in Ni/SnAg/Ni solders.

Sri Harini Rajendran, Seong Min Seo, Jae Pil Jung

With the progress in miniaturization and portability of consumer electronics, soldering, one of the essential joining techniques, faces a setback due to the growth of Cu-Sn IMC at the solder/substrate interface. Nanocomposite solders gained superiority in refining the microstructure, suppressing the Cu-Sn IMC growth at the interface and providing the dispersion strengthening to the solder matrix. However, dispersion of nanoparticles is challenging task, especially with the downsizing of the solder joints. Presently, nanoparticles are dispersed in solder paste and printed for surface mount technology (SMT) and ball grid array (BGA) packages. However, nanoparticles are expelled during reflow due to the flux volatility and the expelled nanoparticles amount increases with decreasing the pitch size. Ultrasonic melt dispersion (UD) is proved to be one of the best technology for second-phase particles dispersion in Al and Mg alloys. However, this technique is seldom discussed for nanocomposite solder alloys. The present work investigates the dispersion strategy of nanocomposite solder for ball grid array application. SAC 305-ZnO bulk nanocomposite solder is fabricated via ultrasonic melt treatment. The bulk solder is investigated for the spreading ratio and contact angle using spreading test (Japanese Industrial Standard 2003: JIS-Z-3198-3, structure-property relationship using microstructure and tensile test and thermal stability using aging tests. Consequently, the bulk solder is rolled, punched and made as BGA solder balls and studied for the amount of nanoparticle retained using ICPOES. The mechanical property of the solder ball was investigated using shear tester and reliability is analyzed using Weibull analysis The spreading ratio of the ZnO nanocomposite solder improved by 5.7%, attributed to the stable ZnO/molten Sn interface. The microstructure revealed significant grain refinement in as-cast and after aging. Accordingly, the nanocomposite solder exhibited superior tensile strength with acceptable elongation loss. Solder balls prepared from the ultrasonic melt treatment technique retained an average of 38.6% of ZnO nanoparticles after reflow. Ultrasonic dispersion leads to significant primary β-Sn grain refinement of 13.1 μm in BGA solder ball. The micro hardness and shear strength of ultrasonically dispersed nanocomposite BGA joints increased by 14.6% and 17.1%, respectively. Reliability is calculated from Weibull analysis shows increasing trend in Weibull modulus. In summary, for BGA soldering, solder balls prepared from ultrasonic dispersed nanocomposite SAC 305 ingot can be an effective option to improve the reliability. Keywords: Nanocomposite solders, ultrasonic melt treatment, dispersion, ball shear strength.

Mak Hoi Chau, Chung-Long Pan, Yu-Jung Huang

The main development trend of modern microelectronics is to continuously reduce product mass and dimension, increase their performance and reliability. The wide application of multi-chiplet architecture in high-performance computing clusters has aroused great interest. The multi-chiplet placement can influence the signal transmission behavior in a 3D integration architecture. Inter-chip communication has remained a major design factor due to the diverse traffic requirements in heterogeneous multi-chiplet systems. In general, to exploit the capabilities of a multi-chiplet architecture without I/O bottlenecks, dense vertical connections in stacked chips become of increasing importance in modern semiconductor technology. Consider a heterogeneous or homogeneous multi-chiplet architecture with a dense vertical connection system that gains a performance per energy benefit from fast state migration between these chiplets. In this paper, we study the effects of the signal transmission on different chiplet placement designs, where the wirelessly connected multi-chiplets modules are proposed. The inter-chip wireless heterogeneous or homogeneous multi-chiplet architecture is modeled using a high-frequency structure simulator, in particular, the placement effect of the side differential vertical signal transmission is analyzed.

Chi-Min Cheng, Hsi-Wei Chao, Chu-Chiao Yen, Kun-Ting Chiang, Wei-Yao Chang, Chia-Wen Chang, Ya-Ping Chen, Hsien-Wei Ho, Chun-Yu Ko, Chun-Liang Kuo

With the rapid development of technology, the number and demand for handheld devices are increasing, and the new technology product development and launch are getting faster and faster. Also, handheld devices need to withstand various movements, fall-down situations, and even normal use in different temperature environments. Therefore, solder joint reliability is really crucial for handheld devices. Moreover, how to seize the key factors during the design development phase and fulfill market demands are also significant. According to the definition of JESD22-B111, the drop test requires that the board should be horizontal with the package facing in the downward direction (-Z) during the experiment. Therefore, under the influence of the acceleration of gravity, the weight of the BGA (ball grid array) package, the number of balls, solder ball material, and the solder ball pad size in the drop test are recognized as important factors affecting the board-level reliability of the drop test. This paper will explore these key factors, and how they affect board-level reliability of the drop test. Two of the key factors, solder ball pad size, and solder ball number would both affect and determine the total contact area of the ball. Then, the interaction of the key factors, there was a conclusion through experiments and calculations: when the package weight was divided by the contact area of the solder ball, the weight per unit area could be obtained. The greater the load-bearing capacity per unit area, the greater the risk of failure for the samples. Conversely, reducing the package weight or increasing the solder ball contact area can substantially reduce the risk of failure. In this study, samples with different ball contact unit areas and different package weights were collected for testing, and the solder balls were fixed using SAC1205. The characteristic life (63.2%) data was obtained by Weibull analysis, and the load-bearing capacity per unit area of the ball contact was analyzed and compared with the characteristic life (63.2%). Finally, we could get the trend curve to predict the performance trend by the risk level and the characteristic life (63.2%). Furthermore, it could even predict the board-level drop test ability of the load-bearing capacity under different unit areas. This prediction trend can provide designers with a design reference. In the product development stage, the prediction model can improve design capabilities and accelerate the product development schedule. Additionally, using this analysis method could meet market demands, avoid the waste of experiment costs, and finally, improve industrial competitiveness.

Hsiang-Chen Hsu

Fingerprint recognition is one of the most well-known digital identifications and has been widely used on forensic science, criminal investigation, financial services, electronic smart locks ...etc. In this paper, latent fingerprint marks have been image segmentation and reconstruction based on the Unet method. In the first, latent fingerprint marks were collected on Ninhydrin reaction thermal-induced paper and the image of fingerprints were segmented using Unet algorithm. Secondly, mutilated fingerprints were image reconstructed for the whole loops and whorls on a finger. And lastly, a Receiver Operating Characteristic (ROC) curves scheme has been applied to analyzed classification accuracy of a statistical developed model.

Liang-Yu Ou Yang and Chia-Hung Kao

In this paper, an easily implemented calibration method to extract the equivalent circuit of the bump interconnection is proposed. Benefitting from the symmetry and reciprocity of the designed flip-chip interconnection, the calibration kit for this design can be composed of a single component. A lossless T-type network that consists of two identical series inductances and a shunt capacitance is used to model the bump interconnection. The experimental data for the frequency response from dc up to 40 GHz have an acceptable agreement with the theoretical and simulated results. This study may be useful for millimeter-wave packaging applications.

Chung-Yu Ke

With the development of smart phones, the developing direction of Application Chip (AP) is to be thinner and lighter. FOPOP is the mainstream packaging mode to cope with the ever-increasing layout density. In the mobile phone market where a hundred schools of thought contend, to cope with mobile phone APs of different brands and performances, the structure of w/o memory stacking has gradually become the mainstream of the FOPOP structure. The FOPOP w/o memory stacking, in order to complete the memory stacking of different brands and the application of mobile phones at high frequencies, there are strict requirements on the material of the connection surface. Among them, Build-up Film, due to its low dielectric constant (Dk), low dielectric loss and low coefficient of thermal expansion (CTE) at high frequencies, can solve problems such as transmission loss and package warpage. In order to achieve memory stacking, we used the laser drilling technology on the Build-up Film to reveal the pattern that connected to the Memory, and fill the solder into the drill hole in advance, which is convenient for the end product to stack the Memory. The shift of the laser drilling will directly affect the difficulty of stacking the Memory, which will eventually lead to the opening of the circuit. Hence, the shift of the laser drilling is one of the necessary inspection items. However, Build-up Film is a non-traditional transparent film, by laser microscope, we cannot know the position of the pattern under the Build-up Film, and cannot measure the shift. The Infrared (IR) Microscope is generally used to detect backside and side wall cracks in silicon die. The purpose of detection is achieved through the characteristics of IR long wavelengths that easily penetrate Silicon. Relatively, the red light laser microscope that most commonly used in the production line cannot penetrate the Build-up Film due to the short wavelength of red light. Hence, we use long-wavelength IR to penetrate the Build-up Film, and use a correction sheet to correct the length to ensure the accuracy of the length measurement. The measurement of laser drilling shift is achieved, to ensure the quality of laser drilling. Finally, we confirmed that the error between IR Microscope measurement result and cross-section & SEM is within 3.5um, so IR Microscope is a feasible measurement tool for laser drilling shift of Build-up Film.


Abstract— With the rapid development of science and technology, electronic products are moving towards the goal of miniaturization and multi-function. With it comes the problem of heat dissipation. Thus, Quad Flat No-lead (QFN) Packages have become popular in the IC market and are widely adapted by many companies due to better down-forward thermal path. The packaged chip is generating heat, which need dissipate in order to avoid overheating problem. Therefore, most QFNs are equipped with a metal based thermal pad at the bottom of the package, which is in direct contact to the silicon die through epoxy die attach (DA). This structure can help dissipate the heat in direction of the PCB to reduce chip temperature. In this paper, this study is focusing on Quad-Flat-No-Lead (QFN) package mounted on a JEDEC PCB to understand the temperature behavior and observe the impact of the parameters of package includes structure (Die-to-Package size ratio / Die-to-Pad size ratio / DA / PCB thermal vias / Gold wire) and material (EMC / DA / Lead Frame). On package side, we discuss about Quad Flat No-lead (QFN) of size 4mm*4mm to 7mm*7mm, with different die size and DA thickness. With the development of high thermal dissipation material in recent years, EMC and DA with higher thermal conductivity (K value) were considered to reduce thermal resistance. Thermal effect of Lead Frame material of A194 and C7025 were taken into account in this study as well. On another hand, PCB design is a major factor to dissipate the heat. PCB thermal vias underneath pad are usually used to dissipate the heat away from the package and to directly transfer heat from the top metal layer of the PCB by conduction to the inner and bottom metal layer or to the other environments by convection and radiation. In order to evaluate the thermal performance study, Finite Element Method (FEM) simulation was carried out to investigate the influence of various design parameters that involve PKG and PCB. In evaluating the numerical three-dimensional (3D) model, the critical junction temperature that were extracted from the numerical model to calculate thermal resistance of Theta JA for further comparison. In brief, numerical simulation model results show QFN packages and the necessary design optimization that can reduce thermal resistance in the integrated circuits. For thermal impact weight, Die size effect ≥ K value effect of Die attach > K value effect of Mold compound ≥ PCB via effect > K value effect of Lead Frame > Gold Wire effect. Keywords— quad flat no lead (QFN), JEDEC PCB, junction temperature, thermal resistance, thermal conductivity (K value), 3D FEM

Shijuan Qin, Patt Chang, Falconee Lee, Thonas Su, Denis Chen, Bennet Huang, Weijie Yuan, Mark Cao, Aje Chang, Donald Fan, YL Li, Jimmy Hsu, Kevin Liang, Bryant Tsai, Kate Tzeng

The trend of using 48V as the intermediate bus has become a hot topic in server. 48V brings advantages to server power delivery, but there are still some problems of its own. There are many high-speed signals routed in the server mother board, those traces are sensitive to noise caused by Voltage Regulator (VR). Currently, 48V only exists in some special areas of the motherboard. This paper will introduce an innovation study to use two stage power architecture for 48V rack, based on this architecture, compared distribution loss and PCI Express* noise coupling between 12V and 48V within same Printed Circuit Board (PCB) layout.

Ho Chuan Lin

Abstract Abstract -As silicon scaling closer to physical limit, future reduction of the gate oxide does not lower down the cost per-transistor. But the demand of higher functionality and lower cost of electronic devices do not slow down. Development of electronic devices metaphor to high-density package integration. What the electronic industries do is to break down a large die to a chiplet based devices for improving yield and lower the total cost. Chiplet package become a key technology to continue Moore’s law. With the intensive researches, multiple chiplet packages are evolved such as multi chips on Si interposer using TSV (2.5D), die to die stack on each other (3D), Fan-Out Multi Chip Module (FOMCM), and EMIB (Embedded Multi-Die Interconnect Bridge). These packages are developed for the server, high performance computing, router, and switcher markets. A 3D system integration technology platform with high interconnection density and high bandwidth is desirable to realize both directions.The growth of artificial intelligence, internet of things and 5G technology demands for much higher data rate. Though Moore’s law has come to end. But, the need of high functions devices are not stopping. The rise of AI artificial intelligence and the expansion of applications have created a large number of computing demands.The application of high-bandwidth memory(HBM) is increasing day by day. The package type integration of high-bandwidth memory(HBM) has been discussed. This paper is to present the electrical metrics on Fan out multichip module on substrate (FOMCM) at industry benchmark by numerical analysis. The model renders the transportation performance of bit source deployed at high speed memory bank connection, and communicate the through-hole-via routing at fan-out scalable area, then reach to another logic cell chip bank. The raised-module solution is key to jump across the accelerator wall by advocating on bit-per-joule for next high performance computing.

YC Chang, Eason Hsu, Andy Chen, and Andy Huang

Wi-Fi 6E is the new WLAN standard from IEEE 802.11 category, which provides wider un-licensed channels and bandwidth, flexible resource unit for connected devices. To deliver competitive product, we successfully established the new double-side-molding module. This brings design challenge for the miniaturization of Wi-Fi 6E module. We implemented mSAP PCB, strip grinding after molding, then laser ablation process to deliver highly integrated, compact, robust module. It fits for mobile devices with flexibility of LAA and UWB co-exist, which also extend productive life cycle of smart phone application. And we also developed software tools to assist validation processing and concentrate TXP spread. All those efforts can be leveraged for future projects.

Jimmy Hsu, Steven Wu, Kuan-Ting Wu, Brian Ho, Lemon Lin, Jim Tseng, Thonas Su, Betty Chen

As the data center industry grows rapidly and signal data rate increases, the channel design and electrical characterization is getting more and more important. How to identify design quality issues earlier and implement corresponding solutions are very critical for customer time-to-market. In this paper, a systematic and efficient approach was proposed to seamlessly correlate the physical hardware design, channel electrical characteristics by Intel® Automatic In-board Characterization (AIBC) and electrical validation (EV) for customer design robustness [1]. Most customers directly build boards with the simplified channel loss prediction to meet the electrical specification and conduct electrical validation once system is functional. However, channel loss prediction may not be well correlated with the real board measurement by the manufacture variation or inaccurate modeling. The risk will be higher if this channel loss prediction is under estimation and over the design criteria. If customer skip board level quality check and there is any issue related to board design, it can only be found at EV stage and it is quite late from an overall timeline point of view. Meanwhile, it may take more time in problems solving to impact customer time-to-market. In addition, it takes a considerable amount of time and resource to pre-process these data with various formats and types to seamlessly link hardware, SI and EV. How to process these data systematically is also very important to identify design defect and EV issues efficiently. This enhanced process is proposed to ensure customers design and manufacture quality earlier by Intel ® Automatic In-Board Characterization and end-to-end(E2E) check and reduce debugging resource before electrical validation. To identify design defect on the early stage, AIBC was adopted to efficiently characterize mother board design quality with over thousands of high-speed I/O(HSIO) testing for the impedance and loss for signal quality check before EV testing. The end-to-end measurement can verify the whole channel signal quality, including the riser, cable, etc. besides mother board by AIBC. The proposed methodology demonstrates an effective approach to characterize channel design and closed-loop interactions among hardware design, signal integrity and electrical validation. In these customer cases, the correlation among channel loss and EV margin can be clearly observed. The board design and manufacture quality risk could be clearly identified by AIBC measurement on the early design phase. With the support of AIBC and EV mapping method, it is more efficient to check PCB design quality and manufacture impact on EV. The next step is to make this methodology better and to extend the coverage besides mother board, such as automatic E2E measurement for PCIe topology including the riser, cable etc. for better debugging efficiency and optimizing the measurement database can make correlation more convenient. In summary, this enhanced methodology was proposed and successfully applied in customer real design cases, which made it promising and important in the data center related design industry.

Gary Tsai

For Power Delivery design, the Z(f)impedance of power rails (e.g. CORE/GT/SA/VDD2) is required to meet Intel criteria in each generation of platform. Customer may not perform PI simulation to check if board level routing Z(f) can pass LL (Load Line) specification or not. Instead of relying on actual validation to see if any issue is related to the power rail design. Then modifying the rail routing to lower the Z(f) impedance and meet criteria in next board re-spin which cause additional time and cost. The symbol pattern reserved in board layout can help customer to save time (no additional PCB to check) if the design hit any Z(f) impedance problem. The idea of “Impedance Implementation Pattern” is kind of short-pad of L-shape symbol pattern which will be observed when place it on PCB top side or bottom side. But when the design implement in early phase to fix the system hang issue concern, the short-pad can be removed in MP (mass production) phase. Below is what the concept focused on. • This proposal is to implement the symbol pattern into rail routing to be reserved in layout just in case the LL of each rail can’t meet Intel criteria (refer to INTEL EDS) • When customer found their design can’t meet LL criteria then they could use short-pad soldering on PCB top side (or bottom side which based on the location of short-pad) then the entire impedance will be lower and meet the criteria • The symbol pattern will require additional routing space in layout inner layer or may need additional PCB layer added for this purpose • Basic concept of the symbol pattern is using the equivalent resistance formula 1/R=1/R1+1/R2+......1/Rn • We expect customer to implement the symbol pattern in their board file design then check if need to adopt it according to simulation result of LL (Load Line) and trying to shrink the impedance value to meet Intel criteria • Symbol Pattern will be L-shape or specific rectangular shape with certain impedance

Kuo Yung-Sheng ; Tseng Weng-Ching ; Nhlakanipho Sikhondze

Since their inception in the 1980s, IGBT voltage and current values have improved to 6500V/2400A, the switching time to 40ns, and the operating frequency to 40 KHz, all of which are still being enhanced. While the current flowing through the IGBT module(s) is large, the switching frequency is also relatively frequent, causing the module’s temperature to rise. An IGBT liquid cooling thermal dissipation module mainly uses the characteristic of a liquid’s specific heat being larger than that of air, allowing the liquid to absorb a large amount of heat energy emitted by the chip. This research discusses the thermal influence of the pin-fin angle and spacing of a liquid cooling module, and uses CFD simulation software for validation. DOE (Design of Experiment) is a mathematical statistical method for arranging experiments and analyzing experimental data, which mainly arranges experiments reasonably, and obtains ideal experimental results and scientific conclusions with fewer experiments, cycles and costs. A set of 4 angles and a set of 13 pin-to-pin distances are selected as input factors for numerical simulation, and the final simulation result is Tjunction. For comparison, Tjunction is defined as the wafer junction temperature. The flow and heat transfer of objects in this study follow the mass conservation equation, the momentum conservation equation, and the energy conservation equation. The mathematical relationship is as follows: ∂ρ/∂t+∂/(∂x_i ) (ρu_i )=0 (1) (∂ρu_i)/∂t+∂/(∂x_j ) (ρu_i u_j )+∂p/(∂x_i )=∂/(∂x_j ) (τ_ij+τ_ij^R )+S_i (2) ∂ρH/∂t+(∂ρu_i H)/(∂x_i )=∂/(∂x_i ) (u_j (τ_ij+τ_ij^R )+q_i )+ ∂p/∂t-τ_ij^R (∂u_i)/(∂x_j )+(ρε+S_i u_i+Q_H ) (3) where u is the fluid velocity (m/s); ρ is the fluid density (kg/m3); S_i is the uniformly distributed load per unit mass (N/m2); QH is the heat source (W); τij is the viscous force tensor (N/m); q_i is the heat flux (W/m2); ε is the turbulent kinetic energy dissipation rate. The heat transfer between solid and fluid is solved by conjugate heat transfer, and the mathematical relationship is as follows: ∂ρe/∂t=∂/(∂x_i ) (λ_i ∂T/(∂x_i ))+Q_H (4) where e is the specific internal energy (e=c‧T) and c is specific heat. In this study, water was used as the working fluid, and the flow rates were set to 1LPM, 5LPM, and 10LPM. When the pin-fin angle was increased, the junction temperature became higher. Although the junction temperature rose slowly, it was still above the maximum operating junction temperature of an IGBT module. Furthermore, when the pin-fin spacing was increased from 1mm to 8mm, the junction temperature rose at a faster rate. Therefore, the results from this study suggest that the pin-fin angle should be, or close to, 0° (perpendicular to fluid flow direction) and the spacing between pin-fins should be as small as possible when designing liquid cooling thermal dissipation module. This allows for the achievement of the maximum number of fins and heat dissipation area can. A design like the aforementioned one will prolong the stagnation time of the coolant in the cavity and effectively achieve the effect of heat dissipation. Keywords Liquid cooling, thermal influence, pin-fin

Fu-Hsiang Chang, Kuo-Chi Chang, Hsiao-Chuan Wang

For Taiwan's semiconductor industry supply chain, the upstream is IP design and IC design industry, the midstream is IC manufacturing, wafer manufacturing, related production process testing equipment, photolithography, chemicals and other industries, and the downstream is IC packaging testing and related production process testing. Taiwan's IC manufacturing sector, the epidemic has not slowed down. In order to avoid chain disconnection and market share, downstream manufacturers have successively increased inventories and even urgent orders, making Taiwan's foundry industry still perform well in the second half of 2021. This research first conceives the control system requirements, and uses PLC to build the system, then uses MATLAB to build the corresponding simulation model, and uses the configuration software to design the important safety human-machine interface to complete the communication function between the human-machine interfaces based on two models. Two models are studied for testing. Under the same input conditions, the physical model and the simulation model can achieve the same input and output conditions, and the possibility of using the simulation model for the electrical control safety design of ISD of new recruits in high-tech factories is verified. This is an important contribution to this research.

Timo Teng, Mark Wang, Jimmy Hsu, Wayne Lee, Thonas Su, Jenny Kan, Betty Chen

PCI-Express (PCIe) channel design is very challenging for 32GT/s applications, and channel loss management and impedance matching are very important for system robustness, especially for the channel with multiple connection configurations. In this paper, several important design strategies were applied to optimize out-of-guideline three connector topology. The channel insertion loss is reduced because of lower motherboard loss meeting PCI-SIG requirements for various applications. Increased voiding in the adapter card and better cable quality were adopted to improve channel impedance matching. Intel® Automatic In-Board Characterization (AIBC) and end-to-end electrical characterization using Intel® IO Margin Tool (IOMT) were adopted to efficiently investigate the electrical design quality. Customer time-to-market was much improved because of this comprehensive analysis.

Joshua Lan

In a world full of detection devices, photodetectors are of great importance. Two- dimensional materials have excellent optoelectronic properties, suitable for active layer of silicon-based photodetector. The most typical example of a 2D material is graphene, which boasts high carrier mobility, high light transmission and excellent thermal conductivity. The effects of resonant cavity are measured by the response of the photodetector. The project is divided into two main directions: (1) resonant cavity-free graphene photodetectors(control group) (2) resonant cavity-Si based graphene photodetectors(experimental group) In this project, different resonant cavities(Pattern1+Etching and Pattern2+Etching) are fabricated on silicon substrates through photolithography and etching, to improve the optoelectronic properties of photodetectors, as shown in Figure 1(a). In addition, the experiments spin-coating Reduced Graphene Oxide, namely rGO, on silicon substrate, as the active layer of the graphene photodetectors, the structure of the photodetector is also shown in Figure 1(a). Figure 1(b) demonstrates the process flow of photodetector fabrication, and a picture of a final sample (the other samples look the same: Graphene photodetectors with interdigitated electrodes). As for the result, compared to the device without resonant cavities on silicon substrates, the responsivity of the photodetector with resonant cavities on silicon substrate is enhanced by 1.5~2 times, reaching around 300A/W and a specific detectivity, D*, of nearly 1013 Jones under white light and room temperature and bias:3 Volts. Based on the results, it is concluded that 1600rpm*1800rpm is a great option for spin coating rGO. Above results are backed up by theoretical analysis and formulas. The external quantum efficiency(EQE) of the devices with resonant cavities, are about two times higher than the ones without. Under raman spectrum, photodetector has stronger intensity at raman shift of 900, 1400, and 2700 cm-1. At those raman shifts: Spin coating rGO with spin rate of 1600rpm*1800 rpm, photodetector has higher intensity than that of 2200rpm*2400rpm, which again proves that 1600*1800rpm is a relative better spin rate for spin coating rGO. Since the structure of those photodetectors are simple, this kind of photodetector can be widely used. Although the magnitudes of results(responsivity, detectivity, external quantum efficiency, and so on) may vary from one research to the others, the method of “creating resonant cavities on silicon substrate to improve response of Graphene photodetector” can be applied in similar cases.

Hung-Hsien Ko, Yun-Yi Huang, Yu-Chiao Tsai and Heng-Yin Chen

The wireless non-contact electromyography (EMG) signal sensing system was developed with impedance compensation. The non-contact electrodes were designed with two sensing electrodes and a ground electrode for noise reduction. The algorithm were designed to compensate the impedance of EMG signals between human skin with textile material for improving the accuracy of EMG sensing circuits. The flexible EMG sensing system would help users monitor muscle activity during exercise.

Meei-Yu Hsu

Epoxy resin has been widely used in electronic and other fields. It has been commonly used as an insulating material for semiconductor packing for its excellent mechanical properties and heat resistance; however, the rapid development of high-voltage and high-power modules that lead to the accumulation of excessive heat. Consequently, the properties of encapsulant would be destroyed, module performance would be reduced, the service life was also be shorten. Thus, it is important to design a package materials with high thermal conductivity. A novel thermal conductive epoxy resins with mesogen structure and aliphatic chain are synthesized and developed, the resin demonstrates low viscosity as the temperature less than 100oC. The chemical structure was identified by 1H-NMR. Viscosity of the thermal conductive epoxy resin is 2.54 Pa.s at 90oC. The reaction of thermal conductive epoxy resin compositions are evaluated by DSC. It is showed one of composition exhibiting exothermic peak around 132oC, the enthalpy is about 414.5J/g, implying the good reactivity of the novel thermal conductive epoxy resin. Thermal conductivity of the composition which containing the synthesized thermal conductive epoxy resin in this study is 0.30 (W/m.K) by used of laser flash method. The novel thermal conductivity epoxy resin demonstrates promising properties for semiconductor packaging applications.

Chien Hsun Chu

Fan-out packaging technology (FOP) is one of the main trends in microelectronic packaging, which is mainly realized by using copper redistribution layer (Cu-RDL). In the future, panel-level packaging is quite promising due to increased productivity and cost reduction. However, the panel-level electroplating process is prone to the edge effect of the electric field, resulting in the problem of uneven film thickness, so thickness uniformity is the most critical factor. In this study, we first use the simulation system to simulate the flow field and electric field behavior in the electroplating bath, and then analyze the effect of Cu thickness uniformity, followed by the actual verification on the panel-level electroplating. Finally, we fabricated the Cu-RDL with an average thickness of 10 um and the thickness uniformity of more than 80%, which was successfully applied to transparent active component. The component have high transmittance at visible wavelengths (300-800 nm) and low return loss. Our electroplating simulation system technology can effectively reduce the number of experimental verifications. Therefore, it is quite suitable for the preliminary development of various electroplating technologies.

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