S25: Advacned Design & Emerging Modeling
Oct. 28, 2022 13:30 PM - 15:30 PM
Session chair： C.A. Yuan, Assoc. Professor, FCU / K-J Chung, Assoc. Professor,NCUE
RF Filter device Packaging Technology Trend
發表編號：S25-1時間：13:30 - 13:45
5G & 6G wireless communications are expanding spectrum bands into sub-terahertz frequencies, and RF front-end modules (FEM) are key devices for such frequency bands.
This paper introduces the RF filter device packaging technology trend with actual device tear-down study for understanding the next-generation technology approach.
And will discuss the key core technology of RF filter device packaging.
- Study of RF filter device packaging history with x-rays analysis
- Key RF filter packaging technology trends
- Wet chemical solution for RF device process
Keywords: RF filter device, 5G, X-rays analysis, AlN & Al etching rate
Warpage Analysis of IC Packages with Fine Pitch Substrate
發表編號：S25-2時間：13:45 - 14:00
Some IC packages use lead-frame as the conducting interconnect and supporting carrier for dies. However, with the advancement of technologies, the demand for more interconnects in a package has been raised, and the available pin-count of lead-frame type packages is not high enough. Therefore, in the application field, substrate-based IC packages such as BGA (Ball Grid Array) or flip-chip are attracting more and more attentions recently. In past substrate-based-package simulation studies, substrates were commonly modeled as a single material layer with average material properties. This paper builds the RDL (Redistribution Layer) model in detail and makes the model as close as possible to the actual design.
This paper uses ANSYS trace import function to build a substrate mesh model, then uses Moldex3D to perform mold filling and post mold cure analyses on the complete package. P-V-T-C model, which considers both volume shrinkage due to thermal mismatch and chemical shrinkage, was used to predict the amount of warpage and residual stresses after the mold filling process. Next, the dual shift factor model for viscoelastic analysis was adopted to model the post mold cure process and predict the amount of warpage and residual stresses after the post mold cure process.
After comparison, it was found that results from both simulations and experiments agree well in both the warpage shape and amplitude after post mold cure process. In addition, it is found that the amount of warpage of each single unit at different locations in the strip is not the same. The magnitude of warpage values for each unit ranges from 9.4μm to 228μm.
Effective Modeling of Circuit Substrate for Flip Chip Chip Scale Package Using Trace Mapping
發表編號：S25-3時間：14:00 - 14:15
Wen You Jhu
Recently, to enable increased electrical performance, maximal I/O
density, and miniaturization, advanced packaging technologies such
as flip chip package on packaging [1,2] and flip-chip chip scale
packaging (FCCSP) [3,4] has emerged. In this packaging technology,
high-end chips are bonded onto a multi-layer circuit substrate. To
better comprehend the thermal-mechanical behaviors of the FCCSP so
as to assess its thermal-mechanical reliability [5,6] it is essential to
conduct detailed modeling and simulation of the multi-layer circuit
substrate. However, the circuit substrate is typically composed of a
great number of miniscule copper (Cu) pads and vias, and also various
Cu circuit layers surrounded by a prepreg (PP) dielectric material
together with a top protective material. Thus, it presents enormous
challenges and difficulties to straightforwardly and accurately model
the circuit substrate with multi-material and complex geometric
compositions using numerical approaches such as finite element
analysis (FEA). To ease the technical difficulty, effective modeling [7-
10] can be a very promising approach.
This study proposes a novel effective modeling approach to
accurately assess the equivalent material properties of circuit
substrates with complex geometry FCCSP. This effective modeling
approach integrates FEA, electronic computer-aided design (ECAD)
trace mapping (TM) technique [5-7], and a rule of mixture (ROM)
method [1,2,8-10]. This effective modeling is hereinafter termed
TM/FEA-based effective approach. The TM technique allows an
accurate, efficient and precise depiction of the microscopic, complex
Cu traces, pads and vias. A brief description of the TM procedure is
illustrated in Fig. 1. By this technique, the complex Cu traces and vias
in a Cu metal layer of the substrate in a high resolution ECAD model
are mapped onto a constructed three-dimensional (3D) finite element
grid with regularly- and uniformly-distributed mesh [1,2].
Furthermore, the ROM method is applied to estimate the average
element elastic properties, namely Young’s modulus, coefficient of
thermal expansion (CTE), and Poisson’s ratio, based on the volume
fraction of the Cu metal and the other material on each element. At
last, with the mapped Cu traces, vias and pads, together with the
calculated average elastic properties on each element, FEA is
performed to calculate the equivalent elastic properties of the Cu metal
layer. It should be noted that the Cu metal layer can be modeled as an
effective isotropic, orthotropic and anisotropic elastic material .
The above procedure is repeated until the effective elastic properties
of all the Cu metal layers in the circuit substrate are completed. At this
stage, a 3D finite element model of this circuit substrate with multimaterial
and complex geometric feature can be developed.
To demonstrate the effectiveness of the proposed TM/FEA-based
effective modeling approach, the calculated displacements under the
tensile and thermal loading are compared with those of several other
different approaches, such as the detail FEA modeling and the
conventional direct ROM averaging technique [4,5] that assumes the
Cu metal layer to be an isotropic elastic material. Besides, the results
calculated based on the effective orthotropic material assumption for
the Cu metal layer are also compared with those of the effective
anisotropic material assumption.
The predicted substrate’s effective elastic properties are further
utilized in the warpage process simulation of the FCSSP during
manufacturing [3,4]. The constructed 3D finite element model of the
FCCSP is depicted in Fig. 2 and the fabrication process of the FCCSP
is shown in Fig. 3. The modeled warpages are validated by the
experimental measurement data.
Table 1 and Table 2 reveals the comparison of the calculated
displacement results under tensile and thermal loading, respectively,
using four different models, i.e., detailed FEA, TM/FEA-based
effective modeling approach with the assumption of orthotropic and
anisotropic material, and conventional direct ROM method. They
demonstrate that the proposed effective modeling approach can offer
a much more accurate prediction of the thermal-mechanical behavior
of the Cu metal layer than the conventional direct ROM method. It is
also clear to see that the effective anisotropic material assumption for
the Cu metal layer outperforms the effective orthotropic one in the
prediction of its thermal-mechanical behaviors under tensile and
thermal loading. Moreover, the proposed TM/FEA-based effective
modeling approach can be also used to accurately evaluate the processinduced
warpage behavior of the FCCSP during fabrication.
It turns out that the proposed effective modeling approach can not
only give a very good prediction accuracy of the elastic properties of
the complex multi-layer, multi-material circuit substrate and the
process-induced warpage behaviors of the FCCSP during fabrication,
but also greatly ease modeling challenges and improve computational
Using Extra Trees Machine Learning Algorithm to Predict the Asymmetric Warpage Geometry of Panel Level Packaging
發表編號：S25-4時間：14:15 - 14:30
Z. Hsu, B. S. Wang and K.N. Chiang
In recent years, the market demand has resulted in the evolution of electronic components to be thin and multi-functional. Therefore, the related electronic packaging technology has also made considerable progress. Among them, Fan-Out Panel Level Packaging (FO-PLP) is a one of the options that can meet market demand, fan-out refers to the telecommunications connection between the chip and the circuit board through Redistribution Layers and Solder Balls. In addition, the fan-out package also saves many process steps, such as wafer bump, removal of flux, underfill and so on.
In this study, Finite Element Method (FEM) was used to build a 3D model, and the experimentally verified Equivalent CTE was used in the epoxy molding resin material. This is to simplify the curing reaction of the material. The resulting chemical effects such as volume shrinkage have finally successfully established a model for fan-out panel-level packaging. Although FEM can save a lot of time and cost compared with experiments, the results are often different due to human error, and the model must be re-established when the structure size is changed. Therefore, in order to reduce the above situation, this study uses machine learning (ML) to predict the amount of warpage at different packaging scales. First, a training database for fan-out panel-level packaging models of different geometric sizes will be established through the finite element method, and then machine learning will learn through these training databases. After learning, machine learning can quickly predict any geometric size panel Warpage value for level package.
In this study, an ensemble learning algorithm of Extremely Randomized Trees (ET) is used to predict the warpage value of the panel-level package. The algorithm is characterized by its fast operation for large-scale data. The database trains the algorithm, and finally the warpage value of the panel-level package can be predicted.
However, from many literatures, it can be found that the warpage of the fan-out panel level package is an asymmetric shape. There may be many reasons for affecting this result. For example, the thickness of the package epoxy resin is not uniform, and the thickness of the package epoxy resin will be different. There are different shrinkage rates. When the shrinkage rate of one side is different, it will affect the deformation behavior of other places, so there is a chance to produce asymmetric warpage. In addition, in the process of compression molding, the encapsulation epoxy resin is passed through the contact During the curing process, the encapsulated epoxy resin will shrink in volume, which will cause warpage and affect the contact area. Therefore, the heating temperature will be different, and the curing reaction of the encapsulated epoxy resin will be different.
Therefore, this study further explores the causes of asymmetric warpage, such as the influence of the process and so on. At the same time, a three-dimensional model is established by the finite element method to simulate asymmetric warpage caused by process differences.
Multiscale modeling of RDL-first FO-PLP utilizing the process-oriented simulation for warpage prediction
發表編號：S25-5時間：14:30 - 14:45
Chi-Wei Wang, Che-Pei Chang, Guang-Zhi Lin, Hao-Zhou Lin,Chang-Chun. Lee*
With the advantage of high I/O account, thin substrate, and good heterogeneous ability, the fan-out panel-level packaging (FO-PLP) has become a major topic for the future design of novel packaging. Despite of the enlarged area of the panel-level package, the process-induced warpage may cause a serious yielding problem in the subsequent process and assembly for the package. The process-induced warpage would be an urgent issue need to be solved for the FO-PLP. The coefficient of thermal expansion (CTE) mismatch between the materials is the main cause of the warpage. The process temperature for material is also a factor need to be considered. The tremendous cost of time for investigating the effect between materials through experiment is a problem that cannot be ignored. Therefore, the finite element analysis (FEA) is proposed in many researches to overcome the problem of time cost. Another issue is the discontinuous model and warpage after the sawing process from panel to stripe, and stripe to unit package. In this research, a redistribution layer (RDL) first FO-PLP is presented with integrated multiple scale of package model in FEA analysis. The complicated fine RDL and micro-bump is considered with the equivalent materials method and the equivalent stress-free temperature in the process-orientation simulation. The chemical shrinkage of molding underfill (MUF) is also concerned for the material characteristic. The effect of gravity cannot be ignored in the simulation due to the large area of FO-PLP. A rigid plane is constructed on the bottom of model to give a reference plane for the FEA. To give an entire process flow simulation, the saw process of panel to stripe and stripe to package is presented. The saw process must have a multiple scale problem in the FEA. Therefore, the multipoint constraint (MPC) is applied on the boundary of multiple scale model. The estimated warpage from the FEA is verified with measured warpage from experiment for three process steps, panel-level, stripe-level, and single unit package. The measured warpage of a single unit package is found that the position of package on the stripe-level would determine the warpage. The presented methodology for FEA also indicated the same results as the experiment. The warpage error between the simulation and experiment are below 10 %. Accordingly, the presented simulation methodology is validated, which can be utilized to estimate the warpage of FO-PLP. The factor and the material for the process can be further optimized based on the proposed methodology with FEA.
Measurements of Thermally-Induced Warpages and CTEs of Capped-Die Flip-Chip Packages Using Strain Gauges
發表編號：S25-6時間：14:45 - 15:00
Y. W. Wang, Y. S. Chou, and M. Y. Tsai
Heterogeneous integration using a silicon interposer has been increasingly applied to the advanced integrated circuit (IC) package such as 2.5D IC and 3D IC [1-3]. In order to monitor or measure package warpage, the high-cost commercial full-field shadow moiré or 3D-DIC  is usually used for those packages with a metal frame or cap on the top. A relatively low-cost and easy-to-use strain gauge measurement tool is newly proposed here for an alternative method for determining thermally-induced warpages and coefficients of thermal expansion (CTEs) of the capped-die flip-chip packages. The stiffness effect of the thermal interface material (TIM) of the capped-die flip-chip packages is also taken into account. The result suggests that the general back-to-back gauge measurement method on the top and bottom of the specimen would cause significant errors as the TIM inside the capped-die flip-chip package is relatively compliant. This study also further proposes a modified gauge method with a few related strain equations for those cases with compliant TIM to determine their curvatures and CTEs from the gauge measurement. With the good consistency of out-of-plane deformations from moiré and strains data from gauges, the model of the finite element method (FEM) are validated. It is further found from the FEM simulation that the curvatures and CTEs from the modified gauge method are in a good agreement with those from the effective one, and the out-of-plane deformations from the modified gauge method are also closer to the FEM ones than the effective method. As a result, it has been proven by experiments and simulations that the newly-developed modified methods of strain gauges are feasible and workable.
Keywords: Capped-die flip chip package, Thermal Warpage, CTE, Strain Gauge, Shadow Moiré, FEM.
Predict Reliability Life of Wafer Level Packaging Using GPR with Cluster
發表編號：S25-7時間：15:00 - 15:15
Chih Yi Chang
With the advancement of technology and consumers' demand for
electronic products, the technology of electronic packaging is
developing towards smaller sizes, lighter and thinner, and higher
performance. Before entering the market, electronic packaging
products will undergo a series of experiments to test their reliability.
Accelerated thermal cycling (Thermal Cycling Test) is one of the
reliability tests. The disadvantage of experimental detection is that it
takes a lot of time and human capital. This is for today's market
Finite element analysis is used in the simulation analysis of
reliability to improve the development time. A model that has been
verified by real experiments is used to simulate the package to obtain
a reliability life. In this study, ANSYS software will be used to
simulate the reliability of wafers and packages. The stress distribution
of the package is simulated by the application of a thermal cycling load.
The coffin-Mansion formula will be applied to calculate the reliability
life of the package. Bring the equivalent plastic strain generated on the
solder ball into the Coffin-Mansion formula to calculate the reliability
life. In addition, the mesh size is controlled for the most frequently
failed locations in the experiment to obtain more accurate simulation
values for comparison with the real thermal cycle experiment.
The finite element analysis still has its shortcomings. The models
established by different researchers often get different results. In order
to evaluate the reliability analysis of the package through simulation
analysis, professional background knowledge is required. To eliminate
simulation errors and reduce the difficulty of operation, this research
combines the application of artificial intelligence and machine
learning to estimate the reliability of the package body. The data sets
of different sizes and structures will be established by the finite
element model verified by the real thermal cycle test.
This research will apply the Gaussian process regression model for
data training to predict the reliability of the Wafer Level Chip Scale
Packaging (WLCSP). Initially, the simulation results will be compared
with experimental results of thermal cycle loading. With the verified
model, using the same modeling process, we will create a training
database that generates different parameters using FEM. This study
will explore the data effect of the Gaussian regression model on
different kernel functions. The study will also combine K-Means
clustering with an analysis of the time complexity of the Gaussian
regression model based on the amount of data.
The effects of time-dependent inelastic behaviors on the debonding of Cu-polyimide interface
發表編號：S25-8時間：15:15 - 15:30
Chien-Yu Wang, Tz-Cheng Chiu
Multilayered fan-in or fan-out redistribution interconnects are used extensively in advanced package designs for many state-of-the-art high-performance computing and portable applications. A common feature of the various redistribution interconnect designs is the high density of materials interfaces between metal conductors and ceramic or polymeric dielectrics. While the design offers significant benefit in electrical performance, the lack of strong bonds between the dissimilar materials leads to a higher risk in delamination failure under process and reliability test conditions. In the estimations of the mechanical or thermomechanical debond driving forces, an important factor to be considered is the time-dependent inelastic behaviors of metals and polymers. Under thermal or mechanical loading conditions, the energy dissipation in the layered structure is not only through the breaking of the weak chemical bonds at the dissimilar materials interface, but also through the viscoelastic and viscoplastic deformations of the polymer and metals around the interface. From the perspectives of the thermomechanical reliability and structural design of the redistribution interconnect, it is important to evaluate the contributions of the inelastic energy absorptions of the metal and polymer and their effects on the interface debond growth.
In this study, the influences of the viscoelastic behavior of polyimide dielectric and the viscoplastic behavior of Cu metallization on the debonding driving force of the redistribution interconnect is considered. The thermoviscoelastic constitutive behavior of the polyimide thin film was modelled by using a generalized Maxwell model with time-temperature superposition scheme. The viscoplastic behavior the Cu interconnect was considered by using the Anand model. A finite-element based numerical model was developed to evaluate the debonding growth at the Cu-polyimide interface. The model was first applied to evaluate the energy dissipations of the inelastic materials and their influences on the debonding strain energy release rate under either Mode-I or mixed-mode loading conditions. The effects of temperature and loading rate on the partition of energy dissipation through interface separation, viscoelastic and viscoplastic deformations were also discussed. The model was then applied to investigate an interface crack in redistribution interconnect under thermomechanical load. The numerical procedure developed in this study can be implemented to enable a quick evaluation of the interconnect geometry and materials selection for package design and process development.