Oral Sessions

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S12:Advanced Bonding and Interconnect Technology

Oct. 27, 2022 10:00 AM - 12:00 PM

Room: R503
Session chair: Chih Chen, Distinguished Professor, NYCU / Ting-Li Yang, Professor,NYCU

Low Contact Resistivity Cu-Cu/SiO2 hybrid bonds by [111]-oriented nanotwinned Cu
發表編號:S12-1時間:10:00 - 10:30

Invited Speaker

Chih Chen, Professor and Chair, National Yang Ming Chiao Tung University

1. Cu-Cu bonding mechanism and modeling
2. Evolution of interfacial voids and bonding interface.
3. Low-temperature and low-pressure Cu/SiO2 hybrid bonding with low specific contact resistance
4. Reliabilities of the Cu-Cu joints


 
The Effects of Voids on Solder Joint Reliability in First Level Interconnect
發表編號:S12-2時間:10:30 - 10:45

論文編號:AS0038
Sze Pei Lim, Kor Oon Lee, Kiyoshi Oi, Yvonne Yeo, Keith Sweatman, Toshiaki Ono, Kei Murayama, Steven R. Martell, Haruo Shimamoto, and Masahiro Tsuriya

First level interconnect (FLI), e.g. flip-chip attach on substrate or wafer, using solder as the interconnect material is employed extensively in the advance packaging assembly. During the flip-chip die attach process, some voids is often formed in the solder joints. Though in the past this may not be seen as a major issue since the void % is typically less than 10%, but as miniaturization continues, the solder joint of FLI is becoming smaller (<100um bump or Cu pillar size) with tighter pitch and higher density, there is an increasing concern on how the micro voids in the solder joint will affect the package long term reliability even though the void % is not excessive. In addition, a literature search on the web shows that there is limited research done on this subject.

During the first phase of this project, process recipes are defined to consistently build packages with and without solder voids. And the appropriate X-ray inspection tools and CT are used to determine the size and location of the macro and micro voids in the FLI solder joints. It is found that packages built using solder paste typically has more voids in the solder joints compared to packages built using flux and solder sphere process. Subsequently, test packages built in first phase, both with and without micro voids, are subjected to different reliability tests, i.e. thermal cycling test, electromigration test and thermal shock test. Observation from the test results show that test packages with solder voids generally performed worse in solder joint reliability compared to the test packages without solder voids. It is also observed that voids can create current crowding in the area surrounding them and accelerates electromigration degradation, with larger voids having more significant impact from the simulation model. Consistent with other studies, greater electromigration degradation occurred in joints where the orientation of Sn grains which is aligned along the c-axis and parallel to the current flow direction.

This paper will describe the details of the different test conditions, and discussion on the observation from the failure analysis done with cross-sections and EBSD analysis.


 
Low Temperature Fusion Bonding of Glass to Si Using Plasma Activation
發表編號:S12-3時間:10:45 - 11:00

論文編號:TW0022
Ya-Huei Chang

Anodic bonding has been extensively used to permanently bond glass to Si wafer for MEMS (microelectromechanical systems)-based sensor applications. This approach involves the alkali ion migration (such as Li, Na, and K) under high temperature, high pressure, and high voltage. Moreover, similar coefficients of thermal expansion (CTE) are required to bond these two heterogeneous substrates over a wide range of temperature. However, some active or passive devices in MEMS are temperature sensitive and those alkali ions from glass could exhibit undesirable side effects to degrade the device performance when subjected to moisture and heat. The low temperature direct bonding processes for an alkali-free glass wafer to another Si wafer hence has been studied recently. In this talk, Corning Incorporated and D-process Inc. will discuss our joint work about bonding a pristine 300 mm Si wafer to an alkali-free glass wafer (SG3.4) via plasma activation approach without post annealing process.

In this study, SG3.4 glass wafers with CTE match Si wafers, prepared by Corning’s proprietary fusion-draw process and post polishing process were evaluated. The fusion-draw SG3.4 glass with excellent attributes that endows an intimate contact with Si wafer, such as low total thickness variation (TTV, < 3 μm), low warp (<30 μm), and excellent smoothness (Ra<0.3 nm). Additional polishing step during wafer fabrication was added to obtain better attributes: lower TTV, better local flatness (e.g., SFQR <0.2 μm for 26mm x 33mm size), and more consistent cleanness level in terms of particles.

Prior to the low temperature fusion bonding step, both wafer surfaces were subjected to the SC-1 cleaning to eliminate organic contamination at the bonding interface. The process began with the N2 plasma activation on the surfaces of both wafers, followed by the megasonic-assisted DI water rinse at the bonding interface, and then the wafer bonding under the atmosphere at room temperature, the bond propagation initiated by bond pin at the wafer center. The results indicate that the fusion-draw SG3.4/Si bonding pair had the bonding energy greater than the bulk fracture strength, which is similar to the polished SG3.4/Si bonding pair. This result means that plasma activation process not only damages the subsurface to form water reservoir but also helps close the nanogap between the bonding pairs [1]. The bulk fracture strength is an ideal permanent bonding and suffice to survive post-bonding processes, such as grinding and metallization. Furthermore, both bonding pairs exhibit low bubbles or bubble free performance mainly because of optimized SC1 and megasonic DI water clean processes before bonding. In conclusion, this low temperature bonding approach offers a solution for temperature-sensitive device manufacturing processes with Corning glass substrates.


 
Electromigration Reliability of Micro Joints with Au/Pd(P)/Ni(P)/Cu Pads
發表編號:S12-4時間:11:00 - 11:15

論文編號:TW0042
Cheng-Yu Lee, Shun-Cheng Chang, Chih-Tsung Chen, Hung-Cheng Liu, Kuo-Hsing Lan, Pin-Chung Lin, and Cheng-En Ho*

Electroless Ni/electroless Pd/immersion Au (Au/Pd(P)/Ni(P), ENEPIG) trilayer has become one of the most popular surface finishes treating over the Cu pads in the high-end microelectronic components. The Au film serves as oxidation resistance. The underlying Ni(P) film functions as a diffusion barrier, preventing the Cu pads from solder during soldering or a subsequent normal lifetime use. The deposition of a Pd(P) layer between Au and Ni(P) can reduce the galvanic hyper-corrosion in the Ni(P) film resulting from the immersion Au process (black pads [1]), and also act as an efficient diffusion barrier between Au and Ni(P), thereby advancing the solderability and bondability of metallization pads. In soldering applications, the Au/Pd(P) bilayer can be quickly eliminated from the metallization pads, exposing the Ni(P) layer to the molten solder to form intermetallic compounds (IMCs) in-between. A recent study [2] revealed that in a high-temperature storage, the dissolved Pd might migrate from the solder matrix to the solder/Ni(P) interface, where nucleates a dense (Pd,Ni)Sn4 layer that seriously degrades the mechanical reliability of joint interface (termed Pd-embrittlement phenomenon). Since the Au/Pd(P)/Ni(P) trilayer is now being attempted in the micro-joint applications, the electrical and mechanical reliabilities of smaller joints with such a new surface finish technique should be reassessed at the present state, which is the focus of this study.
Experimentally, micro joints with a ENEPIG/Sn/ENEPIG configuration were employed for the electromigration reliability evaluation. The thickness of Au/Pd(P)/Ni(P) trilayer was 0.1 µm, 0.25 µm, and 7 µm, respectively. Upon electron current stressing, a 3.5-amp direct current was applied to the joint structure, producing an average current density of 8 × 103 A/cm2 at the solder/pad contact window and a temperature rise to approximately 158 °C due to Joule heating. The current density distribution in the micro joint upon current stressing was simulated by ANSYS finite element analysis software (Fig. 1a). The composition of IMC species and the corresponding crystal structure before and after current stressing were verified by using electron probe X-ray microanalysis (EPMA) and electron backscatter diffraction (EBSD), respectively.
Fig. 1(b) shows the microstructure of the micro joint after soldering reaction (prior to current stressing). Numerous (Pd,Ni)Sn4 grains (Au: 0.7 at.%; Pd: 4.4 at.%; Ni: 15.4 at.%; Sn: 79.5 at.%) in the solder matrix neighboring the joint interfaces can be noted in this figure. Interestingly, (Pd,Ni)Sn4 gradually migrated to the anode interface during current stressing and translated into a dense NiSn4 layer dissolved with a limited amount of Pd (0.8 at.%) (Fig. 1b–e). Moreover, a remarkable volume expansion was caused by electromigration with the (Pd,Ni)Sn4 translation into NiSn4. This abnormal IMC translation and volume expansion had never been reported previously in the literature and might seriously deteriorate the mechanical/electrical reliability of micro joints. The underlying mechanism associated with this unusual electromigration phenomenon will be presented in this talk. The fundamental study advances our understanding of electromigration behavior and Pd-embrittlement phenomenon, which offers valuable information about the ENEPIG reliability in micro joints.

REFERENCES
[1] K. Suganuma and K. S. Kim, The Root Causes of the “Black pad” Phenomenon and Avoidance Tactics, JOM 60 (2008) 61–65.
[2] C. Y. Lee, S. P. Yang, C. H. Yang, M. K. Lu, T. T. Kuo, and C. E. Ho, Influence of Pd(P) Thickness on the Pd-free Solder Reaction between Eutectic Sn-Ag alloy and Au/Pd(P)/Ni(P)/Cu Multilayer, Surf. Coat. Technol. 395 (2020) 125879.


 
Failure Analysis for Package of Gold Wire Bonding From Practical Case
發表編號:S12-5時間:11:15 - 11:30

論文編號:TW0106
Huang Shan-Yu

Package of Semi-conductor tends to multi-function and minimization in electronic product, the process of package fabrication become to complex and high requirement of environment, such as vibration and cleanness. Industry of semi-conductor has been developed many technologies to inspect quality of package, such as C-SAM, EMMI, FIB, TOF-SIMS. However, these skills were available for identification of single defect normally, e.g. delamination, circuit short/open, contamination. In this paper, we presented a practical experience related to package failure from field, and used traditional equipment (cross-section, oven, SEM) to reveal 2-level failed mechanism of package. In the final conclusion, we considered the failure was strongly related to crevice between gold wire ball & pad and the molding of package accompanied with concave warpage when using 1~1.5 years from field.
Another purpose of this paper is that author would like to draw industry’s attention regarding to standard of wire bonding. In current standard only states the pull strength of wire bonding, but it did not control the structure quality of wire bonding, bad connection of electrical property may result in temporal failure of electronic product and not easy to find out the root cause of failure, this situation may influence different level of product, e.g. military, satellite, medical instrument, air industry, server, personal computer.


 
Edgebond adhesive enhances reliability of low temperature solder in board level assembly
發表編號:S12-6時間:11:30 - 11:45

論文編號:OT0132
Simon Chang, Tae-Kyu Lee, Wei Lee, Karl I. Loh, Edward S. Ibe

Low melting temperature solder, which enables a lower temperature assembly process comes with significant benefits for less warpage and lower component defect risk, but at a cost of a potentially inferior thermal cycling performance due to higher creep rate at elevated temperature environment.
The creep rate can be reduced by dispensing underfill between BGA and PCB to lower thermal stress concentrate on the corner. So the thermal cycling performance would be improved. However, this would increase difficulty when replacing the BGA. For this reason, applying edgebond on the peripheral of the BGA in the assembly process makes it easier to operate on during the rework process. Additionally, it will reduce material consumption dramatically for big BGA.
In this study, we evaluate the reliability of three kinds of low temperature solders. This includes Sn-58Bi solder used in the BGA, 12mm*12mm, assembly without edgebond and Sn-58Bi with edgebond. Comparing the characteristic life cycle number of 3327 cycles with Sn-58Bi solder, the full edgebond BGAs’ do not show any failures up to the test completion at 4050 cycles.
To extend edgebond applications for the strong need of extra-large BGA in today’s electronics industry, we use simulation methods to compare the thermal stress of the solder joints when BGA size increases from 12mm by 12mm to 70mm by 70mm, and up to 100*100mm. This includes the BGA assembly without edgebond and with edgebond. As thermal stress increases, the thermal cycle reliability shortens. From simulated thermal stress results, we can predict the edgebond’s significant benefit for the thermal cycling reliability of extra-large BGA on the board level assembly.


 
Study of Electromigration in Ni/SnAg/Ni Solder Micro-bumps
發表編號:S12-7時間:11:45 - 12:00

論文編號:TW0048
Hung-Chieh Su, Shih-Chi Yang, Chih Chen

Flip-chip solder joints were replaced by solder micro-bumps below 30 µm since the miniaturization of microelectronic devices. Electromigration (EM) have emerged as a critical reliability issue with the reduction of bump height. In this study, electromigration tests were conducted under low temperature of 125 ℃. And the micro-bumps were stressed with two different current density: 5104 A/cm2 and 105 A/cm2. Daisy chain (40 bumps per chain) and Kelvin structure were used for electrical measurement. In order to investigate EM-induced failure at early and later current stressing stages, criteria of resistance raise were set at 5 % and 10 % of initial value. And the competing relation between voiding failure and intermetallic compound (IMC) formation was examined. At the early stages of current stressing (5 % resistance change), failure in micro-bumps was similar under different current density. However, voiding is more significant in current density of 105 A/cm2 at later stages of EM. On the other hand, several bumps with solder transferred into fully IMC joints have been observed in 5104 A/cm2 testing conditions. EM lifetime for these bumps to reach 10 % resistance raise have surpassed 2000 hours. To sum up, we concluded that IMC formation was the dominant failure mechanism at early stages of 125 ℃ electromigration; while the failure mode at later stages of 125 ℃ and 105 A/cm2 electromigration was the combination of voiding failure and IMC formation.


 


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