Oral Sessions

It may be obvious to most that Networks offer ubiquitous connectivity to connect devices. It should be equally obvious, even if one has not realized, that multimedia, with underlying audio and video technologies, offers the most natural connectivity to connect devices and humans. We will examine the future trends of networks, those involving Ethernet, Wi-Fi and Bluetooth in particular, and multimedia, their underlying audio and video technologies, as the world becomes more connected while devices become more intelligent, autonomous, and interactive.
【Bio】
Yee-Wei Huang is currently Spokesperson and Vice President of Realtek Semiconductor Corporation. He has been in the semiconductor industry for 35+ years with experiences ranging from a Fortune 500 company to Silicon Valley start-up, but always focusing on SoC and related IP solutions for the computing, consumer, communications and automotive markets. Yee-Wei has a PhD in Chemical Engineering, MS in both Chemical Engineering and Computer Science, and an MBA degree.

 

1.Introduction & Background
2.Design of High Dk & Ultra low loss laminates
3.Material test of new High Dk & Ultra low loss laminate
4.Summary
5.Question & Answer

 

1.Introduction & Background
2.Design of high Tg low Dk/Df laminates
3.Laminates of Nan Ya for high-speed applications
4.Material test of new halogen free laminate NPG-188HM
5.Summary
6.Question & Answer

 

1. Introduction and Background of AIP.
2. Nan Ya laminates for AIP applications.
3. Material Tests and Reliability Tests
4. Summary

 

1.Introduction and background of the next generation mobile communication
2.Low dielectric laminates design and measurement
3.Nan Ya advanced laminates for millimeter wave and LEO satellite applications
4.Summary

 

1. Introduction
2. Copper Foil Design for High Frequency & High Speed
3. Nan Ya Copper Foil for High Frequency & High Speed Application
4. Summary

 

1.Introduction & Background
2. Comparative 2,6 dimethyl phenol epoxy and DCPD-PN Epoxy and problem of them
3. Design Novel Low Dk/Df Epoxy Resin
4. The Laminate properties of Novel Low Dk/Df Epoxy Resin
5. Summary
6. Question & Answer

 

In view of the common problem by the current metallization on 5G HF materials with poor adhesion and non-uniformity of electroless copper metallization on the sidewall of blind via. We offer an option of metallization process by using Reduced Graphene Oxide. This process (so-called nano scale metallization process) not only could solve the above problems, but also offer advantages of environment-friendly and operating convenient . Furthermore, its unique special properties can enhance the filling performance on copper plating. Meanwhile, rGO is the acid process which is different from the traditional metallization on alkaline state, thus, it can be used as a privilege in enlarging the dry film applications on PCB design, for example: to improve the filling power as well as the good uniformity on track. Upgrade the demand of fine line.

 

With intensive thinking, some new ideas for optimizing the traditional process would be very interested, such as copper pillar process; mSAP process and via filling together with through plating in automotive field. On copper pillar process, using rGO on dry film can balance the current density distribution in the hole of fully panel during electroplating, the yield of pillar can be enhanced. For mSAP and via filling together with through plating , the other idea is using ultra via-filling plating(so-called flash plating) together with RPP afterward, thus, can improve the thickness of uniformity both on track and through hole. And even more to upgrade the fine line device.

 

With the demands especially on 5G era, the design of circuit board are facing new challenges which combine smaller via together with higher I/O density device and larger thermal via for heat transfer in one board. Consequently, in general, the standard copper electroplating filling process is very hard to fulfill the needs, for example: the plating process with good filling power could be satisfied for large via, but it could make over filling for the small, and vice versa. With this respect one of the special property of SF50 was developed to cover this critical demand and meanwhile has been confirmed by several market fields, such as AiP; RF; HPC; mSAP; Optical module and Automotive. Furthermore, XF60 is designed for ultra-thin flash via-filling, specially apply for thermal big via, which can not only eliminate copper thinning process, but also could achieve the finer line demand.

 

In the era of 5G, the needs of HLC PCB market are growing alongside with the quick expansion of infrastructure of base stations. When review the production of traditional electroplating process on HLC board, the throughput are always facing low efficiency and high cost. To overcome those problems the new pulse-reverse plating system – PRT3300 was developed, the main features are using higher current density with lower reverse ratio (lower plating time) could achieve good plating performance, such as: high throwing power, fine crystalline, non-uneven in the hole, longer life-time…etc.

 

1. Cu-Cu bonding mechanism and modeling
2. Evolution of interfacial voids and bonding interface.
3. Low-temperature and low-pressure Cu/SiO2 hybrid bonding with low specific contact resistance
4. Reliabilities of the Cu-Cu joints

 

First level interconnect (FLI), e.g. flip-chip attach on substrate or wafer, using solder as the interconnect material is employed extensively in the advance packaging assembly. During the flip-chip die attach process, some voids is often formed in the solder joints. Though in the past this may not be seen as a major issue since the void % is typically less than 10%, but as miniaturization continues, the solder joint of FLI is becoming smaller (<100um bump or Cu pillar size) with tighter pitch and higher density, there is an increasing concern on how the micro voids in the solder joint will affect the package long term reliability even though the void % is not excessive. In addition, a literature search on the web shows that there is limited research done on this subject.

During the first phase of this project, process recipes are defined to consistently build packages with and without solder voids. And the appropriate X-ray inspection tools and CT are used to determine the size and location of the macro and micro voids in the FLI solder joints. It is found that packages built using solder paste typically has more voids in the solder joints compared to packages built using flux and solder sphere process. Subsequently, test packages built in first phase, both with and without micro voids, are subjected to different reliability tests, i.e. thermal cycling test, electromigration test and thermal shock test. Observation from the test results show that test packages with solder voids generally performed worse in solder joint reliability compared to the test packages without solder voids. It is also observed that voids can create current crowding in the area surrounding them and accelerates electromigration degradation, with larger voids having more significant impact from the simulation model. Consistent with other studies, greater electromigration degradation occurred in joints where the orientation of Sn grains which is aligned along the c-axis and parallel to the current flow direction.

This paper will describe the details of the different test conditions, and discussion on the observation from the failure analysis done with cross-sections and EBSD analysis.

 

Anodic bonding has been extensively used to permanently bond glass to Si wafer for MEMS (microelectromechanical systems)-based sensor applications. This approach involves the alkali ion migration (such as Li, Na, and K) under high temperature, high pressure, and high voltage. Moreover, similar coefficients of thermal expansion (CTE) are required to bond these two heterogeneous substrates over a wide range of temperature. However, some active or passive devices in MEMS are temperature sensitive and those alkali ions from glass could exhibit undesirable side effects to degrade the device performance when subjected to moisture and heat. The low temperature direct bonding processes for an alkali-free glass wafer to another Si wafer hence has been studied recently. In this talk, Corning Incorporated and D-process Inc. will discuss our joint work about bonding a pristine 300 mm Si wafer to an alkali-free glass wafer (SG3.4) via plasma activation approach without post annealing process.

In this study, SG3.4 glass wafers with CTE match Si wafers, prepared by Corning’s proprietary fusion-draw process and post polishing process were evaluated. The fusion-draw SG3.4 glass with excellent attributes that endows an intimate contact with Si wafer, such as low total thickness variation (TTV, < 3 μm), low warp (<30 μm), and excellent smoothness (Ra<0.3 nm). Additional polishing step during wafer fabrication was added to obtain better attributes: lower TTV, better local flatness (e.g., SFQR <0.2 μm for 26mm x 33mm size), and more consistent cleanness level in terms of particles.

Prior to the low temperature fusion bonding step, both wafer surfaces were subjected to the SC-1 cleaning to eliminate organic contamination at the bonding interface. The process began with the N2 plasma activation on the surfaces of both wafers, followed by the megasonic-assisted DI water rinse at the bonding interface, and then the wafer bonding under the atmosphere at room temperature, the bond propagation initiated by bond pin at the wafer center. The results indicate that the fusion-draw SG3.4/Si bonding pair had the bonding energy greater than the bulk fracture strength, which is similar to the polished SG3.4/Si bonding pair. This result means that plasma activation process not only damages the subsurface to form water reservoir but also helps close the nanogap between the bonding pairs [1]. The bulk fracture strength is an ideal permanent bonding and suffice to survive post-bonding processes, such as grinding and metallization. Furthermore, both bonding pairs exhibit low bubbles or bubble free performance mainly because of optimized SC1 and megasonic DI water clean processes before bonding. In conclusion, this low temperature bonding approach offers a solution for temperature-sensitive device manufacturing processes with Corning glass substrates.

 

Electroless Ni/electroless Pd/immersion Au (Au/Pd(P)/Ni(P), ENEPIG) trilayer has become one of the most popular surface finishes treating over the Cu pads in the high-end microelectronic components. The Au film serves as oxidation resistance. The underlying Ni(P) film functions as a diffusion barrier, preventing the Cu pads from solder during soldering or a subsequent normal lifetime use. The deposition of a Pd(P) layer between Au and Ni(P) can reduce the galvanic hyper-corrosion in the Ni(P) film resulting from the immersion Au process (black pads [1]), and also act as an efficient diffusion barrier between Au and Ni(P), thereby advancing the solderability and bondability of metallization pads. In soldering applications, the Au/Pd(P) bilayer can be quickly eliminated from the metallization pads, exposing the Ni(P) layer to the molten solder to form intermetallic compounds (IMCs) in-between. A recent study [2] revealed that in a high-temperature storage, the dissolved Pd might migrate from the solder matrix to the solder/Ni(P) interface, where nucleates a dense (Pd,Ni)Sn4 layer that seriously degrades the mechanical reliability of joint interface (termed Pd-embrittlement phenomenon). Since the Au/Pd(P)/Ni(P) trilayer is now being attempted in the micro-joint applications, the electrical and mechanical reliabilities of smaller joints with such a new surface finish technique should be reassessed at the present state, which is the focus of this study.
Experimentally, micro joints with a ENEPIG/Sn/ENEPIG configuration were employed for the electromigration reliability evaluation. The thickness of Au/Pd(P)/Ni(P) trilayer was 0.1 µm, 0.25 µm, and 7 µm, respectively. Upon electron current stressing, a 3.5-amp direct current was applied to the joint structure, producing an average current density of 8 × 103 A/cm2 at the solder/pad contact window and a temperature rise to approximately 158 °C due to Joule heating. The current density distribution in the micro joint upon current stressing was simulated by ANSYS finite element analysis software (Fig. 1a). The composition of IMC species and the corresponding crystal structure before and after current stressing were verified by using electron probe X-ray microanalysis (EPMA) and electron backscatter diffraction (EBSD), respectively.
Fig. 1(b) shows the microstructure of the micro joint after soldering reaction (prior to current stressing). Numerous (Pd,Ni)Sn4 grains (Au: 0.7 at.%; Pd: 4.4 at.%; Ni: 15.4 at.%; Sn: 79.5 at.%) in the solder matrix neighboring the joint interfaces can be noted in this figure. Interestingly, (Pd,Ni)Sn4 gradually migrated to the anode interface during current stressing and translated into a dense NiSn4 layer dissolved with a limited amount of Pd (0.8 at.%) (Fig. 1b–e). Moreover, a remarkable volume expansion was caused by electromigration with the (Pd,Ni)Sn4 translation into NiSn4. This abnormal IMC translation and volume expansion had never been reported previously in the literature and might seriously deteriorate the mechanical/electrical reliability of micro joints. The underlying mechanism associated with this unusual electromigration phenomenon will be presented in this talk. The fundamental study advances our understanding of electromigration behavior and Pd-embrittlement phenomenon, which offers valuable information about the ENEPIG reliability in micro joints.

REFERENCES
[1] K. Suganuma and K. S. Kim, The Root Causes of the “Black pad” Phenomenon and Avoidance Tactics, JOM 60 (2008) 61–65.
[2] C. Y. Lee, S. P. Yang, C. H. Yang, M. K. Lu, T. T. Kuo, and C. E. Ho, Influence of Pd(P) Thickness on the Pd-free Solder Reaction between Eutectic Sn-Ag alloy and Au/Pd(P)/Ni(P)/Cu Multilayer, Surf. Coat. Technol. 395 (2020) 125879.

 

Package of Semi-conductor tends to multi-function and minimization in electronic product, the process of package fabrication become to complex and high requirement of environment, such as vibration and cleanness. Industry of semi-conductor has been developed many technologies to inspect quality of package, such as C-SAM, EMMI, FIB, TOF-SIMS. However, these skills were available for identification of single defect normally, e.g. delamination, circuit short/open, contamination. In this paper, we presented a practical experience related to package failure from field, and used traditional equipment (cross-section, oven, SEM) to reveal 2-level failed mechanism of package. In the final conclusion, we considered the failure was strongly related to crevice between gold wire ball & pad and the molding of package accompanied with concave warpage when using 1~1.5 years from field.
Another purpose of this paper is that author would like to draw industry’s attention regarding to standard of wire bonding. In current standard only states the pull strength of wire bonding, but it did not control the structure quality of wire bonding, bad connection of electrical property may result in temporal failure of electronic product and not easy to find out the root cause of failure, this situation may influence different level of product, e.g. military, satellite, medical instrument, air industry, server, personal computer.

 

Low melting temperature solder, which enables a lower temperature assembly process comes with significant benefits for less warpage and lower component defect risk, but at a cost of a potentially inferior thermal cycling performance due to higher creep rate at elevated temperature environment.
The creep rate can be reduced by dispensing underfill between BGA and PCB to lower thermal stress concentrate on the corner. So the thermal cycling performance would be improved. However, this would increase difficulty when replacing the BGA. For this reason, applying edgebond on the peripheral of the BGA in the assembly process makes it easier to operate on during the rework process. Additionally, it will reduce material consumption dramatically for big BGA.
In this study, we evaluate the reliability of three kinds of low temperature solders. This includes Sn-58Bi solder used in the BGA, 12mm*12mm, assembly without edgebond and Sn-58Bi with edgebond. Comparing the characteristic life cycle number of 3327 cycles with Sn-58Bi solder, the full edgebond BGAs’ do not show any failures up to the test completion at 4050 cycles.
To extend edgebond applications for the strong need of extra-large BGA in today’s electronics industry, we use simulation methods to compare the thermal stress of the solder joints when BGA size increases from 12mm by 12mm to 70mm by 70mm, and up to 100*100mm. This includes the BGA assembly without edgebond and with edgebond. As thermal stress increases, the thermal cycle reliability shortens. From simulated thermal stress results, we can predict the edgebond’s significant benefit for the thermal cycling reliability of extra-large BGA on the board level assembly.

 

Flip-chip solder joints were replaced by solder micro-bumps below 30 µm since the miniaturization of microelectronic devices. Electromigration (EM) have emerged as a critical reliability issue with the reduction of bump height. In this study, electromigration tests were conducted under low temperature of 125 ℃. And the micro-bumps were stressed with two different current density: 5104 A/cm2 and 105 A/cm2. Daisy chain (40 bumps per chain) and Kelvin structure were used for electrical measurement. In order to investigate EM-induced failure at early and later current stressing stages, criteria of resistance raise were set at 5 % and 10 % of initial value. And the competing relation between voiding failure and intermetallic compound (IMC) formation was examined. At the early stages of current stressing (5 % resistance change), failure in micro-bumps was similar under different current density. However, voiding is more significant in current density of 105 A/cm2 at later stages of EM. On the other hand, several bumps with solder transferred into fully IMC joints have been observed in 5104 A/cm2 testing conditions. EM lifetime for these bumps to reach 10 % resistance raise have surpassed 2000 hours. To sum up, we concluded that IMC formation was the dominant failure mechanism at early stages of 125 ℃ electromigration; while the failure mode at later stages of 125 ℃ and 105 A/cm2 electromigration was the combination of voiding failure and IMC formation.

 

Bringing more powerful processing/computing capabilities closer to every human on the planet, requires significant advancements in Packaging technology to get there. Handling and moving the large central data workloads is especially challenging. This talk will share some of those packaging requirements, and the work in progress to achieve these goals.

 

1.Why edge computing
1.1Edge AI trend
1.2Edge AI benefit
1.3Edge AI and Cloud
1.4The advantage of Kneron solution
2.Kneron Solution in Edge AI
1.FR & Smart door lock
2.ADAS
3.Smart factory
4.Healthy care
5. The challenge of IC package selection

 

Memory bandwidth and energy transfer per bit are the key for edge computing, however the solution beyond Moore’s law is the key to boost edge computing performance.

 

Panelists:
1. Ken Brown, Intel
2. Albert Liu, Kneron
3. Sierra Lai, Winbond

 

Flip chip ball grid alley (FC-BGA) substrate is well known as a package to connect semiconductor and mother board. And these substrates are produced by semi-additive process (SAP). Recently, with the high functionality is required for server and PC, FC-BGA substrate is also rapidly required to be high densification and functionality. Especially, flatness, planer filling and uniformity are necessary for copper plating and suppressing transmission loss and no undercut are necessary for flash etching. To meet these demands, we have developed new copper plating process and flash etching process.

 

There were increasing demand for decreasing transmission loss at mm wavelength application. In order to reduce dielectric loss, it was preferable to use a material with lower Dk/Df compared to conventionally used epoxy film for circuit board and interlayer insulation film. Since the dielectric loss of the epoxy resin film was particularly worse at high temperature and high humidity, a material with stable dielectric loss even at high temperature and high humidity was desired. Thermoplastic resins such as LCP and PPE have been proposed as candidates, but these resins had inferior in process ability and reliability due to their thermoplasticity. We have synthesized a new thermosetting copolymer based on PPE, which showed excellent dielectric properties. And by blending this resin as a base, we have developed a new thermosetting film that has excellent dielectric properties even under high temperature and high humidity conditions, as well as process ability and reliability equivalent to epoxy resin films. In this presentation, I will describe the development and various characteristics of the new film.

 

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Recent advances in packaging technology have led to the establishment of semiconductor packages that require greater integration and geometric efficiency.
Three dimensional system integration using through silicon via (TSV), COC (Chip on Chip), POP (Package on Package) are representative examples of 3D technology.
Passive interposers for 2.5D/2.1D assembly have also been contenders.
In this presentation, a new generation Apic Yamada Molding Technology and solutions are introduced which required for advanced packages
i.e smaller footprint, lower profile with multi-stacking for highest density integration with better thermal performance.

 

We have developed silicon bridged multi chip module, named direct bonded heterogeneous integration (DBHi) package. The DBHi package structure allows direct connection of processor chips through a silicon bridge leading to high-bandwidth and low-power communication for artificial intelligence (AI) workloads. In this talk, assembly technologies and materials to enable reliable DBHi packages and analysis results of thermo-mechanical FEM modeling are presented.

 

Reducing total carbon footprint on data center system; PCB and design strategy assessment; Intel Project Blue Glacier (DC-MHS) Standardization of data center building blocks; High-speed Input/Output(HSIO) Interconnect Solution

 

The ever-increasing need for compute performance is driving a sustained raise in the power and power density of IT equipment and components. This requires a more efficient cooling technology than achieved by air. Liquids are more efficient in dissipating heat than air, and immersion cooling is a liquid cooling technology that is currently gaining an increased interest from the industry. In immersion cooling, the IT equipment is fully submerged in a dielectric liquid that acts as the efficient cooling medium. This session discusses pros and cons with immersion cooling and show cases thermal characterization data of Intel Xeon CPUs in both single-phase and two-phase immersion cooling.

 

Intel System Power Design Validation(SPDV) provide a TCO optimization with system benchmarks. Since Intel implemented Fully Integrated Voltage Regulator (FIVR) that help resolve core noise issue and MB VR was validated by checking V(t) using CPU VR Test Tool (VRTT). This approach include a real system with real CPUs can provide system performance review to achieve customer TCO reduction and power design optimization

 

Intel Probe-On-Pin provides the methodology to measure the Power Delivery Network Characterization with a flexible approach to identify risks from the board level PDN impedance without complicated instrument setups.

 

Intel ® Automatic In-Board Characterization (AIBC) is established for fast, robust, and accurate printed circuit board (PCB) characterization. It can provide comprehensive impedance analysis of thousands signals for the design quality check and PCB manufacture management. The insertion loss can be efficiently analyzed for risk evaluation by comparing with reference platform. This approach can help customers not only verify PCB technologies, such as back drill impact, but also make the right decision based on trade off study between the performance and cost.

 

As society moves to AI, machine learning, 6G, AR/VR, metaverse, autonomous driving, etc., efficient electronic systems with high performance and small form factors are needed.
Traditionally system packaging is divided into levels. Solders and cables are used for the interconnections between different packaging levels. However, if we can reduce the levels of system packaging, we can increase the system performance by reducing the interconnection length. The recent development of chiplets solution has confirmed the trend.
There are two primary directions used in heterogeneous integration for high-performance system integration. One direction is die-to-die integration. Leading companies like TSMC with “SoIC” and Intel with “Foveros” solutions. The other direction is substrate integration. “Substrate integration” integrates a fine line substrate with a coarser line substrate. Examples are 2.5D substrate solution and EMIB by Intel.
Various “die-last integrated substrate” solutions have been developed for the past ten years. For example, Shinko has developed 2.1D and 2.3D solutions, and SiPlus has developed 2.0D and 2.2D solutions. 2.0D structure is thin film RDL directly on a core-less substrate. 2.1D structure is thin film RDL on a cored substrate. In comparison, 2.2D structure is thin film RDL solders to a cored substrate.
Both 2.XD solutions have the advantages of removing solder or/and TXV (TSV or TLV) in the integrated substrate structure. Depending on the requirements of cost, performance, and time to the market, users can select the most suitable 2.XD structure to meet their needs.
In this talk, the development history of the integrated substrate and structure performance comparison of 2.XD integrated substrate will be discussed.

 

To release warpage problems in the step-soldering process, low-temperature Pb-free solders with low cost and high reliability are in demand in the electronic industry. Eutectic Sn-58Bi with high mechanical properties, good wettability, and low melting temperature at 139 °C has drawn great interest in the industry. However, the brittle nature of the Bi-rich phase and microstructure coarsening during thermal aging is a significant issue in employing the Sn-58Bi solder. In the invited talk, CALculation of PHAse Diagram (CALPHAD)-type thermodynamic calculations using the PANDAT software and corresponding key experiments were performed for Sn-Bi-Ga, Sn-Bi-In-Ga, Sn-Bi-Ti, Sn-Bi-Ag, Sn-Bi-Zn, Sn-Bi-Ag-In, and Sn-Bi-Ag-Zn systems. Each system had different advantages, which can meet various applications in the future. Furtherly, the calculated and experimental methods agreed with each other. The relationship with solidification paths, microstructure, and tensile properties was highlighted.

 

SUMMARY
This paper will provide an overview of memory integration evolution trends seen in the industry across different package platform, including memory on PCB, memory on module and memory in package. It also figure out major advantage of Fan-Out package with HBM integration. Finally, package level reliability w/ fan-out HBM integration also be demonstrated.
List of Keywords: Heterogeneous Integration (HI); Artificial Intelligence (AI); High-Performance Computing (HPC); Silicon Interposer; Fan-Out Multi-Chip Module (FO-MCM), Redistribution Layer (RDL); High Bandwidth Memory (HBM)

INTRODUCTION AND MOTIVATION
Leading-edge applications such as Artificial Intelligence (AI), High-Performance Computing (HPC), 5G and IoT are driving demand for increased electronic device performance. On the other hand, the innovation in package technology is also related to an increase in the functional integration of large system-on-chip solutions. Therefore, major focus on heterogeneous integrations have prompted the chip industry to develop a new set of solutions as advanced packaging.
Heterogeneous Integration (HI) by Fan-Out Multi-Chip Module (FO-MCM) solution is driving the “More Than Moore” vision. With higher memory bandwidth requirement, High Bandwidth Memory (HBM) is major candidate to replace traditional GDDR to meet higher data rate for end product application.

TECHNICAL APPROACH
As heterogeneous integration increases, the convergence of die, package, and PCB will increase as well. For example, Fan-Out with memory integration corresponding more IO count requirement for fine-pitch micro-bump and Redistribution Layer (RDL). In other word, it represented to request both finer RDL line and more RDL layer count. Furthermore, the end-user mainly determines package requirement and therefore defines the complexity of both chip and package. It trigger high-density FO-MCM package technology to meet the demand.
High-density FO-MCM incorporates several chips in the same package, including HBM. Traditionally, HBM was mainly found in 2.5D package. In general, standard HBM generation’s product got specific IO pin and serdes location. It is more suitable to approach various Fan-Out package compared to SOC homogeneous integration without specific serdes. Basically, from structure simulation point of view, figure out suitable package platform according to various product design from customer side.

RESULTS AND DISCUSSION
Compared to 2.5D package, FO-MCM package showed lower stress to meet heterogeneous integration packaging requirement. In conclusion, with the construction of FO-MCM package with HBM integration, package level reliability verification is demonstrated successfully by Pre-condition, unbiased highly accelerated stress test (uHAST), high temperature storage (HTS) and thermal cycle test (TCT)

 

As a trend of the advanced package, Embedded Chip Package (ECP) shows a high growth value at semiconductor package field in these years. During ECP substrate manufacturing, a high temperature resistant protection tape (referred as tape hereinafter) is used to enable the chips aligned in the substrate and embedded with a laminating sheet. In the process, the substrate with copper trace patterns and pre-formed cavities is attached to the tape; chips can be packaged in the cavities by laminating a B-stage epoxy sheet on the top surface; and the epoxy sheet flows into the cavities, can be cured and bond to the substrate panel through a high temperature and high-pressure bonding process. Ultimately, the protection tape needs to be peeled off from the substrate easily without residue.

Easy to use, easy removal, low residue and free of contamination after high temperature and high-pressure hot-pressing process are the key requirements for the protection tape used in this embedded die process. High temperature resistance silicone tapes tend to contaminate substrate surface with silicone residue; Other acrylic high temperature resistant tapes, although being predominantly used in the embedded-chip-in-substrate manufacturing process, still suffer from the residue or delamination issues under higher temperature and pressure conditions. To avoid residue, some manufacturers applied an additional buffer layer to prevent tapes from directly contacting with substrates, which adds extra process steps and cost to remove this buffer layer.

In this paper, we discuss a novel non-polar & silicone-free (NPSF) high temperature resistance tape that was developed for the embedded-chip-package-on-substrate manufacturing. This tape demonstrated dramatically reduced residue on substrate surfaces, even after a thermal bonding process up to 225℃ for 2 hours with a high pressure at 430 psi, which enables continuously build redistribution layer (RDL) without bubble or delamination issue. The tape also showed good chemical resistance on various organic solvents. Furthermore, die shifting defect can be controlled to less than 50μm for a chip package size of 1 x 1 mm. With this tape, epoxy material would not bleed out from the cavities under tape protection. Compared to other tapes on the market, 3M NPSF tape gives significant benefits with higher process yield and lower process cost for embedded chip package applications.

 

Higher performance and smaller form factor are always the critical subjects for mobile device in recent years. To meet this demand, System-In-Package (SiP) has become a certain path for innovation and an unstoppable trend for decade. Multi-functional active chips and related passive components can be pre-assembled into a system or sub-system through heterogeneous integration design on laminated substrate. However, as this technology has almost approached its limits, innovation is needed on the corresponding package of SiP for now and the future.
Fan-Out packaging is package with connections fanned-out of the chips surface by using redistribution layer (RDL), enabling more external I/Os, better electrical and thermal performance, precisely RDL can enhance RF performance by accurate impedance control and routing to inductor for impedance matching. In general, Fan-Out technology can be classified into two types, being Chip-First and Chip-Last. Chip-Last Fan-Out take the advantages of lower cost and yield due to the Known-Good-Die (KGD) approach, good compatibility to current packaging infrastructure and easy to integrate heterogeneous elements (Si-chips, non-Si chips and passive devices with different thickness).
In this study, the benefits of evolving SiP with organic substrate to Fan-Out SiP (FOSiP) for new generation mobile RF module with higher performance and smaller form factor has been illustrated. A designed and manufactured FOSiP module with 6 RF devices integrated by several core features and building blocks would be demonstrated, including chip-last RDL manufacturing, carrier system, wafer level assembly and shielding sputtering. First, Fan-Out RDL provides fine line design capability which is better than substrate to enhance the function matching in SiP. Second, carrier system makes thin wafer handling possible. In addition, wafer level assembly delivers high speed and high accuracy SMT and Molding Under Fill (MUF) technique for advanced encapsulation. Finally, shielding sputtering provides an option to apply on specific RF applications.
As results shown, this FOSiP module could have 40% footprint and >50% thickness reduction comparing to conventional SiP module made by organic substrate. Besides, the electrical performance (S-parameter) has been also measured with good agreement as expectation. Through this validation, FOSiP provides a new platform to fulfill the demand from these markets to make the next generation mobile products possible.

 

In recent years, with the development of science and technology, the demand for artificial intelligence (AI), Internet of Things (IoT), 6th generation mobile networks and even autonomous driving applications has increased significantly. These systems all require high-speed signal transmission and a large amount of data processing. Therefore, the multi-channel data transmission and the required frequency must reach the mmWave (~66GHz) level when designing the SiP module. Small size and multi-channel big data transfer requirements, the advanced package such as fan out chip on substrate (FOCoS) is good candidates for high performance computing products.
For mmWave and high-speed design on Fan-out package, impedance characteristic and Redistribution Layer (RDL) trace loss are very important. So, how to get accuracy Dielectric Constant (Dk) and Dissipation Factor (Df) is vital work. The paper is using the Transmission Line (TL) method to get the Dk and Df value. The frequency is up to 60 GHz. Thermal and stress effects on the Fan-out FOCoS package is crucial key. Moisture has obvious effects on Polyimide (PI) Dk/ Df value. This paper also studies the moisture effect on outer and inner RDL layer.
As Fig. 1 shows, the GSG design of 2-layer RDL is used for Dk/ Df extraction. The Cu thickness of the designed RDL1/ RDL2 is 9.3/ 7.3um, PI thickness is 9um, width/ space is 15/ 15 um respectively. Use different line lengths to get de-embedded measurement data for simulation correlation. And then get the broadband PI Dk/ Df value from transmission line method and verify the Dk/ Df value by using T-resonator. There is good correlation between measurement and simulation when applying this Dk/ Df value in the simulation model as Fig. 2. The samples are put on the chambers for oxidization. In this paper, the moisture effect on inner/outer RDL has been demonstrated.

 

• Introduction
• Heterogeneous Integration Package
• Test Chips and Wafer Bumping
• Build-up Package Substrate
• Fine Metal L/S RDL Substrate Fabrication
• Hybrid Substrate Assembly
• Summary

 

The advent and ongoing evolution of internet-enabled mobile devices has continued to drive innovations in the manufacturing and design of technology capable of high-frequency/high-density electronic signal transfer. The combined requirements for both fast, always-on data transmission, and small geometric form-factors can be difficult to satisfy without compromised performance and signal loss.
Selection of materials used in PCB manufacturing is critical for optimum performance of the electronic assembly. Among the primary factors affecting the integrity of high frequency signals is the surface finish applied on PCB copper pads – a need commonly met by technology manufacturers through the electroless nickel immersion gold process, ENIG. However, a well-documented limitation of ENIG is its insertion loss due to the inferior conductivity of nickel over copper, leading to higher conductor losses. Additionally, nickel’s ferromagnetic properties adversely affect circuit performance. The result is an overall reduced performance in high-frequency data transfer rate for ENIG-applied electronics, compared to bare copper.
The selection criteria of surface finish for RF-MW, 5G, high frequency, high density applications, etc. (next generation PCB technologies) involves minimal insertion loss, long shelf life, cost-effective and high reliability. There are few options (EPIG, EPAG, DIG, etc.) available in the market and their pros and cons will be discussed. Moreover, an innovative nickel-less approach involving a proprietary nano-engineered barrier designed to coat copper contacts, finished with an outermost gold layer has shown superior benefits over contemporaries. Detailed insertion loss and reliability testing results will be discussed for the novel Ni-free surface finish.

 

Information technology is dramatically evolving. Ultra high speed application such as fifth-generation mobile communication system(5G) and wireless communication such as GPS and Bluetooth is getting more popular. In near the future, plenty of data traffic will be covered by them. In addition, we expect 6G and satellite communication will be developed and global standards to be set in near the future. We can expect Internet of Things(IoT) which all of devices are connected each other is coming soon. In the future, Internet of Everything(IoE) will also come to the world. At that time, the number of device and traffic speed will dramatically increase.
The Printed Circuit Board (PCB) are required to have high speed signal, be high-density capable and support high-layer counts. In addition, PCB is required to be environmentally friendly.
We introduce our approaches to achieve electronic properties required and to satisfy future application demand.

 

Recently, the TaN thin film resistors, Edge Emitting Laser(EEL) has been rising for Direct Plating Copper (DPC) applications. In the past, to add resistors to ceramic circuit boards, it was necessary to mount the chip resistors on them through the SMT process.

In this paper, we have successfully integrated TaN thin film resistors with the ceramic substrate, which not only reduced the SMT process but also directly integrated circuits on the substrate. The TaN films were deposited by reactive magnetron sputtering. The electrode materials were prepared by Direct Plating Copper (DPC) from Tong Hsing(TH). First, the TaN films resistors were fabricated on the ceramic substrates with various surface roughness. We found that as the roughness of the substrate increased, the sheet resistance also increased for TaN films of the same size and thickness. Next, after the wet process of DPC, it is confirmed whether the roughness on the ceramic substrates and the sheet resistance of TaN have changed significantly. The results found no significant change. Finally, the difference in resistance value was observed by changing the process sequence of the resistance and the electrode. It was found that in the structure where the electrode was fabricated first and then TaN was sputtered, the resistance result was much greater than that in the structure where the electrode was fabricated by sputtering TaN first. The reason for this was speculated that there was an extra contact resistance resulting in an abnormally large resistance value. On the other hand, in the EEL process, the laser diode needs to be mounted on the ceramic substrate with the finished surface. The laser diode is installed on the boundary of the conductor surface, so the side wall of the finished surface needs to be close to vertical, so that the laser can be completely emitted. If the side wall of the conductor is not vertical, it will block part of the laser and cause the light to not be fully emitted. In this article, the process is improved to make the sidewall angle of the surface close to vertical.

 

The proliferation of Artificial Intelligence (AI), big data, 5G, electric vehicles, Internet of Things (IoT), edge computing, High Performance Computing (HPC) and Electric Vehicle (EV) in recent years has necessitated the increased use of electronics. Therefore, the hardware reliability of electronics has received more attention in the industry. With prevalent environmental pollution, air quality will also directly or indirectly influence the life of electronics in indoor and outdoor applications. In general, the hardware reliability of electronics can be easily affected by corrosive gases, moisture, salts, contaminants and particulate matter, especially in outdoor environments with high sulfur-bearing gaseous contamination. Therefore, next generation electronics required not only high performance but also robustness against harsher environments.
A guideline from the International Society for Automation (ISA) standard 71.04-2013 was used to classify the measured corrosion thickness of airborne contaminants into the various severity level rankings by using pure copper and silver coupon exposure. However, some end-customers have asked their Original Design Manufacturers (ODMs) provide the product for passing G2/G3 severity level compliant to 3 years, 5 years, even 10 years through accelerated corrosion methodologies in recent years. Therefore, more and more ODMs have adopted the conformal coating solution. Conformal coating is a popular solution which can protect the board and component to prevent the sulfur corrosion occurrence, especially in edge computing and outdoor infrastructure.
In this research, Flower of Sulfur (FoS) testing method was adopted to validate the anti-corrosion capability of bare copper Printed Circuit Board (PCB) with different conformal coating materials, including typical silicon-based and electronic grade fluorine-based conformal coating, and also benchmarked them against the bare copper PCB without conformal coating. Besides, this corrosion test can be satisfied ANSI/ISA G3 severity level compliant to 5 years exposure. Several analytical methods were used in this research, including, Optical Microscope (OM) Inspection, Coulometric Reduction (CR), Scanning Electron Microscopy (SEM) and Energy-Dispersive X-ray spectroscopy (EDX). Finally, we found that fluorine-based conformal coating from 3M™ Novec™ has robust corrosion resistance that can enhance the specific protectively of outdoor electronics application.

 

Interfacial reaction is a fundamental issue for solder-joint reliability. Solder-joint reliability is influenced by the properties of intermetallic compound (IMC) layers. The mechanical characteristics of solder joints are primary problems in developing electronic packaging, and choosing the right metallization is critical for obtaining dependable solder connections. The Cu-3.28wt.% Ti alloy is named as C1990HP and has good conductivity and mechanical strength. It is suitable to be used as the lead-frame materials. The Sn is the base material for lead-free solder. The interfacial reactions between the pure Sn solder and the C1990HP substrate were investigated by using the solid/liquid reaction couple technique. The C1990HP/Sn/C1990HP sandwich couples were reflowed at 240 to 270°C for 5 to 1200 minutes. Based on the composition analyses by energy dispersive spectrometer attached on scanning electron microscopy (SEM/EDS) and electron probe micro-analyzer (EPMA), the abnormal structure of the Cu6Sn5 phase and the precipitated Ti2Sn3 phase which spread to the molten Sn were found at the Sn/C1990HP interface. The X-ray diffraction (XRD) results were also used to confirm composition analyses. The Ti atoms were dissolved into the molten Sn solder and provided as the heterogeneous nucleation sites for the Cu6Sn5 phase. The Cu6Sn5 phase spalls gradually in most couples with raising time and temperature. The thickness of the IMCs was enhanced when the reaction time and temperature were increased. The total IMC thickness in the C1990HP/Sn/C1990HP sandwich couples can be described by the parabolic law. The IMC growth mechanism was diffusion-controlled. The growth rate constants were increased with the increase in the reaction temperature, and the value of the activation energy is 101 kJ/mole. Additionally, the tensile test was conducted by using the C1990HP/Sn/C1990HP sandwich couples to measure the mechanical strength of the solder joints. The tensile strength and fracture behaviors at 200°C for various aging times were investigated. The result revealed that the tensile strength decreased with the increase in the aging time. However, the tensile strength increased when the reflowing temperature was increased. The tensile strength was decreased due to the change of the failure surface from the solder/solder interface to solder/IMC interface. The ductile fracture mode of the solder-joint reflowed at 240°C was found. When the reflowing temperature was raised to 255°C, both brittle and ductile fracture modes were found. Furthermore, the fracture mode of the solder joint reflowed at 270°C was changed to a brittle type. In this study, the Ti contents in the Cu-based substrate enhanced both the quantity and the detachment of IMC at the interface during the reaction. The C1990HP/Sn/C1990HP interface had good was the ultimate tensile strength (UTS) bonding due to the dissociative strengthening effect of Cu6Sn5 particles. It revealed that the minor content of Ti in the substrate could improve the mechanical properties of the solder joints.

 

Millimeter wave (mm-wave) frequency band (76–81 GHz band) has received widespread attentions in the radar sensor applications as its high resolution, long range, and beam-steering radar characteristics. In the normal life use, the antenna performance might be gradually degraded by the oxidation of conducting materials (e.g., Cu) due to the poor adhesion of oxides to dielectric materials (i.e., substrate), and cause signal integrity problems with short or open circuit. The adoption of surface finish to Cu circuits enables to prevent circuits from oxidation, thereby improving signal integrity and bondability/solderability with electronic components. However, the surface finish coatings would dominate the electrical properties of Cu circuits, particularly in the high-frequency applications, due to the so-called “skin effect’’. The focus of this study is to probe into the effect of surface finish coatings on the antenna signal performance in the mm-wave frequency band.

In this study, the signal performance of antenna (including S-parameters, VSWR, gain, directivity and radiation efficiency) with different surface finishes at 76–81 GHz was investigated through the finite element analysis (FEA) method by using a 3D electromagnetic simulation software (ANSYS-HFSS). Additionally, experimental measurements were conducted by using a vector network analyzer (VNA) and anechoic chambers to characterize the influence of electrical properties arising from different surface finishes, so as to validate the FEA simulation.

The IG surface finish seems to be beneficial to ɛR of the antenna operating at 76–81 GHz. In contrast, a significant degradation of ɛR was caused with adoption of other surface finishes, especially for the ENIG and ENEPIG cases. The degradation can be attributed to poor electrical and magnetic properties of the Ni(P) coating. The results of the present study indicated that the surface finish played an important role on the antenna performance (radiation efficiency) and IG surface finish is beneficial to ɛR of the antenna operating at 76–81 GHz. Detailed analysis on the S-parameters, VSWR, gain, directivity and radiation efficiency in relation to the surface finish coating will be presented in this paper.

 

Performance, time-to-market, and sustainability are the drivers for next generation packaging. Advanced packaging in the form of chiplets is becoming increasingly important, but there is no one solution that meets all needs. For some applications, 3D with hybrid bonding is the solution, but there are many challenges. Challenges such as design, test, assembly, and thermal are discussed. Choices for the future path are discussed.

 

CIS (CMOS Image Sensor) has been widely used in many electronic appliances, including mobile, camera, desktop/laptop computer, security, and some other consumable devices. However, with high image resolution requirements in CIS, some unique Heterogenous Integration Packaging technologies, such as Through Si Via (TSV) or Wafer to Wafer (W2W) Hybrid Bonding are poised here to help enhancing the performance of CIS device applications.
In this presentation, full range types of CIS (such as FSI – Front Side Illumination and BSI – Back Side Illumination), its technology market trends, as well as process flow and challenges will be briefly addressed. By the way, we will also discuss how Applied Materials to offer a full dimension aspect of differentiated manufacturing and metrology equipment solutions, such as PVD, ECD, Etch, CVD, and CMP to full fill Through Si Via (TSV) and Hybrid Bonding technologies which are required for CIS device appliances currently and for the future.

 

Advanced packaging is introducing exciting opportunities to product designers, to drive forward overall product performance in all application segments. Different die types are integrated in optimized manner, with various geometrical configurations (Examples- INFO, CoWoS). Furthermore, die and substrate warpage, die sizes, pitch scaling, are some of key technical challenges that need to be addressed. To bring these advanced packaging opportunities to reality, and enable high design flexibility, special attention needs to be drawn to the die bonding technology to be applied. This talk will be focused on the approaches for well-controlled die bonding, to address the advanced packaging challenges. Thermocompression bonding, with its unique features and control knobs, will be of main focus of the talk, in addition to other emerging bonding technologies.

 

The continuous growth in data generated and computing needs, global network traffic and digital transformation are further driving the adoption of electronics & semiconductor devices. The need for more performing and smarter devices, with increased functionalities, that can address high bandwidth needs, faster speeds, with more efficient power consumption is driving the industry to further develop new and innovative technologies, many of which are enabled by organic substrates. The presentation will focus on global market trends highlighting the major semiconductor industry trends and applications, the increased need and growth of heterogeneous integration and the importance of advanced interconnect solutions.

 

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Demand for more powerful devices requires 3D integration (3DI). However, conventional 3DI processing is limited by the minimum thickness of the silicon wafer and the maximum connection density. In contrast, wafer-on-wafer (WOW) technology with bumpless interconnects can produce stacks of wafers with only a few μm thickness each. [1] During this process wafer warpage can occur, which requires careful monitoring and correction. Usually, alignment markers are placed on each wafer and the deformation confirmed with transmission IR. However, this has several drawbacks, such as low spatial resolution and lack of depth perception. In contrast, confocal Raman spectroscopy is not only non-destructive and contact-free, it also has sub-micrometer resolution in XY plane and can probe semiconductor devices at a certain depth. In this report we describe how confocal Raman imaging can be used in WOW manufacturing.
Edge-trimmed 300 mm DRAM wafers were temporarily bonded on support wafers with temporary adhesive and subsequently thinned with a grinder (DGP8761, DISCO Corp.), first by coarse grinding down to 50–60 µm thickness, and later by fine grinding down to the final thickness. During fine grinding, an automatic feedback sequence was applied to improve the total thickness variation within the 300 mm wafer.
Hyperspectral Raman images were measured in backscattering geometry, with a confocal Raman microscope (Confotec MR250, SOL Instruments). The sample was raster scanned with a motor stage (pitch 4 μm/pixel). Two different lasers, 532 nm and 785 nm, were used in the experiment. The absorption depth of silicon strongly depends on the wavelength in the visible range. Therefore, Raman spectra measured with 532 nm excitation are representative of the structure close to the surface (<1 μm), and Raman spectra measured with 785 nm excitation represent the structure ~5 μm below the surface. The data was analyzed with a custom code written in IgorPro 9 (Wavemetrics).
Figure 1 shows typical Raman spectra at the scribe line, near the center of the wafer. The peak of silicon at 520.7 cm-1 is clearly visible with both excitations. The Raman spectrum measured with 532 nm excitation has a significantly higher fluorescence background, possibly from organic contaminants on the surface.
Raman imaging was performed at the cross-section of two scribe lines, shown in Figure 2(a). The area was chosen because it contains alignment markers from both wafers, upper and lower. Markers located at the upper wafer (indicated with red arrows) are visible in the bright-field image. The cross-shaped marker in the lower wafer, however, is not. Raman images of the intensity of the silicon band are shown in Figure 2(b) (532 nm excitation) and Figure 2(c) (785 nm excitation), respectively. Close to the surface, the scribe-line crossing appears homogeneous, without noticeable difference in contrast. Only markers from the upper wafer appear as dark rectangles, since they block the excitation laser above the silicon. On the contrary, the 785 nm laser probes deeper into the silicon. Some of light reaches the lower wafer marker and is reflected back. Therefore, more Raman signal is created from silicon just above the marker. As a result, the cross-shape of the marker appears in the Raman intensity image. We see that the cross is not centered on the scribe line, due to wafer warping. This result demonstrates that Raman imaging can be used for post-process analysis of wafer warpage. Further, it can be extended to in-line alignment monitoring in WOW manufacturing.
Next, we discuss the Raman shift due to stress in the silicon wafer. Tensile stress shifts the band at 520.7 cm-1 to lower frequencies, while compressive stress leads to higher frequencies. [3] In silicon, near the surface, the shift due to stress is linear and can be described by the following equation [4]:
σ (MPa)=-470 ∆ω (cm^(-1))
Two areas were investigated, one near the center of the wafer and one close to the edge of the wafer. The silicon band was fitted with a single Lorentzian function. Resulting images of the peak position are shown figure 3. The peak position is almost same inside each area, indicating that the stress distribution is locally homogeneous. However, there is a significant difference between the central and the edge areas. Near the edge the peak has shifted ~0.5 cm-1 to lower frequency, which corresponds to a tensile stress of around 235 MPa. On the other hand, near the center, the peak shift is shifted ~0.3 cm-1 to higher frequency, indicating compressive stress of around 141 MPa. This is consistent with wafer warping which occurs during the WOW production process. Detailed correlation analysis between macroscopic warping and microscopic stress observation from Raman scattering is currently underway.
In summary, we investigated the bare silicon structures on a scribe line of a WOW stack with confocal Raman spectroscopy. By changing the excitation wavelengths different depths of the silicon could be measured. In particular, alignment markers in upper and lower wafers were identified simultaneously. We emphasize that the lower marker is only visible in Raman imaging and not in conventional reflective laser scanning. Further, stress distribution in the wafer was visualized, with tensile stress located closer to the edge of the wafer and compressive stress near the center of the wafer. Overall, we demonstrated that confocal Raman imaging provides not only an alternative to transmission IR, but has also several unique advantages, such as higher resolution (< 1 μm), spatially resolved stress distribution in the silicon and 3D imaging capabilities.
References
[1] T. Ohba, T. et al. ”Review of Bumpless Build Cube (BBCube) Using Wafer-on-Wafer (WOW) and Chip-on-Wafer (COW) for Tera-Scale Three-Dimensional Integration (3DI)” Electronics 2022, (11), 236.
[2] Z.-W. Chen et al. ”Ultra-Thinning of 20 nm-Node DRAMs down to 3 μm for Wafer-on-Wafer (WOW) Applications”, 2021, IEEE 71st Electronic Components and Technology Conference (ECTC), 1131.
[3] Z. Iqbal and S. Veprek. “Raman scattering from hydrogenated microcrystalline and amorphous silicon” J. Phys. C: Solid State Phys. 1982, (15), 377.
[4] S.-K. Ryu, et al. "Micro-Raman spectroscopy and analysis of near-surface stresses in silicon around through-silicon vias for three-dimensional interconnects", J. Appl. Phys. 2012, (111), 063513.

 

Understanding of how a chip power performance is impacted by the IR drop of a power delivery network (PDN) enables system operating conditions to be optimized. It allows IR drop impacts to a silicon chip to be identified and fixed early during design phases.
Conventionally, the static and dynamic IR drop analysis for a silicon chip only considers the impact of silicon level power switching gates and metal routing. Such an analysis approach assumes the power supply from voltage regulator module (VRM) to silicon bumps is noise-free and steady, without taking the impacts of system level components into considerations. In our opinions, such an analysis approach is unduly optimistic and causes IR drop signoff to be less reliable.
This paper uses a RISC-V CPU as a case study to illustrate the importance of the external components in an IR drop analysis. The characterization results show that an IR drop of 100mV caused by PDN impedance can result in the targeted clock speed to be reduced by up to 500MHz, which is equivalent to a 50% performance degradation for a 1GHz CPU and is significant. Then, the impact of system level IR drop caused by package, board and VRM to a silicon chip power performance is further shown. A comparison between the conventional Redhawk chip IR drop simulation and our approach is presented. Our modelling methodology, which uses a system-level distributed PDN to increase IR drop analysis accuracy has also been described in detail. It is shown that external factors including package, board and VRM can induce up to 5.7% additional IR drop, or, 0.057V for a 1V power supply. This may cause the targeted clock speed to be reduced by up to 250MHz in the actual silicon. It is demonstrated that the intrinsic resistance and impedance of PDN if not being managed properly could negate the power delivery efficiency and impacting silicon performance. This PDN parasitic effect becomes more prominent when complex activities at silicon edges draw a large amount of current from a power supply.
It is concluded that when signing off the chip power target, we must analyze the PDN at system-level including VRM, board, package, decoupling capacitors, metal routing and power switches in the silicon concurrently.
This approach allows the potential impacts to be identified upfront during design phases and hence, enables the metal routing and power planning to be optimized as needed, enables early discovery of IR drop issues to mitigate costly “down-binning” or worst, re-spinning a silicon to reach the design goals.
This paper is organized into the following sections:
Section I: The DC IR drop and di/dt noise external to the silicon are taken into consideration in chip power analysis.
Section II: The relationship between supply voltage to core clock speed.
Section III: shows the simulation results with different core activities scenarios. It is shown that additional voltage supply noises could encroach the IR drop margin significantly.
Section IV: provides comparisons of the worst-case impacts between analysis with and without external IR drop.

 

System performance is major indicator of a server or workstation. Besides the CPU’s (Central Processing Unit) computing power, the DRAM (Dynamic random-access memory) used in the memory system has a direct impact on the performance. To provide high bandwidth and large memory space, the memory system must operate in a high frequency and the system needs to have the capability to provide as many DRAM slots as possible, respectively. DDR4 (Double Data Rate 4th generation) has been introduced since 2014 and the current Intel server SoC (System-on-Chip) platform support it to be operated in 2933 MT/s (Mega Transfers per Second) with two DRAM modules populated in a channel. Through the capability of supporting multiple channels (e.g., 4 channels), a system can support up to several Tera bytes of memory. From system designer’s point of view, it is vital to test the robustness of the memory system in the EV (Electric Validation) phase. To achieve the goal, Intel not only asks designers to conduct “system test” by running test tools but also provides the “Intel Rank Margining Tool (RMT)” to help designer understand how much eye height and eye width margin exist before the memory system has risk. Since a severe low margin usually leads to a re-spin of the mainboard, the test and debug activity are both critical to ensure the quality of the mainboard design. In this paper, a systematic and scientific debug methodology is proposed and demonstrated to identify an abnormal DDR low margin issue found in an Intel Xeon server platform in an OEM’s (Original Equipment Manufacturer) project. This system is based on an Intel SoC processor, which supports up to 4 channels of DDR4 memory. Several DQ (Data) bits run into low eye height and eye width margin in the RMT test. This implied there would be a potential risk in the memory system which may decrease the robustness or increase the DPM (defeats system per million) after the HVM (High Volume Manufacturing). A proposed DDR debug methodology was adapted to find the root cause. Through the process, several DDR signals (aggressors) had been identified as low margin aggressors by EV engineers and the low margin phenomenon was solved after the design implemented SI (signal integrity) engineer’s suggestions.

 

With the rapid growth of market demand for portable mobile data access devices, the market's requirements for functional integration and packaging complexity are also increasing. At the same time, higher integration, better electrical performance, lower latency, and shorter vertical interconnect requirements are forcing packaging technology to shift from 2D packaging to more advanced 2.5D and 3D packaging designs. To meet these demands, various types of stacked integration technologies are used to integrate multiple chips with different functions into smaller and smaller sizes. Even so, the key factors that affect the packaging challenges are still similar, such as cost-effective manufacturing process, fine pitch interconnect within the micro-behavior, and so on. Specifically, they are in the chip / wafer level miniaturization and integration issues that must be overcome. In the previous paper, we have presented a novel 2.2D solution that used thin film RDL directly bonded to substrate. This 2.2D structure can create a die last integrated substrate with a very flat and rigid base with fine lines on top and coarser lines at the bottom side. This simplifies the integrated substrate structure and further improves the cost and cycle time. However, to meet the rapid design change in the early phase, the simulation tool for underfill analysis is needed to meet the sizes variations from 20x20mm, 40x40mm, and up to 60x60mm.
For the simulation of dispensing behavior, 3D modeling is unavoidable. However, the computing cost will become unaffordable due to the increasing number of bumps and simulation area sizes. In this study, instead of a detail model removing the describing bumps, a novel Equivalent Bump Group (EBG) model with dispenser simulation is introduced to save at least 10 times faster simulation time. The concept of the EBG model is established as a series of weighting factors to modify the contribution of capillary force for the bump effect of capillary-driven underfill flow. A validated case shows that the modeling solution of melt front by EBG model has a good agreement with detailed model for given dispensing passes settings. Moreover, filling time for multi-array package due to the flow pattern controlled by the dispensing design is also investigated by the EBG model. Not only the model provides a better understanding of the physics of the capillary underfill process but also it is proven to be an effective tool for assessing the dispensing conditions.
Keywords—3D CAE modeling, capillary underfill, multi-chip package, micro bumps, dispensing process, Equivalent Bump Group (EBG).

 

For the high reliability and harsh environment applications such as automotive grade MCM (multi-chip modules) or SiP (System in Package), normally requires under-fill to achieve the needed thermal cycles, mechanical shock and vibration reliability. And, these high reliability applications often incorporate high process cost, spending on PCBA flux cleaning, baking, plasma treatment even under-fill capillary time consuming. Despite of above manufacturing process cost, the environmental regulations also challenges the manufacturer to consider more cost effective and environmental manufacturing processes with moderate reliability to meet modern automotive industrial requirements.
This study focus on non-cleaning corner / edge bond reinforcement techniques including material selection, verification, and process design to improve the solder joint reliability of BGAs assemblies to meet the minimum automotive industrial standards (AEC-Q104 Failure Mechanism Based Stress Test Qualification for Multichip Modules). The reliability testing protocol used here, included pre-conditioning (3X multi-reflow) and thermal cycling (-40 to 85 °C). Four adhesive materials (commercially available) were studied with test vehicles including die attachment and BGAs with plans to expand the study on WLCSP BGAs. Process development was also conducted on the edge bond process to determine optimum process conditions.
For edge bond processing, establishing an edge bond that maximizes bond area with proper fillet height without encapsulating the solder balls is key to prevent the process quality issues as well as reliability improvements.

 

Moore’s law was proposed by Gordon Earle Moore, who believes that the number of transistors that can be accommodated on an integrated circuit would double about every 18 months. Since it is approaching the physical limit, Moore’s law is no longer applicable. Packaging technology becomes more important in the post Moore era. The development of electronic packaging can be roughly divided into five stages, namely TO-CAN, DIP (Dual In-line Package), PQFP (Plastic Quad Flat Pack), PBGA (Plastic Ball Grid Array) and the CSP (Chip Scale Package) used in this research. The evolutions are to improve signal transmission speed, storage capacity and the pursuit of higher packaging density. The reliability of packages is very important. Different sizes or manufacturing methods will affect their lifetime. Before these packages are put on the market, they must be tested and experimented to ensure their reliability. However, it will waste a lot of resources and time costs, resulting in less profit.
Finite element analysis is a numerical method that can subdivide a large physical system into a finite number of smaller and simpler elements. The study uses ANSYS to simulate WLCSP (Wafer Level Chip Scale Packaging) through thermal cycling test, and used empirical formulas to estimate the lifetime of solder balls. Also, the mesh size at the maximum DNP (Distance from Neutral Point) is fixed. Make the simulation closer to the experiment results. After the verification of simulation and experimental data, the feasibility of the model is established, thereby saving the huge time cost of packaging testing and experimentation.
However, finite element analysis will produce different results depending on the researcher. In order to avoid this factor and save the time spent in constructing the model, this research introduces artificial intelligence and combines supervised learning and unsupervised learning to estimate the solder ball lifetime. In this study, we used the verified finite element model to obtain different lifetime according to different sizes, and then introduced a large amount of data into AI algorithms to achieve the purpose of quickly predicting the reliability of the package.
The algorithm used in this study is KNN (K-Nearest Neighbors) which can be used for classification and regression, and uses different data numbers, different preprocessing methods, different distance definitions, and different weighting methods to compare the impact of the algorithm’s predictions on the lifetime of our packages. In addition, we combine unsupervised learning methods like K-means to assign data of the same characteristic into each cluster. Try to simplify the complexity of the model, save calculation time and improve the performance of KNN.

Keywords – Wafer Level Package, Finite Element Analysis, Thermal Cycling Test, Reliability Assessment, Artificial Intelligence, Supervised Learning, Unsupervised Learning, K-Nearest Neighbors, K-means

 

Advancement of electronic devices has lead the IC package technology to move toward ultra-fine L/S (< 8 µm) manufacturing. To maintain a good conductive traces integrity, adhesion enhancement system by introducing adhesion promotor molecules is becoming necessary. This work demonstrates the development of a novel adhesion enhancement system which can fulfil all challenges in IC package manufacturing. Organic molecule adhesion promotor introduced in the process to serve as chemical interface bridge, improving significantly the adhesion of substrate laminates on smooth conductive traces at zero line width reduction.

 

High performance computing (HPC) products market is growing to meet current and future demands in business, government, engineering, and science. HPC system can process big data and perform complex calculation at high speeds, where the system also generates a lot of heat continuously. The accumulated heat needs to be managed to avoid affecting the performance and lifetime of HPC system. Therefore, a key design and development of HPC products is to achieve high thermal dissipation in electronic devices. The application of thermal interface materials (TIMs) has been a promising thermal dissipation solution for electronic devices. However, the thermal conductivities of current silicone-based TIMs have been insufficient for future products. Indium is a potential candidate for high heat dissipation needs, because the thermal conductivity of pure indium is around 86 W/mK, which is higher than most silicone-based TIMs. When indium has been applied as a metallic TIM and jointed with the metal of surface finish, there is an intermetallic compound (IMC) reaction at the interface of indium joint. The phase and microstructure of IMC depend on the conditions of thermal treatments and the type of surface finish. The interfacial condition of indium joint is the key to heat dissipation performance. Therefore, the interfacial mechanism and mechanical properties of indium joints have been investigated by applying different surface finishes and various heat treatments in this study.
In this paper, the interfacial reactions of indium jointed with different surface finishes (Au/Ni(V) and Au/Ni) have been investigated, respectively. For studying the interfacial microstructure evolution of the indium joints, they have been treated with different thermal treatments, including reflow process (with 245oC peak temperature) and high temperature storage tests (aging at 100oC, 125oC, and 150oC for 250~1000 hours). The interfacial morphologies of indium joint and the growth behaviors of IMC have been observed, and the interfacial IMC has been identified as Ni28In72 phase. For Au/Ni(V) surface finish, there is rock shaped IMC grains on the surface of Ni(V) layer, and the grain size of IMC increases with the increase of the reflow cycle. In Ni(V) layer, there is a significant In/Ni inter-diffusion reaction after different thermal treatments. For Au/Ni surface finish, the thickness of IMC increases with the increase of aging time and temperature, and the growth rate of IMC increases with the elevating storage temperature. In the results of shear tests, it indicates that increasing IMC thickness has no significant effect on the shear strength of indium joints, and moreover, the failure mode of all indium joints are ductile fracture in the bulk of indium.

 

Electroless Ni-P plating film is known for its capability of being tuned into different chemical, mechanical, electrical and magnetic properties. Therefore, electroless Ni-P plating film, as a low-cost and facile functional surface treatment, has been popularly used in various applications. In electrical industrial field, as the trend to substitute Si chip with wide band gap materials such as SiC or GaN in order to achieve high-function, dense-current = more compact in dimension power modules, related packaging components are requested to endure high temperature environment usage. However, in the case of electroless Ni-P plating film, as phosphorous is over-saturated, IMC= intermetallic compound such as Ni3P precipitates after high temperature aging. As a result, electroless Ni-P plating film becomes fragile after high temperature aging. Fragile electroless Ni-P plating film results in cracks on substrate surface and causes discontinuity in electrical circuit and eventually module breakdown. Considering of Ni’s excellent stability in ambient atmosphere and its multi-functionality, the importance of high-temperature resistant electroless Ni-P plating film development is obvious. In this study, the authors propose an innovative electroless Ni-P plating film whose cracks do not occur after severe environment tests by suppressing phosphorous content and sulfur content.

 

INTRODUCTION
The process rule of a semiconductor is getting smaller and smaller. Accordingly, the size of a via hole or line and space in a package is also becoming smaller. In addition, yearly evolving materials are being tested as substrate materials for the next-generation higher-frequency circuit boards or buildup substrates. The laser micro-hole drilling is a key technology for realizing these demands, and development of lasers with higher output power and shorter wavelengths is being vigorously conducted in order to drill smaller holes at higher speeds. On the other hand, significant challenges exist for drilling small holes in newly emerging materials. Depending on the parameters, drilling can damage the copper film behind the hole or chip the material due to its own brittleness. Therefore, it is necessary to optimize various processing parameters such as laser pulse width, pulse energy, repetition frequency, irradiation time, wavelength, and beam trajectory according to the required design, including hole diameter, aspect ratio, and pitch. Currently, parameter optimization is being done manually in a trial-and-error manner, which could take several months or even years for new materials and designs. The time required for feasibility testing can slow down the design process, and also forces material manufacturers to spend a great deal of time examining what kind of material composition will actually be used.
For this reason, fully automated parameter optimization is desired, which has been hindered by several factors. One of the most significant factor is that post-processing observation and evaluation cannot be done without human intervention, which is a barrier to algorithm-based optimization. To overcome this barrier, we have constructed a cyber-physical system that can perform not only processing, but also micrometer-accurate sample handling, measurements, evaluations, and parameter suggestions in a completely autonomous manner.
EXPERIMENT
Figure 1 shows a picture of a fully-automated laser processing machine named Meister Data Generator (MDG). It works 24 hours, 7 days a week. There are many types of laser oscillators in the system, and laser parameters such as pulse duration or wavelength can be tested under a variety of conditions. For example, grid search to find a suitable parameter set in a 4-dimensional parameter space is an easy task for MDG. If one simply performs a grid search, the machine can test 10,000 drilling conditions in a few hours. Figure 2 shows an example of a result of a laser drilling in glass material with ten thousand different laser parameters taken with a scanning electron microscope.
One of the main features of this system is that all data on processing and measurement, obtained in the process of grid search or algorithm-based parameter optimization, are stored in a unified database. Huge amount of high precision data can be used to make a deep neural network (DNN) to make a laser processing simulator [1]. With the simulator, one can perform an intensive parameter in a cyber space, making this system what one would call a Cyber-Physical System.
Since laser processing is highly nonlinear and results can differ even under the same laser irradiation conditions, it was unclear whether the feedback would work. It is possible to have an artificial intelligence (AI) in the MDG system to perform the actual trial and error. We have found that Bayesian optimization works well for a feedback loop of the laser processing [2]. We can ask MDG to find a good parameter set with a feedback process with the help of AI. It helps to reduces a lead time of a production system.

Another important feature is that this system can be used as a cloud service via a browser. Once the sample to be tested is set in MDG, the processing-measuring cycle and parameter optimization can be performed as a web service. The user who accesses the system from anywhere in the world does not have to care about where it is located in the same way as the case for supercomputers. The user will not even need to care if MDG really executes an experiment or it uses a simulator to respond in the future when the simulators mature. This system works not only for the parameter finding for laser micro-processing but also for an experiment to figure out physics behind the laser processing phenomena, which would reveal the extremes of processing.
Reference
[1] Shuntaro Tani, and Yohei Kobayashi, "Ultrafast laser ablation simulator using deep neural networks," Sci Rep 12, 5837 (2022).
[2] Keiichi Bamoto, Haruyuki Sakurai, Shuntaro Tani, and Yohei Kobayashi, "Autonomous parameter optimization for femtosecond laser micro-drilling," Optics Express vol. 30, pp. 243-254 (2022)

 

IC chips and electrical components are electrically connected by fine-pitched conductive lines, micro-vias and PTHs (plating through hoes) among multi-layered PCBs with high density interconnect (HDI) inside of various electrical devices. Nowadays, along with requests of modules to be more dimensionally compact, lots of material and manufacturing improvement effort has been made. One of the major change is the diameter of micro-via has been dramatically decreased. In late 20th century, the diameter of micro-via was 125 μm. And now, the diameter is under 10 μm, which is approximately 1/13 of the old-time size. On the other hand, void occurrence in micro-vias has been reported for decades. As voids seldom cause fatal damages in big-diameter micro-via, the consciousness toward voids in micro-via was not high. However, recently micro-vias encounter reliability problems such as delamination and cracks. We can assume the impact of voids become more obvious in nowadays tiny-diameter micro-vias. Moreover, together with the trend to substitute IC chip material from Si to wide band gap semiconductor such as SiC and GaN, which can work at higher temperature (> 200 ℃) than conventional Si, micro-via, as an essential electrical component, is facing challenge of its reliability in severer environment. In this study, the authors investigated possible related content = nickel, whose ion is added in conventional plating solution for stress releasing purpose in electroless Cu plated layer, that may have influence on void formation. Morphological and ingredient difference between voids in conventional electroless copper plating layer with Ni ion additive and a new electroless copper plating layer called “OPC-FLET”, which is without Ni ion additive is analyzed and compared.

 

EUV lithography drives the miniaturization of semiconductors for higher integration, and semiconductor manufacturing is in transition from two-dimensional (2D) to three-dimensional (3D) structures [1], which plays a crucial role in supporting packaging for edge computing such as Internet-of-Things (loT). 3D power scaling enables higher integration without reducing the size of transistors by arranging them vertically instead of horizontally. One of the important processes in manufacturing 3D structured semiconductors is the formation of films on sidewalls of trenches and holes. Such films are often deposited by plasma enhanced chemical vapor deposition (PECVD) [2]. Due to the gas decomposition by plasma, PECVD method archives a high deposition rate of good quality films at low temperature, which is an advantage over other deposition methods such as atomic layer deposition (ALD) [3]. However, this does not fully meet the actual manufacturing requirements. For instance, SiO2 dielectric films deposited by PECVD usually have low coverage and poor film quality on sidewall of trenches and holes compared to films on surface. Ion impact is one of the most important factors contributing to improving step coverage and film quality in trenches and holes. One parameter that characterized ion impact is the ion energy distribution function (IEDF) and ion angular distribution (IADF) [4,5]. There are strong needs for low temperature deposition in trenches and holes. Here, we show a plasma CVD technology for solving such issues on sidewall deposition in trenches and holes, based on experimental and simulation results.
Our PECVD experiments clearly demonstrated that amplitude modulated discharge PECVD is an excellent technology for solving such issues on sidewall deposition in trenches and holes [6, 12]. Details on the experiments will be described in the proceedings paper and presented at the conference.
To reveal the mechanism leading to the excellent experimental results. We carried out particle-in-cell/Monte Carlo collision (PIC-MCC) simulation [12]. We investigated plasma parameters using 1d3v PIC-MCC simulation in the capacitively coupled discharge Ar plasma at 10 mTorr with and without amplitude modulation. AM frequency f_AM is varied from 1 kHz to 1 MHz to evaluate the AM frequency dependence on the plasma parameters. The electron density, axial electric field E_z, and IEDF vary with time in AM discharges. The variation of electron density decreases with increasing the AM frequency above 10 kHz, one of the peak energy of IEDF decreases with increasing the AM frequency above 1 MHz, and one of E_z shows no significant difference with respect to the AM frequency. In other words, our simulation shows that the amplitude modulation frequency of amplitude modulated discharge PECVD is a good tuning knob to control IEDF and IAFD. The behavior of ions inside the microstructure of substrates such as holes and trenches, and the AM frequency dependence on electron energy distribution function (EEDF) which is related to radical generation rates will be reported at the conference.
In short, we show a plasma CVD technology for solving such issues on sidewall deposition in trenches and holes, based on experimental and simulation results.

 

In this paper, we deposited highly (111)-oriented nano-twinned Cu as the Cu joints, and the joints were bonded at 250 ℃. To study voids evolution more precisely, we developed the new characterization method by plan-view images of focused ion beam (FIB).
Furthermore, we analyzed the interfacial voids of the Cu joints after annealing. We studied the quantitative analysis of the interfacial voids distribution, and we also examined the kinetics study of voids evolution. We classified the evolution of interfacial voids during the thermal compression bonding (TCB) process into three different stages, including plastic deformation, creep deformation, and void ripening. The interface and voids evolution are impacted by grain boundary and lattice diffusion.
On the basis of our experimental data, we found that voids ripen significantly at early stage of the TCB process, which was owing to higher diffusivity of grain boundary diffusion. However, if the bonding interface was eliminated during the TCB process, the sizes of interfacial voids do not change obviously due to lower diffusivity of lattice diffusion.

 

Advanced Interconnection Stress Testing Mechanism

 

Immersion tin is a final finish which is widely used in the printed circuit board (PCB) industry. It provides a cost competitive surface protection with excellent corrosion resistance, and has the capability for multiple reflow soldering. The tin is deposited on copper by immersion reaction with a typical layer thickness in a range of 0.8 – 1.2 µm. On top of the tin layer an oxide layer is formed, which can influence the properties of the final finish. During the assembly process an intermetallic compound (IMC) grows connecting the copper substrate and the tin of the solder alloy. The growth of the IMC is a complex function of temp and time.
The IMC formation and well distributed pure tin remnants is a key factor for reliable solder joint. With increased aging of the immersion tin deposit, the role of the tin oxide layer becomes of particular interest for aged or reflowed immersion tin layers and regulator for properties of solder and immersion tin in liquidus process at reflow step. Due to the IMC formation the tin layer is facing increasing internal which is potentially released via the oxide covered surface. The quality and thickness of the tin oxide layer impacts the solder wetting performance of the final finish, the risk of whisker formation and in particular the stability and appearance of the layer after reflow aging.
In this paper an introduction on typical failure mechanisms and root causes for solder wetting defects of immersion tin will be given. Such defects can become e.g. visible as solder dewetting in certain areas of the soldered pads or as partial shiny appearance of the tin surface after reflow cycles. The mechanisms introduced in this paper are supported by correlating tests to identify the possible root causes for the solder wetting defects.
In this study various methods are presented which allow the determination of the tin oxide layer thickness. Different factors are investigated on their impact on the tin oxide layer formation and various approaches are studied in order to modify the thickness of the oxide layer. Based on the test results the properties of the tin oxide layer could be identified as critical parameter for the immersion tin layer performance. The application of a dedicated post-treatment solution can modify the tin oxide layer and, in this way, improve the performance of the immersion tin deposit in regard to appearance and solderability. This is confirmed by optical inspection, different types of solderability tests as well as whisker evaluation.

 

As communication technology transits to 5G generation, it drives the development of AI ecology, such as new smart factories, smart warehousing, smart real-time monitoring platforms and other applications, which also tests the quality detection capability of high-speed channels in the data center printed circuit board(PCB), such as the loss of high-speed channels capability of measurement and impedance measurement and segmental analysis.
The PCB manufacturers usually check the impedance by time-domain reflectometer (TDR) and channel loss of the PCB by vector network analyzer(VNA) according to the IPC standards [1] [2]. It is critical to have multi-zone analysis ability of the TDR impedance profile in the design and manufacture accurate perspective, such as how to identify correctly break out with the narrow trace routing, plating through hole (PTH) via and main routing impedance.
The conventional TDR instruments are widely used by PCB manufacturers in the impedance measurement, but the resolution and accuracy are influenced by cables, probes or fixtures which has a huge impact on multi-zone impedance analysis.
In this paper, VNA with the calibration technology is proposed to not only analyze TDR impedance with multi-zones but also measure channel loss for quality risk assessment. The precision coaxial air lines are adopted as primary reference standards to assure impedance measurement verification, and traceability mechanism is conducted into the comparison experimental of impedance resolution capabilities for accurate and robust measurement. [3-5]
In the comparison experimental of impedance resolution capabilities, qualitative analysis method is conducted to verify cables of different lengths, and different instruments in the same type of VNA and TDR in order to compare the analytical capabilities. Through the experimental results, VNA demonstrates the better analytical ability because of the calibration technology and robustness by small error variation between different instruments. In addition, VNA has the advantage of providing measurement information of channel loss for quality risk assessment.
The scope in this study is focused on the analysis of the changes in the measurement values of the instrument itself. Therefore, future research will address the difference between the measured values of the VNA instrument and the TDR instrument, the parameter setting changes of the VNA to convert the TDR value, and the variation of different device under test (DUT).
REFERENCES
[1] IPC-TM-650 TEST METHODS MANUAL “Characteristic Impedance of Lines on Printed Boards by TDR” ，IPC ASSOCIATION CONNECTING ELECTRONICS INDUSTRIES
[2] IPC-TM-650 TEST METHODS MANUAL “Measuring High Frequency Signal Loss and Propagation on Printed Boards with Frequency Domain Methods”，IPC ASSOCIATION CONNECTING ELECTRONICS INDUSTRIES
[3] B.O. Weinschel, “Air-filled coaxial lines as absolute impedance standards,” Microwave J., pp. 47–50, vo, 7, Apr. 1964.
[4] I.A. Harris and R.E. Spinney, “The realization of high-frequency impedance standards using air-spaced coaxial lines,” IEEE Trans. Instrum. Meas., vol. 13, no. 4, pp. 265–272, 1964.
[5] International Vocabulary of Basic and General Terms Used in Metrology, 2nd Ed. International Organization for Standardization, Geneva, Switzerland, 1993.
[6] L. Essen and K.D. Froome, “The refractive indices and dielectric constants of air and its principal constituents at 24,000 Mc/s,” Proc. Phys. Soc., vol. 64B, no. 10, 1951, pp. 862–875.
[7] K.H. Wong, “Using precision coaxial air dielectric transmission lines as calibration and verification standards,” Microwave J., vol. 31, pp. 83–92, Dec. 1988.

 

This paper presents the determination of dielectric constant (DK) and dissipation factor (DF) of a printed circuit board (PCB) by microstrip structure for its easy fabrication as a test coupon in manufacturing, as well as the mature empirical formulas to extract DK and DF from measured data of microstrip propagation constant γ. The ring and straight-line resonators (SLRs) are utilized to measure γ and different results are observed. The explanations of the data deviations with the modified approaches are proposed in this paper to improve the consistency. With the measured γ, the DK extraction can be extracted by an iterative process where the propagation constant γ is calculated based on an initial DK using the microstrip empirical formulas with dispersion effects, and the process is continued until reaching the acceptable error between calculated value and the measured γ. The DF is computed based on the solved DK with conductor loss. The proposed method is examined by the PCB material of RO3003 using probing technique up to the fifth order of resonant modes in the frequency range of 18 GHz to 90 GHz.

 

Copper has been a widely used conductor and metallization material in form of electroplated or sputtered
films, as well as cold-rolled lead frames or clad sheets, in microelectronics and MEMS devices due to the
combination of low resistivity and low power loss. However, surface copper oxide formation during
fabrication or assembly processes increases electrical/thermal resistivities or even causes device malfunction.
The common methods to analyze surface oxide layer are XPS, TEM and XRD (X-ray diffraction) techniques.
Unsatisfactorily, sample preparation for those analytical means is time-consuming. Relevant instruments
are sophisticated and costly. In this study, coulometric reduction method was adopted to investigate the
phase and thickness of surface oxide layer of sputtered copper. The samples subjected to citric acid wash
and room temperature storage were investigated. Repeated reduction tests in NaOH solution was also carried
out to explore the very early state of the copper surface. According to the reduction potential ranging from -
0.62 to 0.65 V, the initial oxide formed in NaOH solution was CuO with the thickness of around 1.1~1.2 nm.

 

Insertion loss of a testing vehicle is widely referred for the material estimation, the differential pair and single-end striplines are generally employed for the high-speed digital applications. In addition to the matte side, the shiny side with the surface treatment of the inner layer is the critical issue for the insertion-loss improvement. In general, the inner-layer roughness is determined by the cross-section scanning electron or optical microscope photo with the manual defining of the average line. Therefore, the tolerance is produced from personal operation or gage repeatability and reproducibility (Gage R and R). In this study, a numerical morphology algorithm is proposed for automatically detecting the roughness of the striplines. Basing on the algorithm and operating flow, the detected Rz and Rq values of the copper-foil roughness are applied in 3D simulation tool for the insertion-loss validation and comparison.
Keywords: differential, single-end, cross-section, numerical morphology, and insertion loss.

 

Portable electronics have become one of the main applications for semiconductor devices, thereby the drop
test has been regarded as an important evaluation for electronics reliability. Direct Cu bonding is considered
an ideal way to achieve inter-chip vertical connections for TSV (through silicon via), due to size
miniaturization and low electrical resistance. In this study, drop testing of packages comprising sputtered
copper on Si chips joined with electroplated copper on Al2O3 substrates assembled by thermal compression
bonding was performed. Experimental results show that pre-treatment using Xenon flash can be
accommploshed in a very short time, but a remarable improvement of drop resistance for direct-copper bonds
can be achieved. As for the package with no flash pre-treatment and those treated with 20 time exposure, the
drop life was less than 5 times. Notably, packages subjected to flash exposures of 5, 10, 15 times all
withstanded drop test for over 30 times, which were much stronger than those bonded using SAC307 solder
pastes (drop life was 10 times or below). The enhancement in joint reliability can be ascribed to the increase
in compressive surface residual stresses, which accelerate diffusion of copper atoms, and reinforce direct Cu
bonding. This finding is very crucial for 3D packaging for portable usages.