Oral Sessions

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Three-dimensionally stacked semiconductor packages are becoming necessary for high-performance electronic devices. Hybrid bonding has attracted attention as a technology for stacking semiconductor chips at high density. This is called hybrid bonding because it bonds the copper pads and the insulating silicon oxide. Hybrid bonding, which uses organic resin as the insulating material instead of inorganic insulating materials such as silicon oxide, has features such as being less susceptible to the effects of nano scale particles attached to the semiconductor chip surface, being able to bond at low temperatures, and having small residual stress.
Polyimide has excellent heat resistance, electrical insulation properties, and mechanical properties, and is promising candidate for an organic resin suitable for hybrid bonding. In order to apply it to hybrid bonding, we designed a low-elasticity photosensitive polyimide and a low-CTE low-temperature curable polyimide, and used them to examine the bonding conditions. As a result, we found that the elastic modulus at the time of bonding and the surface activation treatment affected the adhesiveness. It is thought that the plasma activation treatment increases the number of hydrophilic groups on the polyimide surface, and hydrogen bonds are induced between the polyimide surfaces during low-temperature bonding, and the subsequent post-annealing treatment causes a chemical reaction to bond the polyimide.
Furthermore, they discovered polishing conditions that could expose approximately 1-10 nm of copper using the CMP process on a silicon wafer coated with copper pads and polyimide. As a result of polyimide-polyimide bonding tests under low-temperature conditions using these conditions, they confirmed void-free bonding at process conditions of 250°C or less.

 

With the social implementation of AI and high-speed mobile communication systems, semiconductor technology for processing and transmitting large volumes of information at high speed is becoming increasingly important. To achieve this, chiplet, which connect multiple semiconductors side-by-side on an interposer, and mounting processes that stack them in three dimensions are attracting attention, and interconnect technology, which connects copper electrodes to each other, is key. Traditionally, C4 (Controlled Collapse Chip Connection) and copper pillar bumps with Sn-Ag solder have been used for interconnects, but the difficulty in forming solder bumps with a diameter of <10 µm and the risk of bridging between electrodes due to their liquid nature during bonding make it difficult to apply them to narrow pitch connections of 20 µm or less.
　In recent years, there have been many reports of mass production and development of hybrid bonding as a technology for narrow-pitch connections. Hybrid bonding directly connects copper electrodes to each other, enabling ultra-fine pitch interconnects with electrode pitches of several µm to sub-µm, but it has the problem of requiring high temperatures of 350-400 ℃ to perform copper-copper diffusion bonding. When the bonding temperature is high, thermal stress and warpage increase, causing not only misalignment during bonding and cracking within the chip, but also degradation of heat-sensitive semiconductors such as memory, so it is required to keep the bonding temperature below 250 ℃.
　In this study, we developed a copper surface treatment solution that activates the copper electrode surface to enable copper-copper bonding at 200 ℃. Copper nanoparticles are formed on the copper electrode surface by applying this liquid to the bonding surface of the copper electrode followed by heat treatment at <200 ℃. The lower melting point of the nanoparticles makes it possible to proceed with copper-copper bonding starting from the nanoparticles at relatively low temperatures. Currently working on application to fine pitch interconnections.
　This presentation will introduce the properties of the copper surface treatment solution and show copper-copper bonding results after copper electrode surface treatment, demonstrating its applicability to low-temperature hybrid bonding.

 

As IT technology continues to develop, the demand for high-performance and multifunctional semiconductor devices is steadily increasing. Therefore, interest in semiconductor packaging technology has increased, and there is a lot of research and development taking place. In particular, heterogeneous integration (HI) technology, which is a technology that packages various types of chips such as logic and memory into one package system, is currently in the spotlight [1]. Especially, copper/dielectric hybrid bonding technology is very attractive because it is excellent in implementing fine pitch structures [2]. In this study, Cu bonding was performed at a low-temperature of 200 °C or less by preventing oxidation of Cu using Au passivation nanolayer. Au is hardly oxidized, has the advantage of excellent electrical conductivity, and is possible of dual damascene process using CMP (chemical mechanical polishing) [3].
Cu wafer was prepared by sputtering 50 nm Ti and 1 µm Cu on an 8-inch SiO2/Si wafer. Then, Au was deposited on Cu by evaporating and sputtering, respectively. After heating at temperatures of 25, 100, 150, and 200 °C for 1 hour to determine the degree of diffusion between Au and Cu, diffusion activation energy value was calculated in the Arrhenius equation using the element ratio of the surface through XPS (x-ray photoelectron spectroscopy) analysis. Based on our study of the diffusion mechanism between Au and Cu, it was observed that Au deposited by evaporation diffused more rapidly from the Au nanolayer into the Cu layer. Conversely, Au deposited by sputtering diffused more rapidly from the Cu layer into the Au nanolayer.
The microstructure of Au nanolayers deposited by evaporation and sputtering was observed using transmission electron microscopy (TEM). The evaporated Au nanolayer exhibited a porous and agglomerated structure, preventing the observation of the Au lattice. In contrast, the sputtered Au nanolayer formed a uniform thin film and the preferred orientation of both Au and Cu were identified as (111) by XRD (x-ray diffraction).
After bonding with Au nanolayer, both Au and Cu were detected at the bonding interface due to the sufficiently diffusion of Au into Cu, and the detailed analysis will be presented. In addition, the thickness (2, 5, and 12 nm) effect of Au nanolayer was evaluated using the sputtered Au. The bonding strength of the interface was measured using shear strength measurements by dicing the bonded specimen with 2 mm × 2 mm chip, and contact resistance in the daisy chain structure was also assessed.

References
[1] Li. T, Hou. J, Yan. J, Liu. R, Yang. H, Sun. Z, Chiplet heterogeneous integration technology-status and challenges, Electronics, 9(4) (2020) 670.
[2] J. H. Lau, State of art of Cu-Cu hybrid bonding, IEEE Transactions on Components, Packaging and Manufacturing Technology, 14(3) (2024) 376-396.
[3] G. Karbasian, P. J. Fay, H. G. Xing, A.O. Orlov, G. L. Snider, Chemical mechanical planarization of gold, Journal of Vacuum Science & Technology A, 32 (2014) 021402.

 

Three-dimensional chip stacking with vertical interconnections through silicon (3-D integration) offers an effective route to increase the level of integration in system packaging. A widely adopted bonding scheme for 3-D integration is adding a thin Sn layer on top of Cu pillar bumps as the bonding layer. For the Cu/Sn/Cu bonding structure, one should note that metallurgical reactions between Cu and molten Sn are very aggressive, which leads to the formation of Cu-Sn intermetallic compounds (IMCs) typically accompanied by the generation of Kirkendall voids. The underlayer with an amorphous structure is beneficial for preventing diffusion reactions in the absence of grain boundaries. As a result, thin film metallic glasses (TFMGs) have been studied and found to be excellent diffusion barriers in integrated circuits applications. Many published studies have investigated whether Zr-based TFMG can prevent Cu/Sn interaction. Conversely, Cu-Sn intermetallic compounds proved very beneficial for mechanical properties in bonding strength.
This study explored the possibility of employing a bi-layer diffusion barrier of sputter-deposited TFMG/Cu in a Cu/Sn/Cu bonding structure. To fabricate a 3-D integration bonding structure of Cu/TFMG/Cu/Sn/Cu/TFMG/Cu, we processed the upper and lower sides of the joints separately through a silicon substrate electroplated copper layer. We deposited three layers of Zr-TFMG, Cu, and Sn. Each upper and lower side sample was joined with a thermo-compression bonding process. Using SEM, we examined the bonding morphology of the bonded samples to investigate material interaction across the barrier and evaluate the performance of the barrier.
Our materials analysis revealed that the bi-layer barrier served effectively as a diffusion barrier and prevented full-scale materials interaction for temperatures higher than 300℃. For the bi-layer barrier, the thin Cu layer reacted with the Sn to form a thin Cu6Sn5 IMC, which suppressed IMC and void formation, providing a promising route to improve thermal stability and a much better performance than the single barrier samples. These results from this evaluation enable a better understanding of the employment of a bi-layer of TFMG/Cu as a diffusion barrier in a Cu/Sn/Cu bonding structure toward the thermo-compression bonding process. This study also served as valuable information for 3D-IC product design, especially when applying a diffusion barrier layer underneath the Cu/Sn/Cu bonding structure is required.

 

As semiconductor technology pursues higher I/O density and faster signal transmission speed, Fan-out Panel Level Packaging (FOPLP) has become one of the most important advanced packaging technologies. There are two types of FOPLP. One is Molding-first and the other is RDL-first. Molding-first process improves heat dissipation during packaging and enhances package stability by prioritizing filling process. However, the drag force generated during filling and thermal expansion due to temperature differences may cause warpage and die shift. This study primarily utilizes panels from Molding-first process for simulation and analysis to predict die shift and warpage. Moreover, a comprehensive research process for conducting die shift analysis with Moldex3D software will be developed.
Additionally, due to the high hygroscopicity of Epoxy Molding Compound (EMC), environmental humidity influences the product during storage or transportation, potentially leading to failure. Therefore, this study will also examine the combined effects of temperature and humidity to observe moisture diffusion and moisture-thermal stress distribution for Molding-first FOPLP.
Die shift analyses are categorized into two effects, which are the fluid-flow effect and the warpage effect. This study utilizes elastic analysis to investigate die shift because the drag force during filling process does not cause die slipping. The simulation results indicate that the warpage effect induces a more significant die shift and the farther away from center of the panel, the greater die shift. To consider the softening behavior of mold tape, Young's modulus was measured at different temperatures by Nano-indenter. Comparing Young's modulus of mold tape at room temperature to that at high temperatures results in five times larger die shift values induced by the fluid-flow effect. Additionally, considering Young's modulus of mold tape at high temperatures brings the simulation results closer to experimental values, with the total die shift increasing by 48% compared to only considering material properties at room temperature.
Regarding the study of hygroscopicity, conduct thermal mechanical analysis (TMA) experiments with EMC materials to observe the strain variations under different EMC types and temperatures. According to the experimental results, strain decreases under different high-temperature conditions due to moisture removal. Additionally, strain variation shows different magnitudes for different temperature settings and types of EMC material used. Following moisture experiments, the moisture expansion coefficient of EMC materials is calculated and used to analyze moisture diffusion and moisture-thermal stress within the package.
In the hygroscopicity simulation, a single package structure of FOPLP is constructed and simulated at Moisture Sensitivity Level (MSL) test. The simulation results indicate that the maximum von Mises stress is at the interfaces between die and EMC due to inconsistent Coefficient of Thermal Expansion (CTE) and Coefficient of Moisture Expansion (CME), especially at the corner of the die. Furthermore, temperature has the most significant effect due to the larger thermal strain. It was also found that decreasing EMC thickness and increasing die thickness effectively reduce stress, thus improving product reliability.

 

The surface morphology and stacking topography are significant indicators in high density redistribution layers (RDL) and stacking via layout for advanced packaging development. With the rapid development of AI and HPC, products with fine-pitch RDL (Line/Space < 2/2um) and increasing layers of via stacking have become key drivers of technology innovation. To achieve goals of high density RDL development, the surface morphology characterization of Polyimide (PI) material is needed to develop, and which is important for process capability control. Atomic Force Microscope (AFM) is a common and reliable methodology to be used in measuring surface roughness values of a small area, but it is challenging to measure the entire 12-inch wafer surface performance due to throughput concern. In this paper, we demonstrate a novel metrology called “Advanced Optical Metrology” (AOM) which can provide the whole 12-inch wafer surface morphology information within one minute of measuring time. The AOM can be used to observe the details of the surface variation of wafer. The experimental results of this paper show that each curing cyclization rate of PI exhibits different surface profile. In addition, the lower cyclization rates of PI film after surface treatment are significantly affected than higher cyclization rates under the same chemical treatment conditions. Overall, the demo cases of this paper demonstrate the versatility and usefulness of AOM in analyzing the surface properties of different materials and providing valuable insights into the surface properties of materials, which can be used to optimize surface treatment and curing conditions for various applications.