Poster Sessions

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Poster Session(PCB)

Oct. 27, 2022 15:10 PM - 15:40 PM

Room: Foyer area
Seung-Mo Kang

Fifth-generation (5G) mobile communication technology is an irreplaceable to realize the hyper-connected society which can be realized by diverse electronic devices such as internet of things (IoTs), virtual reality (VR), augmented reality (AR) and RADAR (Radio Detection And Ranging) system for autonomous automobile. Among various required technologies for applying the 5G technology successfully in commercial, high performance printed circuit board (PCB) have been highly considered as a key factor to reduce delay and error rate of signal after sending and receiving signal. To satisfy the industrial standard, a dielectric constant (Dk) and a dissipation factor (Df) of dielectrics in PCB for 5G communication should be around or lower than 3.0 and 0.002 each at frequency higher than 5 GHz.Recently, many materials have been proposed as low Dk/Df dielectrics for 5G PCB, for example, liquid crystal polymer (LCP), modified polyimide (MPI), polyphenylene ether (PPE), and polytetrafluoroethylene (PTFE). However, significant issues such as low adhesion to copper, high water absorption, improper thermal properties, and bad processability are still remained to utilized above materials for 5G PCB in real device. Here, we present thermosetting siloxane resin with low Dk/Df value in microwave frequencies range, low water absorption, and preferable thermal properties. Thermally cured siloxane material represents low Dk/Df value of 2.86/0.002 (@10GHz). Also, Dk/Df value of the siloxane material was stably maintained in diverse humid condition (85℃/85 R.H.%, 25℃/100 R.H.%) due to low water absorption which is 0.047% in ASTM standard. Furthermore, the siloxane material showed high flame resistance, high thermal degradation temperature, and low coefficient of thermal expansion (CTE) with no glass transition which is required properties for PCB. To fabricate PCB substrate, the siloxane resin was impregnated into a quartz cloth (Shinetsu SQX). The fabricated quartz reinforced siloxane (QRS) substrate showed Dk/Df value of 3.0/0.0015 (@10 GHz), originated from low Dk/Df value of the siloxane material and quartz cloth (Dk/Df : 3.7/0.001 @10 GHz). Finally, 5G PCB was successfully demonstrated by using siloxane based double sides copper clad laminates (CCLs) which is composed of the QRS substrate as a dielectric and Cu foil of low surface roughness as a conductor. The structure of PCB was designed as a microstrip line structure by patterning upper Cu layer of the CCLs as a transmission line with impedance of 50Ω, which lower Cu layer was used as ground. The transmission loss of the fabricated PCB was measured in frequency range from 0 to 60 GHz.


Jimmy Hsu, Ryan Chang, Xiaoning Ye, Thonas Su, Zoe Liu

In this paper, a novel and effective approach by the innovative customized PCB surface printing was proposed to reduce far-end crosstalk (FEXT) in multiple microstrip lines. A new type of solder mask with higher dielectric constant up to 8, instead of the conventional one with around 4, was developed for PCB surface printing. The test coupons with the proposed customized solder mask are built and validated, and the measured FEXT was significantly reduced. The design strategy with the optimized structures was clearly addressed, and this innovation can effectively enhance the microstrip electrical performance for high-speed application.


Oscar Chuang , Min-hsiung Liang, Wan-Chen Yang, Frank Yang, Amanda Chou, Peter Hsieh, Johnny Chao, Jimmy Wang

In order to verify the electrical performance of functional integrated circuit including 5th generation wireless system, WiFi 6, radio frequency chip and image chip before advanced packaging, the probe card solution has been demonstrated. The probe structure, IC carrier board and printed circuit board have been assembled to make the probe card system. According to the design of integrated circuit with more functional demand, the number of probe structure in the probe card system has been increased. The total force from increasing probe structure will enhance the deformation of probe card system. Therefore, the gap between probe structure and wafer has been changed and impacted each probe mark. In addition, this phenomenon will influence the uniformity of probe mark and the accuracy of electrical performance. This studying will use the Binarization and mechanical simulation method to enhance the uniformity of probe structure. Before mechanical simulation, Python OpenCV has been applied in image thresholding for binarization to realize the difference of each probe mark in the whole probe card system. From the results of image thresholding, the specific area of probe mark situation is different from others. After understanding the distribution of each probe mark, mechanical simulation has been demonstrated to optimate the design of probe structure. Finally, from this work flow, the probe system has been improved including more than 80% uniformity of total probe mark and enhanced electrical performance and stability of measurement.


Ming-Xian Cai, Hsing-Jen Lee, Ching-Biau Tzeng

Bio-power is a kind of renewable energy made of materials derived from microorganisms. Because the power generation method is to use microorganisms to perform chemical action to generate weak voltage and current, and energy management IC is used to store and convert energy, so that the weak voltage can be boosted to a voltage range of 3.3V ~ 5V for general applications. These energy sources can be used as small power sources, such as toilet lights or the power supply of the sender of IoT integrated information nodes. For the bio-power generation power supply, it is boosted to the application voltage and then connected to the BMS system. At this time, the static power consumption also needs to be maintained at the static current of the BMS IC. Therefore, the overall static power consumption can be maintained within the ideal value of the IC specification by the circuit design method with less parasitic effect. At the condition of small amount of the biomass power generation, the unnecessary consumption would be reduced and the ideal power generation efficiency would be achieved by this process. In this paper, the layout design of the circuit board used for bio-power generation is taken as the starting point, and the parasitic capacitance and static current on the circuit board are improved by the most appropriate layout method, and the results are analyzed by implementing this circuit and simulating with the simulation software. In this circuit design, the existing ICs on the market are used for energy harvesting of bio-power generation. In the design of the actual power supply circuit, appropriate layout techniques are used to maintain the quiescent current at the ideal value of the IC itself, and to improve the parasitic capacitance on the circuit board. Finally, a series analysis of the power supply is carried out to confirm the layout process proposed in this paper. The proposed method can keep the quiescent current of this circuit within the ideal range so that the error does not exceed 10%.


Yu Ming

In the past, the most commonly used solder material in electronic manufacturing was Sn-37Pb alloy, which has low cost. However,In 2006, the main purpose of RoHS (The Restriction of Hazardous Substances in Electrical and Electronic Equipment) is to promulgate laws and regulations such as the concentration of restricted substances in electrical and electronic products. And then develop the choice of lead-free solder, and the eutectic Sn-Ag-Cu alloy has has excellent mechanical strength, ductility, creep resistance and fatigue properties, so it is currently the most potential lead-free In the solder system, among many alloy systems, the Sn3Ag0.5Cu eutectic alloy is currently the most widely used. Solder joints are used in microelectronics to provide electrical, thermal and mechanical continuity in electronic devices and assemblies. The overall overall performance of devices and circuits depends on the strength and reliability of the solder joints. Although Sn-Ag-Cu solder is used in the packaging of electronic products in many fields, due to the fatigue failure of solder joints in electronic modules due to temperature cycling, the increased aging of Cu makes the interface IMC brittle, which is more prominent in SAC solders; The proportion of SAC solder in the lead-free SAC connector is increasing, which affects the reliability of electronic equipment. In reality, IC products are more and more developed and applied in more fields. For example, mobile vehicle products not only face high temperature environment but also increase the possibility of collision during transportation, while Sn-Ag solder has excellent wettability. Thermal fatigue. Although the absence of copper component can reduce the cumulative aging and gradual failure of the interfacial metal co-compound (IMC), the stress concentration is induced when the silver concentration is higher than 3.5 wt%, which adversely affects the mechanical properties. The electronic package product of this study is a ball grid array (BGA) package, in which the solder material is reworkable and self-aligned, so it is the most important component for assembling wiring and components. The reliability of the solder ball joint will determine the life of the ball grid array. The investigated solder ball material is Sn-Ag solder, drop reliability test is performed, and nine-point bend test is performed to obtain strain. Finally, the life distribution of the product is obtained by Weibull analysis, and the thickness and composition ratio of each material component are observed by IMC measurement and EDX, and finally which solder should be used for the product.


Tina Yang

When High-speed Input/Output (HSIO) data rate increases, such as PCI Express Gen5 with 32GT/s or Gen6 with 64GT/s, channel design is very challenging and complex because the routing length reduction in printed circuit board (PCB) by the exponential loss increase in high frequency which decays the signal quality. Traditional FR4 PCB material may can’t meet the design target for high-speed interface. Designers need to spend more time on advanced material study and routing optimization to meet the system design requirement. How to validate the end-to-end whole channel design from transmitter, mother board, connector, riser, and end device is very important to ensure the signal quality. However, the conventional measurement has repeatability and robustness issues by the hand-made probe, and accuracy concern by reflection impact due to the stub from the probing point close to the chip, instead of the device end. In this paper, a fast and accurate end-to-end channel electrical characterization methodology was proposed and developed for design and manufacture quality check. On the transmitter side, the interposer with four-layer PCB stackup was designed to replace the initial chipset and these terminals with mechanical guide pins on the top side were implemented for high-frequency probes up to 40GHz. These probes with the customized mechanical guide pins design can be easily aligned and connected to the specific signals. The probe and interposer effects, including the trace routing and via, can be removed by advanced 2x-Thru methodology, to significantly simplify calibration and de-embedding procedures. The 2x-through symmetric structures was implemented and the electrical characteristics of 1x through is mathematically calculated for the de-embedding. As the end-device, various standard load boards, including Open Compute Project (OCP), Enterprise and Data Center SSD Form Factor (EDSFF) and Card Electromechanical Specification (CEM) were developed and implemented for the testing. It is convenient for designers to characterize the channel and debug efficiently over the oscilloscope in the time domain response or Vector Network Analyzer (VNA) in the frequency. This end-to-end methodology was validated intensively for the accuracy, robustness, and efficiency, including test fixture quality, de-embedding methodology, time domain impedance profile, frequency domain response, Gage repeatability and reproducibility etc. This proposed technique can assist designers to verify the end-to-end signal quality easily with the minimum effort and conduct the channel design assessment efficiently, including PCB design, material selection, manufacture process, connector, cable solution and etc. Furthermore, designers could optimize the channel design and implement the cost-effective solution based on the cost verse performance trade-off study.


Jimmy Hsu, Gary Hung, Jim Tseng, Brian Ho, Lemon Lin, Thonas Su

When Intel data center platform transits generation by generation, Central Processing Unit (CPU) pin pitch is reduced to accommodate thousands of signals by more high-speed Input/Output (HSIO) and more Double Data Rate (DDR) channels. Meanwhile, PCI-Express revision is transiting from 16 GT/s to 32 GT/s data rate and the lower loss interconnect budget is required to achieve higher operation frequency. To meet the tighter electrical requirement, designers need to adopt some advanced PCB process technologies and there are a lot of challenges to PCB design and suppliers manufacture quality management. PCB material is from low loss to ultra-low loss to extend routing length for PCIe Express 32 GT/s, and PCB cost increases significantly by material upgrade with smooth copper foil. PCB layer count increases from 12 layers to 16 layers for more signals routing, and board thickness increases from 76mil to 100mil. The via drill size is reduced from 10 mil to 8 mil for more signal fan-out in CPU area and this leads higher drill aspect ratio from 8 to 12.5 by smaller via drill size in thick board. The back drill process is required to mitigate the resonance by the via stub for high-frequency application. Meanwhile, PCB manufacture variation need to be considered by more suppliers’ competition for cost-effective solution. Intel ® Automatic In-Board Characterization (AIBC) is developed for fast, robust, and accurate PCB characterization and enabled for the testing services of Intel data center customers support to validate design and manufacture quality for board robustness. AIBC can benefit layout and manufacture quality check, channel loss risk assessment, manage PCB manufacture variation and verify PCB technologies impact, such as back drill and PCB material selection. The early visibility by AIBC finding is critical to improve design quality by reducing down-range risk and improve product robustness. Some examples are shown to demonstrate ABC design quality check and identify customer design issues efficiently, such as abnormal higher insertion loss by missed back drill design and higher impedance by routing close to the mechanical holes. Customers also adopted AIBC to manage PCB fabrication quality and identifies suppliers’ quality inconsistencies, including the area or layer dependency within one sample, samples variation by one PCB shop, and difference among various PCB shops. In this paper, the loss variation by two PCB shops is more than 20%. This PCB manufacture impact is critical to the electrical performance, and this variation induces more challenges in the system validation. According to this AIBC findings, designers can identify these issues efficiently to improve PCB manufacture quality, such as oxide treatment, lamination, PCB etching etc. Through full scope in-board impedance and loss measurement, AIBC is very helpful to capture the design defects for improvement of the next PCB re-spin for customer time-to-market. Meanwhile, AIBC can benefit customers to manage PCB fabrication quality, such as PCB drilling, etching quality and manufacture variation, and identifies PCB suppliers’ quality inconsistencies in products.


Kevin Hong

Bottom termination component (BTC) is a leadless component with bottom side termination for thermal dissipation on ground pad and signal transmission on isolated pads. There is an exposed die attached pad to contact with the metal pads of printed circuit board (PCB). However, there are many process challenges in board assembly process and solder joint inspection due to hidden ground and signal pads in the package structure. The major difficulty is excessive void formation on bottom side solder joints by bad outgassing without stand-off gap post pick-and-place on solder paste. This paper discusses how to minimize the void size between BTC termination and PCB pads to meet package vendor’s or client’s void criteria definition by four variables: (1) PCB via configuration with plugged, unplugged, half-plugged type, (2) PCB via array design by matrix/random placement, (3) PCB via position close to pad edge (4) stencil opening ratio. The best combination is found based on Design of Experiment (DoE) result and the BTC void formation in PCB thermal pad is kept significantly < 25%. The primary task of SMT process is how to get stable void rate between BTC termination and PCB thermal pad. The client is concerned about the voids in thermal pad that may compromise the reliability of solder joints. When the voids exceed the client’s criteria, it leads to extra time and cost for reworking these defects. In this void issue from the client’s complaint, obviously the large void is the same as random via design. From via distribution in another product, it is designed as matrix/symmetry position and the void becomes smaller than random via design. Because the client does not modify the via design from random to matrix type, other effective methods need to be explored to minimize the void rate in thermal pad and search for a win-win solution with the client. BTC void DoE plan is considered for PCB pad design, PCB via filling with plugged condition, SMT process parameters, and BTC termination design. DoE control items are defined in the plan to monitor the void performance and eliminate the possible noises for DoE result. - Component for DoE: BTC package with Via-on-Pad (VOP) design. - PCB Via Configuration: Via half-plugged by solder ink from PCB bottom side. - Reflow Preheat Time: This factor defines the sufficient time under certain preheat tempera-ture to vaporize excessive volatile organic com-pound (VOC) from the flux, hence to reduce the void rate during reflow soldering. - Stencil Opening Ratio: To find out the most appropriate aperture for adequate solder paste coverage to reducing the void rate. - Stencil Aperture in Thermal Pad: To create either air escaping passage or keep out area from via to avoid solder from flowing into the via hole that might create voids. This is the key DoE factor that needs further investigation. This void investigation indicates a significant effect on four variables (1) via configuration with plugged, unplugged, half-plugged type, (2) via array design by matrix/random placement, (3) via position close to pad edge/corner, and (4) stencil opening ratio. The best combination is found from the variables above for better outgassing result and significantly reduces void formation down to less than 25%. It is recommended to keep stencil opening ratio at about 60% and decide whether to print solder paste on via or not by via configuration (half-plugged/unplugged). Matrix placement is proposed for via array with via position close to pad edge/corner in PCB layout design. If strict void rate (<25% or less) is required for a special application of product, PCB pad layout with different via types (solder ink plugged, resin filled, copper capped) is a key for a successful low void formation.


CHENXI XIE,HAICHENG ZOU,JIE GUO,MEIJUAN KUANG

With the invention and development of PCB and FPC, Rigid-flexible (referred as R-F in the following text) board was designed and realized naturally by engineers. We combine flex and rigid materials by laminating with certain stack-up, these materials contain FCCL, CVL, LF PP, CCL and so on. Due to the great difference of CTE (coefficient of thermal expansion) between these materials, the defect of hole copper crack happens frequently during thermal cycle test (as known as TCT) for R-F board. Normally rigid PCB can survive after more than 1000 cycles of TCT test with condition of -40℃/15min to 125℃/15min, however the R-F board will fail within 600~700 cycles. After a change of resistance more than 10% detected, engineers will find out the crack of copper mainly in the contact surface of LF PP and PI layer of FCCL, which is resulted from the obvious difference between CTE of LF PP and PI. This paper mainly starts from three factors, different kinds of PP with different CTE, through hole copper thickness and copper elongation, to research how the factors affect the life of R-F board enduring TCT with DOE method. Through this paper, we hope to give some suggestions to engineers who wants to enhance the cycles of TCT test of R-F board in PCB industry.


CHENXI XIE JIE GUO MEIJUAN KUANG

As the high-end rigid-flex board (R-F board) widely used in the automotive electronics, industry control systems and smart medical products, the reliability of R-F board is becoming more and more important. FCCL is a very important material in the stack up of R-F board. As we know, PI has excellent heat resistance, electric property, mechanical property and flame retardancy, because of the amazing physical property and chemical property, PI is broadly applied in all kinds of situation. However, the biggest disadvantage of PI is that it is easy to absorb moisture. When the R-F board undergoes reflow of SMT, the water in PI will turn into water vapor at high temperature, resulting in the delamination between PI and copper foil because of rapidly increased stress of water vapor. In this situation, not only it brings serious economic loss but also affect efficiency. This study is aiming at the root of delamination of FCCL. We mainly study the type of PI, design of grid copper, water absorption and baking before SMT with DOE analysis, to find how these factors affect the delamination of FCCL. We hope this paper can provide reference for engineers in the industry of PCB and SMT.


Yu-Han Chen

Sn plating on copper pads is a common metallization for IC substrates. However, interfacial reactions between Cu and Sn induces IMC formation and exhaustion of Sn and Cu, which give rise to poor solderability and degraded join strength. The most common techniques to analyze above metallization surfaces are XPS (X-ray photoelectron spectroscopy) and TEM (Transmission electron microscopy). However, sophisticated instruments are required and sample preparation is time-consuming. In this study, coulometric dissolution method was developed to investigate Sn coating on copper pads. Identification and thickness estimation of the structural phases along the through thickness are main topics. Experimental results verify that the thicknesses of Sn and Cu of the as-deposited and high temperature aged samples, as well as the intermetallic compounds between them, can be efficiently and precisely analyzed.


Fu-Hsiang Chang, Kuo-Chi Chang, Hsiao-Chuan Wang

The semiconductor factory itself has a large amount of flammable and explosive gases, chemicals, etc., which have great harm to the safety of production equipment and personal safety. When the abnormal system fails, it may lead to inevitable gas leakage risks. In the past, many fire and explosion accidents and toxic gases happened in Taiwan. The leakage has seriously affected the operation of Taiwan's semiconductor supply chain. Especially now that Taiwan has become the world's leading semiconductor manufacturing center, it is particularly important. Therefore, the importance of monitoring and early warning of flammable and explosive dangerous gases is extremely important. Now that the era of Industry 4.0 has arrived, the intelligent production of semiconductor companies is undoubtedly an inevitable trend. Only by realizing the intelligence of explosion-proof gas monitoring and early warning can meet and adapt to the production needs of the era of Industry 4.0. ESP32 is a family of low-cost, low-power single-chip microcontrollers that integrate Wi-Fi and dual-mode Bluetooth. It uses the Tensilica Xtensa LX6 microprocessor and includes dual-core and single-core variants with built-in antenna switches, RF converters, power amplifiers, low noise receiver amplifiers, filters and power management modules. This research takes ESP32 as the core, and the system is designed according to the scene of the semiconductor factory. This intelligent explosion-proof gas monitoring and early warning system includes: sensing and detection system; data communication system; data processing system; comprehensive systems such as early warning, semiconductor factory engineers can real-time monitoring of dangerous gases, according to the intuitive results such as data and status generated by the system, and the trend of gas status changes can be obtained by analyzing the data and status information stored in the database, and the potential threats of safety hazards can be stifled in the cradle as soon as possible. So as to ensure the safety, continuity, and efficiency of the real-time wafer production process.


Chao-Ting Chu, Dai-Shih Ting, Lin-Zhi Xuan

This paper proposes adaptive PD controller in digital solar cell buck converter. The solar cells and other alternative energy sources has increased, so it is necessary to seek energy conversion optimization of energy sources. There are several research topic of DC-to-DC converter circuits for battery charging have been utilized with buck converter. In the solar buck converter, the problems of illumination change, solar panel dust, and aging circuit are a nonlinear problem, so a digital controller needs to be designed to solve. The determination of the PD controller constants depends on the system characteristics. This paper proposes adaptive PD controller that adjusts the control value according to the output target real time, so that the system can be optimized to overcome nonlinear problems such as various illumination changes, solar panel dust, and aging buck circuit. In the experimental results, the input voltage and the load change for target output voltage which adaptive control laws can be adjusted real time to achieve the robustness of the system.


Chao-Ting Chu, Lin-Zhi Xuan, Dai-Shih Ting

This paper proposes solar cell boost converter with adaptive PD controller. Solar power generation systems use sunlight to generate electricity mainly. The same technology as integrated circuits that collect electric energy through solar panel to achieve boost converter. In this paper, we proposed an adaptive PD controller adjusts adaptive law real time that according to load changes and light changes. The adaptive laws used Lyaponuv function to derivation that ensure the convergence stable. Experimental results are shown output voltage stable when input voltage and load change. Therefore, the adaptive laws adjusted real time to achieve the robustness in the system.


Kaung-Wei Chuang; Jin-Tiao Liu; Chun-Cheng Hsu

FFUs are mature devices in the industry that are widely used in 1K or ISO6 cleanrooms or better. USI started installing FFUs to SMT equipment in 2016, with the purpose to keep inside of equipment clean with active purifying air circulation. Verification has shown that it helped prevent production errors and malfunctioning parts in the mounters due to dust accumulation, maintain placement accuracy, extend the interval for the next part replacement and reduce internal temperature. 143 of these units are installed at present. Based on the existing FFU applications, this paper aims to propose an iFFU (Intelligent Fan Filter Unit) system design where sensors and dedicated differential pressure probe developed in house provide accurate monitoring values for determination of filter status and timing of replacement. Data are transmitted to remote monitoring system for a complete package of IoT-based intelligent system for automatic tracing, analysis and prediction.

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