Poster Sessions

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Oct. 26th - Poster Session(PCB)

Oct. 26, 2023 15:30 PM - 15:50 PM

Room: Foyer area, 5F

展示攤位：PS2_1 (論文編號：TW0004)

The Design Guideline of Four-Axis SCARA Robotic Arm Development

Kuang-Wei Chuang

A complete SCARA robotic arm design is presented in this study. The system development and verification are performed step by step from theoretic analysis to selection of key parts. For the kinematics of horizontal articulation, the geometric functions are determined based on Jacobian planar linkage motion studies and the coordinate systems of human body joints and robotic arm are incorporated in the L- and R-arm coordinate systems for characteristics analysis, while a model is built to be incorporated in the design to verify the motion characteristics and spatial limits of SCARA arm using 2D and 3D integrated numeric method, as to facilitate the application of robotic arm in the configuration at every coordinate point and path in automated equipment for better system operation accuracy and reliability.

展示攤位：PS2_2 (論文編號：TW0005)

Research on Direct Labor Training Programs and Certification Mechanisms

Edwin Hsu, Wenkang Cheng, Nancy Hunag

In some EMS company, The LMS(Learning Management System) has been used in house for staff training in combination of online learning and maintain records of staff training history. For direct employees however, this does not satisfy the integration of production workstations and training programs. For this, the OPC(Operator Certification) system is developed to not only provide training records but also allow managers to develop primary job positions and required programs for every direct employee. The pass message is accessed via program connection to make up the current functions of LMS. In addition, the existing product lines are diversified with many workstations. It is necessary to greatly improve the skills of employees, move towards the expansion and enrichment of work, and add multi-skilled positions to allow managers to allocate works appropriately to meet the actual production line. job requirements.

展示攤位：PS2_3 (論文編號：TW0019)

In-Line Sputtered Copper/Aluminum-doped Zinc Oxide Films on Glass Prepared for Energy-saving and Antibacterial Function

Chan Huang-Tian, Chang Shang-Chou, Hsiao Chuan-An, Wu Jian-Syun

Energy-saving glass is designed to minimize heat transfer between the interior and exterior of a building, resulting in reduced energy consumption. Low-emissivity (low-e) glass is a type of Energy-saving glass. It offers superior insulation by reducing heat loss or gain through windows. Both energy-saving and low-e glass are widely used in buildings to improve energy efficiency, and contribute to improve the sustainability of buildings. If energy-saving glass in public facilities has antibacterial functionality, it can provide the public with a healthy and comfortable environment. This study reports the feasibility of copper/aluminum-doped Zinc Oxide (Cu/AZO) films applied in energy-saving glass. Cu/AZO films have been deposited on glass substrates via in-line sputtering system. Antibacterial effects are provided by Cu layer, while AZO layer offers thermal insulation capabilities. In-line sputtering is a process used for depositing thin films onto a continuous substrate. It offers high throughput, uniform coating, and precise control over film properties. It is commonly employed in manufacturing industries for applications such as architectural glass. Thus, this instrument is used in the study. In this study, Cu/AZO films were directly deposited by in-line sputtering with a Cu and AZO target, respectively. In addition, we manufactured a single-layer AZO films for comparison with Cu/AZO films. The structure, visible transmittance, adhesion test and antibacterial activity of the AZO films and Cu/AZO films were compared. The experimental results indicate that the single-layer AZO exhibits low resistivity and low emissivity but lacks antibacterial function. In comparison to AZO, Cu/AZO demonstrates lower resistivity and emissivity. The electrical resistivity of Cu/AZO samples are 1.08×10-3 Ω-cm, which decreases 49% compared with that of the AZO. According to the Hagen-Rubens relation, the reduction in electrical resistivity corresponds to the decrease in material emissivity. The emissivity of Cu/AZO films and AZO films were 0.22 and 0.30 respectively. The average transmittance in visible wavelength (400-800 nm) of Cu/AZO films and AZO films were 56% and 74% respectively. The antibacterial testing was conducted in accordance with the JIS Z2801:2000 standard. Cu/AZO films exhibited a pronounced antibacterial effect against E. coli, displaying an antimicrobial activity level of about 7. Copper material provides antibacterial property, possibly due to its contact killing mechanism. Copper ions cause the destruction of the cell membrane. Furthermore, the addition of copper further reduces the material's resistivity and emissivity. The Cu/AZO proposed in this study has antibacterial and thermal insulation functions. In the future, this can be applied in the mass production of energy-saving glass and the field of green materials.

展示攤位：PS2_4 (論文編號：AS0041)

Valor Stencil Design Introduction and Benefit Evaluation

Chun-Chi Chiu, Bing Bing Huang

In USI, general stencil design flow is as following: engineer proposes stencil aperture; then, delivers the proposals and product data to stencil vendor for coming out stencil file; Finally, checks stencil file. If there are some mistakes, need stencil vendor to modify until every aperture is confirmed OK. It is widely used in SMT industry. But it has some disadvantages; It costs engineer much time on proposing and checking; sometimes, some mistakes may not be found and corrected due to carelessness; In addition, stencil aperture is probably not consistent if it is designed by different engineers. All above will probably increase risk of failure producing, then influence product quality. Currently, one solution to cover these disadvantages is Valor stencil design. It can create and check stencil aperture automatically based on the related stencil aperture library. It largely saves time of proposing and checking. It can also prevent almost all mistakes (such as missing stencil aperture) from happening and keep consistent stencil aperture for same design component based on stencil aperture library. In addition, engineer novice can much easily design and check stencil aperture by Valor. So we plan to evaluate how much time can be saved through Valor, how almost all mistakes are prevented, and how consistent stencil aperture can be ensured in product with same design. Through evaluation, we found following conclusions. With the advantage of abundant stencil aperture libraries and exclusive component grouping principle of Valor, the time for stencil design can be saved about 75%; any components with same design can use same stencil aperture design, and then keep consistent stencil aperture. In addition, the principle can also help to prevent almost all mistakes during designing and checking. So, it can be introduced to all USI factories to improve efficiency of stencil aperture designing, ensure steady and good product quality if necessary.

展示攤位：PS2_5 (論文編號：TW0043)

Advanced Development of 3D Inkjet Printing Package Integrated with DPC Ceramic Technology For UVC-LED Sterilization Applications

Dei-Cheng Liu

Under the influence of the novel coronavirus (COVID-19), WHO has identified Wuhan pneumonia as an international public health emergency. In order to prevent virus infection and spread, in addition to basic protection such as wearing a mask and washing hands frequently, according to experts from the Institute of Virus Prevention and Control, the SARS (SARAr-CoV) virus can be killed in 30 minutes under UV-C irradiation greater than 90uW/cm2 . UV LED does not require warm-up time and mercury, so it has the advantages of environmental protection, long shelf-life, energy saving, and less heat loss. In addition, UVC-LED only use a single wavelength band and the optical power still needs to be increased, so there are less concerns about irradiation safety. The advantages of miniaturization of the light source, it can fully respond to the market demand for small spaces and surface/air conditioning sterilization. The purpose of this project is to be lead in applying the new technology of "3D inkjet printing technology on integrated with DPC ceramic technology for UVC- LED into new ceramic packaging structure" as the key structure technology of its UVC-LED luminous sterilization packaging, and through the 3D inkjet printing technology ceramic frame packaging substrate that has the unique characteristics of non-contact substrate, single and simple manufacturing process, better design flexibility of ceramic frame packaging structure. In order to solve the problems faced by the existing co-fired ceramics as the packaging structure, it is used for future LED light-emitting sterilization packaging applications. Therefore, it highlights that the future market demand for UVC-LED active sterilization will gradually increase. UVC-LED can be widely used in air sterilization and purification, water sterilization (including static water and flowing water), surface disinfection (such as water tank, direct drinking water, humidifier and smart toilet sterilization), medical phototherapy and other applications.

展示攤位：PS2_6 (論文編號：TW0044)

Optimize Stencil Apertures to Eliminate SMT Solder Defects by Shadow Moiré for Warpage Measurement

Kevin Hong

There are key industry trends that are driving the need for the package warpage measurement by temperature variation and focus on manufacturing process development for large component with finer-pitch solder balls in high-temperature lead-free process. Warpage measurement by Shadow Moiré becomes a key measurement for analysis, prevention and prediction of interconnect defects for advanced process development. In this paper we discuss how to analyze the data of Shadow Moiré for warpage measurement of component packages with applications in failure analysis, new product qualification and process control. In accordance with Shadow Moiré data, design the suitable stencil aperture design to prevent the defects in solder joints, such as Head-on-Pillow (HoP), Non-Wet-Open (NWO). In New Product Development (NPD), establish this process preventive mechanism for new component introduction and avoid if the unexpected process issues impact production quality.

展示攤位：PS2_7 (論文編號：TW0062)

Highly Uniform Copper Electroplating Solution for HDI Conformal Plating

Chieh-Ju Li, Shih-Chun Huang, Jimmy Chiu, Chi Yen

The significance of the PCB industry becomes increasingly evident with the rise of high-tech applications like 5G networks, artificial intelligence, and autonomous vehicles. Notably, high density interconnect (HDI) technology stands out as a pivotal and rapidly advancing component in this field. Not to mention the hottest topic in the semiconductor industry currently, IC substrate. Among the complex structure of IC substrate, through-hole plating quality directly plays the critical role of deciding the transition speed of electronic devices. Consequently, the industry necessitates innovative plating formulations to drive its industrial development, ensuring it keeps pace with these evolving demands. Our research centers on the identification of crucial factors that enable the simultaneous optimization of uniformity and throwing power in through-hole plating. Through the utilization of design of experiments, electrochemical experimentation, and plating verification techniques, we have successfully developed an exceptional electrolytic copper additive specifically tailored for HDI through-hole plating. The incorporation of proprietary organic additives has yielded remarkable results in terms of achieving outstanding uniformity and throwing power. Moreover, the utilization of this unconventional electrolytic plating solution ensures simplified bath maintenance, addressing an essential aspect of the process. Additionally, we cannot overstate the significance of cost reduction in the PCB manufacturing industry. The exceptional uniformity performance of our proposed solution presents manufacturers with an alternative avenue to optimize their mass production procedures. In conclusion, this paper serves as a testament to the efficacy of our more efficient electroplating solution, specifically tailored for HDI applications.

展示攤位：PS2_8 (論文編號：TW0065)

Equipment Maintenance Traceability System（EMTS）for Equipment Cost Analysis and Preventive Health Diagnosis

Edwin Hsu；Yu Ren Chen；Yue Li

The equipment replacement plan originally relied heavily on the age of the equipment. However, with the introduction of EMTS (Equipment Maintenance Traceability System), more information can now be compared, including equipment lifespan, frequency of parts replacements, and the cost of replacement spare parts. Productivity is directly influenced by the operational condition of the equipment, and minimizing downtime is crucial for achieving high productivity. Currently, there is a lack of a coordinated equipment management system across global production sites, resulting in an inability to promptly access real-time information on equipment usage and maintenance records. To address this, the software functionalities of each factory are being integrated and improved. This allows equipment managers to reference historical data from the system and analyze cost differences, equipment age, machine serial numbers, and other relevant factors to create effective equipment replacement plans. Through the assistance of IT and software development, the site Office Application (OA) system incorporates a spare parts management module, equipment maintenance record sheets, and an equipment preventive maintenance module. This integration forms an equipment maintenance traceability system, which is being implemented and promoted across all sites.

展示攤位：PS2_9 (論文編號：AS0074)

High-speed Channel Design and Correlation between Signal Integrity and Electrical Validation of Datacenter Platform

Chiew Yee Ho, Brian Ho, Jimmy Hsu, Kuan-Ting Wu

As the data center industry grows rapidly and high-speed signal data rate increases, the channel design and electrical characterization are crucial to ensure the quality of the high-speed signal. Correlation of high-speed interconnect’s (HSIO) channel design and its electrical characterization are helpful to help the Silicon and Platform designer to understand how the system channel design that would affects the Silicon HSIO Physical (PHY) layer’s Receiver Equalizer (RXEQ) functions in optimizing the high-speed signal data transmission with low bit error rate (BER). This paper provides a comprehensive correlations of Signal Integrity (SI) measurement and Electrical Validation (EV) data collected. Intel ® Automatic In-board Characterization (AIBC) is adopted to efficiently characterize mother board design quality with over thousands of HSIO testing for the impedance and channel loss. It can identify the potential design and PCB manufacture quality issues to ensure board design robustness. Intel® IO Margin Tool (IOMT) was adopted for electrical validation, and the voltage margin and timing margin of Silicon Receiver (RX), which can represent the signal integrity of the channels, can be derived afterwar as EV data that consists of the margin which represents the health of the channel design. In this paper, Ultra Path Interconnect (UPI) interface of 4 Intel based datacenter platforms with various channel designs are selected for AIBC and EV data correlation case study. The correlations could have two benefits. First, we can check whether the poor margin performance is induced by the high loss. Second, we can analyze the correlation between loss, margin result, and these RXEQ parameters to figure out which parameters affect margin the most. The RXEQ consists of 3 main modules, an attenuator (ATTEN) which provides signal attenuation and boost, Continuous Time Linear Equalizer (CTLE) for boosting high frequency signal energy to compensate the high channel loss, and Decision Feedback Equalizer (DFE) to remove the Inter Signal Interference (ISI) from the signal. The RXEQ processes the high-speed analog signal at receiver and produces a well-equalized high-quality signal to digital block with low Bit Error Rate (BER). The case study had demonstrated the relationship of the components, such as ATTEN, CTLE and DFE in equalizer adapting at various channel loss to recover the high-speed analog data at low BER. On Figure 1 shown most of the UPI ports are concentrated at the range of 7-9dB at 8GHz loss. As the loss increases, the voltage margin decreased substantially but maintained at the range of 70mV and above. Figure 2 shown a strong correlation between channel loss and CTLE. The trend of higher CTLE of the channels with higher loss was observed on 4 systems, which corresponds to the fact that higher loss requires higher gain to equalize the frequency response. As the result of the different signal equalizer settings of channels, the voltage margins of channels are tuned well. As Figure 1 shown, although the differences of the loss between channels are large, the measured voltage margin is not significantly different due to the CPU RXEQ adaptation. In summary, the output of the various PHY attributes and correlation with channel design would serve as great feedback for high-speed PHY and board designer to optimize their design for the new datacenter platforms.

展示攤位：PS2_10 (論文編號：TW0076)

Novel Approach for Producing Copper-Clad Laminates with Low Dielectric Constant and Low Dissipation Factor

Li-Ting Hunag* and Jyh-long Jeng

The copper-clad laminate is a substrate material utilized in the manufacturing process of printed circuit boards (PCBs). The substrate properties of a copper-clad laminate play a crucial role in determining the durability and electrical performance of the PCB. When components are soldered onto the PCB or during its operational use, the laminate can be subjected to heat. At elevated temperatures, especially beyond its glass transition temperature (Tg), the substrate may undergo thermal expansion. This expansion has the potential to cause delamination of the copper layers and/or breakage of joints that connect components to the PCB. Moreover, the dielectric constant (Dk) and dissipation factor (Df) of the laminate have a significant impact on signal propagation through the PCB and the amount of electromagnetic energy lost within the PCB. These factors influence the transmission rate of signals and the level of signal integrity within the circuitry. The aerogel material made from highly heat-resistant polyimide (PI) exhibits a lightweight and low-density structure. Its high porosity imparts several properties, including low dielectric constant and low thermal conductivity. However, despite the formation of a cross-linked network structure through the polymer matrix, aiming to enhance the material's Tg and mechanical properties, it still faces challenges in direct bonding with copper foil as a substrate material. When used, the adhesive used for bonding must maintain a certain bonding strength without compromising the dielectric properties. Therefore, the development of materials with excellent dielectric performance that also meet other requirements for PCBs, such as high heat resistance, dimensional stability, and adhesive properties, is currently a pressing issue for materials suppliers in the printed circuit board industry. We have developed a low dielectric constant composition consisting of a novel structure design of polyamic acid (PAA) polymer undergoes a crosslinking reaction, followed by imidization and drying, to form a low dielectric polyimide aerogel substrate. The substrate is composed of a thermosetting low dielectric ethylene copolymer resin adhesive layer and copper foils, which are laminated together through a pressing process to create a copper-clad laminate, it has the low Dk/Df at 10GHz (1.5/0.005) and also can passing the solderability test in 260˚C solder bath for 30 seconds. By creating larger pore sizes (600~1500nm) to enhance the internal framework rigidity of the material, we can prevent structural collapse during drying process, resulting in a high-porosity (≧90%), low dielectric PI aerogel substrate. Furthermore, larger pore sizes within the material reduce the influence of capillary forces, thereby improving the heat resistance and dimensional stability of the PI aerogel material, even after undergoing a 2 hours heat treatment at 300˚C, it still maintains high heat resistance and dimensional stability, with a volumetric shrinkage rate of 15%. This meets the requirements of the processing characteristics in printed circuit board fabrication processes.

展示攤位：PS2_11 (論文編號：TW0077)

Noise Analysis and Improvement of Power Supply Network Based on Power Integrity

Bing-Hong Su, Jie-Song Tang, Hsing-Jen Lee, Ching-Biau Tzeng

With the rapid development of today's electronic technology, the functions of many product devices are becoming more and more powerful, and the design of power circuits is gradually being paid attention to. Among them, power integrity is a very important consideration in circuit board design, especially for applications that require high conversion efficiency power supply, how to improve the performance of the overall power supply network (power delivery network, PDN) through layout improvement and appropriate component selection to optimization, these are the main keys that affect power integrity. This paper will conduct an in-depth discussion on the power integrity of the switching power supply. Due to the frequency change on the power supply circuit, the impedance of the coupling capacitor changes, resulting in a voltage drop, and the output voltage ripple becomes larger. Part of the analysis of the target impedance will be carried out through the implementation of the circuit and simulation software, and through the selection of appropriate capacitors, the target impedance can be controlled below 350mΩ. In the test, the power output is tested under the modes of DCM, BCM and CCM respectively. In the CCM mode, the output voltage ripple can be suppressed below 100mVpp, and the error of the output voltage drop is within 10%, and in the improvement of EMI, circuit board layout and appropriate component selection are adopted to effectively suppress EMI, and the final conversion efficiency can reach more than 80%. In the application, the designed power supply circuit is applied to the Microchip blood oxygen system, and the input power supply system module and the oscilloscope are used to confirm whether the signal is disturbed, and after individual confirmation of the improved circuit layout method, there are also improved with significant effects.

展示攤位：PS2_12 (論文編號：TW0093)

Low Contact Resistance and Low Temperature Hybrid Bonding with Polyimide and Highly <111>-oriented Nanotwinned Cu

Pin-Syuan He, Kai-Cheng Shie, Chih Chen

Among the recent decades, the development of fine pitch hybrid bonding is eye-catching, since this kind of technology could realize high-speed signal transmission with high reliability due to the shrunk electrical joints and the surrounded dielectrics. The polyimide (PI) possesses low Dk (~3.61 at 1MHz), low Df (~0.037 at 1MHz), low curing temperature, simple process ability at low cost, excellent mechanical properties, high resistance and stability. It is considered as an excellent candidate to protect joints and enhance their bonding strength. As a result, PI was incorporated with highly <111>-oriented nanotwinned Cu (NT-Cu) to achieve the low contact resistance hybrid bonding (<1.632×10^(-8)Ω·cm2) with low bonding temperature (<250 °C) in this study. To confirm the NT-Cu/PI hybrid bonding technology, we fabricated two bonding types: (A) PI-PI, and (B) NT-Cu/PI- NT-Cu/PI bonding. For PI-PI bonding, different curing degree of PI films (from soft baking to the standard full curing of PI) are chosen to measure the bonding strength and the change of imidization degree after being bonded or treated at 200 °C for 30 min. For NT-Cu/PI-NT-Cu/PI bonding, the co-CMP process is vital. Due to the strong chemical resistance and excellent mechanical properties of PI, a high selectivity slurry for PI is required. Kelvin structure is designed to measure the electrical and contact resistance. The results show that the excellent bonding interfaces and the contact resistance below 1.632×10^(-8) Ω·cm2 can be obtained at below 250 °C under 8.3 MPa. The electrical resistance is quite stable, with the scanning of 1001 points from -0.5 A to +0.5 A, a linear I-V curve can be gotten. With a fixed current of 0.1A, the average resistance value of the Kelvin structure measured 10 times is 4.2 mΩ, with a standard deviation of ± 0.79 mΩ. Furthermore, the NT-Cu/PI hybrid bonds possess very low resistance and very low contact resistance. The height mismatch of NT-Cu and PI can be calculated by a linear expansion formula using their thicknesses, coefficients of thermal expansion, and the bonding temperature (below the glass transition temperature of PI). Because the theoretical value of the thermal expansion coefficient of NT-Cu and fully cured PI are 16.6ppm/K and 33ppm/K, if the bonding temperature is 200 °C, the PI needs to be 8.61 nm lower than NT-Cu joints. However, PI is very difficult to be removed or get the excellent height profile with CMP, so the surface morphology of the post-CMP PI may be as high as NT-Cu joints or become a slight dome shape. Surprisingly, the characterization of polymer can be the key solution of this issue. In this study, once the bonding temperature is closer to the glass transition temperature of PI, there is more opportunity to soften PI and squeeze it out; at the same time, as long as the dished nt-Cu can be avoided, the NT-Cu/PI hybrid bonding can still be achieved with an excellent bonding quality.

展示攤位：PS2_13 (論文編號：TW0095)

3D X-Ray Observation of Electromigration-induced Voids in 30-µm Solder Microbumps

Shih-Chi Yang, Hung-Chieh Su, Tomoo Uraguchi, Chih Chen

Electromigration (EM) is one of the trending topics of the reliability of solder interconnects. To detect EM-induced failures in the solder joints, non-destructive methodologies including micro-tomography and X-Ray laminography were executed to replace destructive approaches. As the shrinkage of solder interconnects continues, a more precise non-destructive analysis is needed. In this study, high resolution three-dimensional X-Ray (3D X-Ray) observation was utilized to detect the EM-induced voids failure of the 30-µm solder microbumps. The spatial resolution of 3D X-Ray is as low as 0.4 µm, which is capable of detecting voids formation in the solder. Unlike the 2D analysis for a single surface by destructive methods, the percentage of voids volume in the microbump can be calculated by the aid of 3D X-Ray facility. In this work, the results of 3D X-Ray observation are in great agreement with destructive analysis by scanning electron microscopy (SEM). Considering two dominant failure mechanisms of EM in solder microbump, we can clearly distinguish voiding from intermetallic compound (IMC) formation by 3D X-Ray. Furthermore, EM-induced voids failures of different EM condition were examined in this research.

展示攤位：PS2_14 (論文編號：TW0104)

PCI Express Receiver Channel Signal Quality Validation Method

Dian-Ying Wu

High-speed Input/Output (HSIO) data rate goes faster and faster than before. Now, the highest speed of PCIe in the industry is PCI Express Gen5 with 32GT/s and its next generation is PCI Express Gen6 with 64GT/s. The signal waveform will be impacted much by channel design quality in higher speed. In order to measure the channel’s impact, the PCI-SIG defines an industrial specification to standardize the signal quality validation methodology for Transmitter (TX) side of a system. The TX signal Eye diagram is the method for TX channel quality. For the Receiver (RX) side, the common used methodology to validate the receiver channel’s quality in industry are Signal Integrity (SI) simulation and Bit Error Rate Test (BERT) method. However, at PCI Express Gen5, the Bit Error Test is not enough to identify the difference of receiver channel’s quality for two RX designs while their error bits are all meet the criteria (1 error of 4*10E12 bits) which defined by PCI-SIG. We only can say the two RX designs are low-risk, but we don’t know exactly which design is better. To solve this problem, we would like to introduce a new methodology for PCI Express receiver channel quality by testing of the “Receiver Eye Diagram”. To implement this new methodology, a new test fixture (called Interposer board) for CPU socket is developed. This RX Eye Diagram methodology is referred from the PCI Express Transmitter (TX) Eye Diagram methodology which is defined by PCI-SIG. Here is the test flow of the RX Eye Diagram Methodology. First, we need to put our test fixture (Interposer board) on CPU socket, then connect the SMA cables from Interposer Board receiver data signal (P/N) connectors to high-speed real time scope and connect the SMA cables from pattern generator in high-speed real time scope to Interposer Board transmitter data signal(P/N) connectors. Second, we need to attach an addon-card (AIC) device with motherboard (MB) which we want to verify its RX signal quality. Third, power on the system and the AIC device will get into compliance mode automatically, then sending out compliance patterns continuously. Forth, we can capture the compliance patterns waveforms from TX EQ settings Preset 0(P0) to Preset 10(P10) which defined in the PCI Express Gen5 Base Specification. Fifth, we can take these compliance pattern waveforms to do analysis by Sigtest Phoenix tool which provided by PCI-SIG and get the eye diagram with the Eye Height/Eye Width data from it. After above test flow, the PCI Express receiver channel’s signal quality can be exactly known by RX Eye Diagram method. Based on the Eye Height and Eye Width results, the system board’s receiver channel quality can be improved.

展示攤位：PS2_15 (論文編號：TW0105)

Micro-Defect Failure Analysis in Fan-Out Package and Correspond to Finite Element Method (FEM) Simulation Results

Yujen Chang

Fan-Out (FO) structures are used for the heterogeneous integration packages recently because it offer high I/O counts, thinner package and lower cost. Along with the performance evolution, the fine line and fine space are trends to 2 µm/2 µm. The failure analysis (FA) of tiny defects of the finer interconnection redistribution layers (RDLs) localization are constantly facing the new challenges within the complex package. The FO package with the multiple chips, two Si dies were connected with the FO RDLs as shown in Figure 1(a). The FO structures enable multiple chips integration using the fine pitch and fine width RDL to interconnect each dies (Figure 1(b)). In this paper, we investigate the FO package with open failed after temperature cycle test (TCT). The FA workflow is examined by electrical testing, 3 Dimensions X-Ray Microscope (3D X-Ray) and Focus Ion Beam (FIB) to find out the failure location and defect mode as shown in Figure 2. Finally, we use finite element method (FEM) to investigate the global and the local stress distribution. To localize the defect in the FO structure, using parallel lapping to remove the package substrate and top dies. Divide the failure path into three parts and then perform electrical test of each part individually. According to the electrical test results of these three parts, we suspect the defect existing at the μbump- fine line RDL-μbump as shown in Figure 3. 3D X-ray inspect at the μbump and the fine line area to confirm the defect location. From the high resolution 3D X-ray image as shown in Figure 4, we observed that there are trace broken at RDL1. The FIB analysis was done on the abnormal area, and we found the trace broken and the Polyimide (PI) delam at failure area as shown in Figure 5(a) and 5(b). In order to confirm the stress distribution in the package, we use the finite element method (FEM) simulation. FEM is often used to estimate the warpage behavior of packages in simulation model. Under TCT, the package was heated to a higher temperature and then cool down to the room temperature. The temperature changes will cause the warpage occurred due to the coefficient of thermal expansion (CTE) mismatch. The high stress would result the PI delam and then cause the trace broken during the reliability test. In this case, the trace broken was found at the location where was matched to the FEM local stress distribution result. In the new packages development period, the FEM simulation not only can provide the stress distribution of the package structure but also useful for the failure behavior investigation.

展示攤位：PS2_16 (論文編號：TW0109)

Dynamic Response Analysis of PCB Under High-G Shock

Ming-Chen Yu, Wu-Lung Wang, Hsin-Chih Shih, Chin-Li Kao, CP Hung

With the development of the science and technology industry, the miniaturization of electronic products is more trendy, making electronic components to be integrated at a high density, especially when the head-mounted device is subjected to high-G energy when it is dropped, it faces the risk of failure. This state will cause failure of the shell, Failure of internal electronic components or package interconnects to the circuit board. Therefore, the impact of shock on the integrity of electronic components on printed circuit boards (PCB) is an important reliability issue to be addressed. Since the impact force during the drop impact will cause the strain and acceleration response of the PCB, in order to better understand the risk on the deformation of the board step to the product. And to design more reliable products in the future to deal with the impact load, this paper studies on the response of the PCB with length and width ratio of 2.6:1 under the influence of different drop heights and accelerations, and observing the dynamic behavior of the PCB at the moment of high-speed drop through the shooting of a high-speed camera, it is found that the convergence speed of the PCB at 10,000 G is faster than that at 1,500 G, and the viscous damping system describes the behavior of the PCB when it is impacted. In addition, the locking of the gasket is added in the 10,000 G impact test to observe the impact of changing the locking conditions on the PCB. This study shows that below 1,500 G, the damping ratio at the PCB center point is 0.036, but at 100,000 G the damping ratio is 0.067, which increases by 86%, because the increase of the damping ratio causes the PCB convergence rate to increase faster and return to flattened faster. In addition, adding gaskets to the PCB lock will affect the strain change at the center point, and the strain at the center point will decrease as the size of the gasket increases. These results can help the PCB to have a better design reference when facing the challenge of more than 100,000 G in the future. List of Keywords: Shock test, Viscous damping system, PCB dynamic response, Board level reliability,. High speed camera

展示攤位：PS2_17 (論文編號：TW0118)

Development and Validation of Simulation-Based Prediction Application of G3.5 Panel-Level-Package Copper Electroplating.

Hsu YuLin

In this research, we collaborated with an electroplating equipment vendor, a display panel manufacturer, and a simulation software company (Cadmen/Ansys) to develop a G3.5 copper simulation-based prediction application for a specific electroplating tank. Initially, we established a simulation model of an RDL (Redistribution Layer) copper electroplating tank by fine-tuning and validating the overall parameters of the electroplating tank. Subsequently, we constructed a ROM (Reduced Order Model) database using optimized equipment parameters from the previous simulation model and integrated the ROM with a customized application GUI (Graphic User Interface). This application enables real-time prediction of graphic uniformity without the need for additional simulation processes or equipment parameter adjustments. It proves advantageous in assisting process personnel with experimental design, reducing the number of experimental groups, shortening process development time, and supporting mass production.

展示攤位：PS2_18 (論文編號：TW0125)

Statistical In-board Characterization Analysis for High-speed Data Center Platform

Yu Hsuan Chen

The conventional electrical measurement method is only limited in the test coupons because there is no efficient approach for in-board measurement. Intel ® Automatic In-board Characterization is developed to transit from solely measuring coupons to encompassing the measurement of entire PCB [1-2]. AIBC can conduct full scope in-board characterization in one board for the design quality, manufacture variation and PCB technology verification. How to set the reasonable measurement quantity with the good confidential level is very important in high-volume manufacture monitoring. In this paper, a statistical approach is proposed to validate the confidential level of the various sample sizes. The statistical full in-board characterization methodology with over six thousand impedance and insertion loss is developed and proposed to have the confidential level in high-volume manufacture monitoring. In this study, over 6000 testing datasets by total 21 pieces PCB samples from 4 different vendors for highspeed datacenter reference platform were measured by Intel ® Automatic In-Board Characterization (AIBC), and this statistical analysis can efficiently evaluate the manufacture variation among various samples by different suppliers for quality management. According to these comprehensive studies, the sampling with 3 pieces PCB boards concluded to have over 85% confidential level. This study will simulate the scenario of sampling 1 to 5 PCB boards to identify how many samples size impact on the coverage above specific confidential level. According to the distribution variation with different sample sizes in Figure 1, that the coverage rate will getting more and more obviously while the sample size increases from 1 to 5. Although it is higher confidential level when sampling many PCBs, but the testing cost and resource also increases accordingly. Therefore, to balance between cost and confidence level, this study developed an algorithm that utilizes statistical analysis to evaluate how to select the sample size. The random sampling approach in statistical method is proposed and adopted to simulate the variability in Figure 2. For average coverage case, 1000 times simulation will be conducted to evaluate the situation. In each simulation, various combinations will be picked up from 21 PCB board samples. Take sampling 3 pieces of PCB for example, A random sample of 3 PCB will be drawn from the pool of 21 PCB board samples as a single simulation. In each combination, maximum and minimum impedance in the 3 PCB will be used to compute its own max range. After 1000 simulations are conducted , all the max range data will be summed and divided by 1000 to calculate the average result under normal conditions. The statistical methodology was proposed to evaluate the variability of PCB manufacture by various vendors. As the result shows, though there’re some difference result between different vendors, it still can be observed the trend of confidential level can reach above 85% when sampling a specific piece of PCB.

展示攤位：PS2_19 (論文編號：EU0126)

X-ray Photoelectron Spectroscopy (XPS) Investigations to Monitor the Cleanliness of Copper Surfaces during Palladium-Free Colloidal Copper Activation

Ibbi Y. Ahmet*, André Beyer, Laurence J. Gregoriades, Julia Lehmann, Yvonne Welz

Palladium-free activators based on colloidal copper systems are proving to be robust alternatives to conventional ionic palladium-based systems. Recent developments have shown that such colloidal copper activators can be used for electroless copper plating on a wide range of materials, including SAP relevant substrates, with plating performance competing with that of ionic palladium. [1] Most promisingly, electrical reliability tests are shown to be free of interconnect defects (ICDs) providing evidence of good copper cleanliness after activation. [2] These encouraging results fuel efforts to establish a detailed understanding of the surface chemistries for the full colloidal copper activation process with particular attention to the copper interconnects within through holes (TH) and capture pads within blind micro vias (BMVs). In this regard we have performed sequential X-ray photoelectron spectroscopy (XPS) analysis to monitor the surface chemistry of each step, from the conditioning to the deposition of the colloidal copper system (i.e. conditioner, selector, activation). Here we have chosen copper coated silicon wafers as a clean and practical substrate to represent copper surfaces. We monitored the N 1s spectra, in combination with the C 1s and O 1s spectra, to determine the functionality and concentration of various organic components at the surface after each treatment step. Furthermore, we used the Cu Auger and Cu 2p spectra to track the changes in the copper oxidation state. These XPS results qualitatively reveal significant insights into the role of the different treatment chemistries and how they influence cleanliness of copper surfaces. Interestingly we found that the selector treatment shows good performance in removing the conditioner chemistry from the copper, whilst simultaneously exposing and stabilizing metallic copper at the surface. These XPS results thus reveal that the selector can minimize the amount of unfavorable oxide species. This in-depth analysis using sequential XPS has provided valuable insights for the further developments of palladium-free colloidal copper activation processes. By understanding the specific roles of each treatment step and their impact on copper surfaces, we are now in a better position to optimize the entire process and can strive towards enhancing the reliability thereof.

展示攤位：PS2_20 (論文編號：TW0129)

Photopolymer Composite with High Thermal Conductivity and Low Dielectric Properties for 3D Electronics

Yi-Chen Weng, Ying-Chih Liao

With the rapid development of the electronics industry, the demand for miniaturization and integration of chips and components in electronic devices has been steadily increasing. The emergence of 5G communication has further highlighted the need for components with high energy density and fast signal transmission capabilities. Consequently, the development of materials with high thermal conductivity and low dielectric properties (i.e., Dk and Df) has been given considerable importance in recent years. In order to rapidly and accurately fabricate objects, the technique of photocuring 3D printing possesses significant advantages in material development. It effectively reduces experimental time and waste, while enabling the printing of complex geometries. The primary material used in photocuring 3D printing is polymer resin. Polymers have advantages such as lightweight, ease of processing, low cost, good mechanical properties, excellent insulation performance, and low dielectric characteristics, making them an ideal material for electronic component packages. To enhance the thermal conductivity of polymers, fillers with high thermal conductivity are typically incorporated into the polymer matrix. Commonly used thermally conductive fillers include carbon-based materials (such as carbon nanotubes, graphene, and carbon black), ceramic materials (such as boron nitride and aluminum oxide), and metal materials (such as silver powder and copper powder). Among them, ceramic fillers that exhibit both high thermal conductivity and low dielectric properties have become noteworthy. However, it is crucial to ensure that these fillers are properly distributed within the polymer matrix to form an effective thermal conduction pathway. Otherwise, issues such as agglomeration or settling of fillers would reduce the stability of the polymer resin and the overall thermal conductivity of the printed components. In this study, methyl methacrylate (MMA) is chosen as the monomer for the photocurable resin due to its advantages such as low cost, high transparency, and excellent mechanical strength, making it suitable as the main material for electronic component packages. To further enhance the thermal conductivity of the photocurable resin, two different-shaped (flake and spherical) boron nitride fillers are selected as fillers. The aim is to adjust the solid content of the two types of boron nitride in the resin and employ suitable dispersing methods to ensure their proper dispersion and the establishment of an effective thermal conduction pathway within the resin matrix. Finally, the formulated resin will be utilized in the photocuring 3D printing process, enabling the rapid and precise printing of complex-shaped electronic component packages. Additionally, the printed objects can undergo post-processing, demonstrating the feasibility of using photocuring 3D printing technology in material development.

展示攤位：PS2_21 (論文編號：AS0136)

PCB Solution with Partial Plane-on-Outer-Layer (POOL) Stackup

Yinglei Ren, Jimmy Hsu, Brett Grossman, Gary Brist

High speed signal performance and PCB cost (e.g. PCB layer) are two important factors to consider during board design. Partial POOL stackup can help balance performance and PCB layer. However, the imbalanced copper density caused by signal / plane layer switch in local areas in partial POOL design may bring risks in manufacturing, reliability and signal integrity (SI) performance. To evaluate the risk level of implementing partial POOL stackup in server design, test boards were built by two PCB suppliers. Fabrication / reliability / SMT assembly / SI tests were done. This paper will introduce the test results. E.g. additional memory signal impedance variation was observed during AIBC (Automatic in-board Characterization) test which effectively captured TDR results of each memory signal on the board. Test details together with the reasons behind the results will be shared.

展示攤位：PS2_22 (論文編號：TW0141)

Decision-based Virtual Metrology Framework to Improve the Efficiency of Solder Resist Opening Qualify Control and an Empirical Study in Printed Circuit Board Manufacturing

Chen-Fu Chien, Yung-Chen Tai, and Yun-Siang Lin

As key component of electronic products, the importance of printed circuit boards (PCBs) has increased with the development of technology. With the rise of new technologies, the demand and importance for PCBs is also rising. With development of electronic products towards size shrinking, combined with the demand of transmission rate and computing power, PCB manufacturing becomes sophisticated, thus requiring more effective quality control methods. The quality of PCBs will directly affect the performance and reliability of back-end products, more precise manufacturing and more effective quality control are required. Solder resist is a surface coating of PCB and is one of the important processes. Above it, some parts need to be excluded from being covered, called solder resist opening (SRO). The size of SRO is a critical quality characteristic, as PCBs become increasingly shrinking, the size of the SRO is also becoming smaller. If the manufactured SRO size is out of specification, it may cause abnormalities during subsequent soldering, resulting in product scrap and yield loss. However, quality control of SRO size is complicated. SRO is affected by multiple processes and can only be measured after the last process, so the inspection must go through a pilot production, leading to material cost for inspection. Besides, the variance of incoming material, solder resist ink, is comparatively high, thus different SRO size compensation values are required for each incoming material batch. To control the quality and confirm the compensation value setting, manufacturers need to carry out stages of pilot runs and inspections, which consumes material costs and time. In response to actual measurement problems, virtual metrology (VM) has been proposed to achieve in-line prediction of target quality characteristic, yet little research exists for PCB manufacturing. Little VM research has been conducted to propose VM framework for PCB manufacturing. In practical application, the uncertainty of VM model prediction and the cost of model update are faced, so the VM framework needs to be integrated with the process of batch compensation value determination based on domain knowledge. If VM is used instead of actual inspection, the pilot run material cost can be reduced and the capacity loss due to inspection can be decreased. This study develops a decision-based VM framework for SRO size, which combined feature selection, prediction model, and the decision process of compensation value determination. In addition, a confidence indicator is proposed to evaluate the reliability of predicted values, which also used as a reference for the model update mechanism to achieve a trade-off between model stability and update cost. An empirical study was conducted in a PCB manufacturing company. The result shows that the framework can help engineers to make decision on compensation values, further replace physical inspections to improve the efficiency of quality control and help PCB manufacturing industry to move towards intelligent production.

展示攤位：PS2_23 (論文編號：TW0153)

Self-Adsorption Polyethylenimine-capped Pd Nanoparticles for High Peel Strength Electroless Cu Plating on LCP and PTFE Substrate

Yi-Cang Wu, Pei-Qing Yang, Pei-Tsen Wei, Tzu-Chien Wei

Electroless plating (ELP) is a common process to metallize non-conductive substrates by means of a catalytic chemical reduction, in which Pd-based activators such as Sn/Pd colloids and Pd ions are widely used as the catalysts to trigger Cu2+ reduction from ELP bath. With the advent of high-frequency, high-speed 5G era, the substrates are required to possess low surface roughness and low Dk/Df. Liquid crystal polymer (LCP) and polytetrafluoroethylene (PTFE)-based materials fit abovementioned features and are chosen as the advanced PCB substrates. However, lacking for distinct adsorption mechanism onto chemically inert LCP and PTFE substrates, both Sn/Pd colloids and Pd ions processes encounter either failure of ELP or insufficient ELP Cu peel strength. Moreover, both Sn/Pd and Pd ion activation are two-step processes; the former requires to remove Sn shell in acidic bath so that the catalytic Pd core can be exposed and the later needs to reduce divalent Pd ion to atomic Pd using additional chemical reagents like DMAB or so. In light of modern PCB manufacturing tends to reduce carbon footprint, obviously the two-step activation of commercial Sn/Pd and Pd ion processes has plenty room to reduce water consumption and minimize chemicals usage. Aiming to develop a novel activator for high-end PCB substrates metallization and meanwhile fulfill the low carbon footprint production, we synthesize a novel polyethylenimine-capped Pd nanoparticle aqueous suspension (PEI-Pd) and explore its applicability in ELP Cu on LCP and PTFE substrates. The PEI-Pd is bi-functional as it provides not only self-adsorption capability onto the substrate from the amine moieties on the PEI structure but also able to activate ELP Cu directly using its Pd0 core; achieving adsorption and activation in a single process. Characterized by transmission electron microscopy (TEM), dynamic light scattering (DLS) and X-ray photoelectron spectroscopy (XPS), the size and interaction between PEI and Pd are explained. In addition, the adsorption mechanism of PEI-Pd onto the substrates is also invesitgated using XPS and fourier-transform infrared spectroscopy (FTIR). The activity of PEI-Pd in catalyzing ELP Cu is analyzed by induction time monitoring and Cu/Pd ratio. Currently, the T-peel adhesions of ELP Cu using one-step PEI-Pd activation on FR4, LCP and PTFE substrates achieve 1190, 807 and 743 gf/cm, all are considerably higher than the peel strength obtained using Sn/Pd process. The bi-functional PEI-Pd activator paves a bright road for the realization of high peel strength of ELP Cu on advanced PCB substrates via a low-carbon footprint activation process.

展示攤位：PS2_24 (論文編號：TW0154)

Capping silver as passivation layer on nanotwinned Cu RDLs

Yi-Quan Lin, Yu-Wen Hung, Chih Chen

As the size of electronic components continues to shrink, the packaging technology has also been upgraded from 2.5D packaging to 3D packaging, which requires the assistance of rewiring layers. In order to have greater flexibility in multi-die integration and a more advanced die-to-die routing capacity, the redistribution layer (RDL) is required to meet stricter requirements on the size of the mask, the spacing of the RDLs, and the number of RDLs. It will be a key factor in 2.5D packaging and 3D packaging, so the RDL plays an important role in this. In order to solve the reliability problem of the RDL, it is very important to select the material of the RDL and the material of the passivation layer on the surface; from the previous research of our team, it is known that the copper line with a nano-twin structure has an anti-electrical The migration ability is better than that of the random copper structure, and the crystalline orientation with the (111) preferred direction is also better in oxidation resistance. Therefore, in this experiment, the 10um line width copper line was prepared by electroplating, and the height (111) preferred direction plane was introduced. Simultaneously, it has the characteristics of nano-twin structure; in the selection of passivation layer material, since the polymer passivation layer is easy to cause solvent volatilization during the curing process, holes appear in the structure, or the thermal stress is too high due to high curing temperature, while metal or low-dielectric material, but the process is relatively cumbersome and requires exposure and development technology. Therefore, this experiment uses immersion plating technology to deposit silver as the passivation layer. In addition to the fact that silver itself has better electrical conductivity and thermal conductivity than copper and is less prone to oxidation than copper, also has the advantages of selective deposition, simple and convenient manufacturing process, and relatively economical cost considerations. This study found that immersion silver plating can completely cover both sides and surface of copper lines, protect the copper line from direct contact with oxygen and water vapor in the atmosphere, and avoid the problem of copper line oxidation failure. To adjust, the thinnest can reach below 200nm, and the phenomenon of local epitaxial twin crystal structure was observed at the same time, this structure tends to reduce the resistance value, and this result can be applied to the RDL structure in the packaging field, or the front of MOSFET front side metallization process.