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Oct. 25th - Poster Session(Packaging)

Oct. 25, 2023 15:30 PM - 16:00 PM

Room: Foyer area, 5F

展示攤位：PS1_1 (論文編號：TW0013)

Development of Hierarchical Dendritic Copper Wick Structure for Ultra-thin Heat-Spreading Vapor Chambers

Chao-Yang Chiang

Compact and lightweight electronic systems have posed stringent dimensional criteria for heat-dissipation components such as heat pipes and vapor chambers. An ultra-thin vapor chamber (UTVC) with an overall thickness below 0.5 mm requires an interior capillary wick structure less than 100 μm. The capillary wick layer provides a flow path for fluid circulation of the condensed fluid back to the heated region in an operational UTVC. The maximum UTVC heat transfer rate normally depends on the capillary performance, which can be indexed by the liquid permeability (K) and capillary pressure (∆P). Large K and ∆P values are rarely realized in typical homogeneous porous structures. In this study, a novel hierarchical dendritic copper wick was prepared to achieve large K and ∆P simultaneously by one-step electrodeposition and thermal sintering process. The effects of electrodeposition parameters, such as current density, deposition time, and solution conditions on the capillary performance of the dendritic copper wicks were investigated. The results indicate that the wicking capability is modulated by the dendritic morphology of Cu deposits. Moreover, a post-deposition sintering process can improve further the structural integrity of the Cu dendrites and the capillary performance of the electrodeposited wicks. An optimal dendritic copper wick with a thickness of 30 μm possesses a promising capillary performance K/Reff of 0.811 μm, which is the thinnest wick reported in the literature, making it suitable for the development of UTVC in highly compact electronic systems.

展示攤位：PS1_2 (論文編號：TW0023)

Development of Ag-to-Ag Direct Bonding for Ge-Pb-Te thermoelectric and Cu electrodes with electroless plated M/Ni diffusion barrier

Yu-En Tsai, Cheng-Lin Shieh, Chien-Neng Liao

GeTe-based compounds exhibit promising thermoelectric properties in middle-high temperature regime. A functional thermoelectric module requires an appropriate bonding layer between thermoelectric legs and metal electrodes. This conductive bonding layer must be robust enough to survive thermal cycling and high-temperature aging operation. In this study, a Ni/Pd barrier and an Ag bonding layer were sequentially deposited on Ge-Pb-Te thermoelectric legs and Cu substrate by electroless plating. The resulting structure was formed by pressured bonding in ambient atmosphere at the respective temperature ranging from 250 °C to 325 °C under a pressure of 80 MPa. The fracture shear strength can reach 14.8 MPa in average at 325°C bonding temperature. The fracture surface indicates that the Ag-Ag bonding strength is superior to the Ge0.87Pb0.13Te fracture strength. However, the bonding layer lost strength after aging at 400°C for 24 hours due to degraded Ni barrier function. To solve this problem, an additional thin metal layer was inserted between Ge0.87Pb0.13Te and Ni layer. The Ni/M bilayer remained the structural integrity after aging at 400 °C for 24 hours. A thin and conformal intermetallic compound layer was formed at the interface, which is effective in preventing Ag diffusion through the barrier and reacting with Ge0.87Pb0.13Te compounds. The newly designed composite barrier layer can help the development of Ge-Pb-Te based thermoelectric modules assembled by Ag-Ag direct bonding technique.

展示攤位：PS1_3 (論文編號：TW0025)

Development of a Semiautomatic Probe Card Adjustment Equipment

Fu Chen Gao, Kuo-Wei Chiang, Zhe-Luen Tsui, Cadmus Yuan, and Chic Chang Wang

A semiautomatic probe card (PC) adjustment machine is investigated in this paper with the capability of manual precise operation within ±5um without a clean room facility. The precision is achieved by a three-level alignment strategy with the feedback-based proportional-integral-derivative (PID) control. Moreover, this precision can be guaranteed after long-term operation. A probe card (PC) is an essential interface between the tester and wafter to acquire the functional yield of the IC prior to the packaging. It provides information about the IC yield but also provides known-good-die (KGD) information for the packaging processes to achieve effective cost reduction. By direct contact between the probe tip and the IC pad, stable electronic connections can be formed to enable the functional tests. However, these continuous touch-down and pull-up cycling of the probe tip might cause the displacement of the probe tip. Approximately, after 3 weeks of continuous work, the location of each probe tip needs to be carefully inspected, and the ones with excess displacement need to be adjusted. The conventional PC adjustment work has been accomplished by the manual station with highly experienced engineers, as schematic in Figure 1. The PC has been placed on the manual X-Y table. A mylar reference, where the standard probe tip location has been plotted on a transparent sheet, is fixed to a flipping arm. The engineer first aligns the mylar reference and the PC below with the image from the microscope. By checking the probe tip individually, the engineer manually adjusts the displaced probe tip with the flipping arm upwards and then checks the adjustment result by rotating the flipping arm again. This rotating operation costs approximately 30% of the time. In the new design of the semiautomatic PC adjustment machine, as illustrated in Figure 2, the mylar reference is removed not only for cost reduction but also the work efficiency improvement. Introducing an automatic X-Y table and a controller computer with the probe tip’s standard coordination. A command can be submitted to order the X-Y table moving to the location of the standard coordinate. By inserting a cross in the microscope system (the ocular lens in this case), the PC engineer can obtain a probe tip reference. The conventional PC adjustment machine applies the mylar reference not only to identify the probe tip displacement but also to provide an alignment of the PC to the station. A new alignment algorithm with implementation has been developed in this research. Moreover, precision maintenance after multiple movements are investigated to guarantee long-term reliability.

展示攤位：PS1_4 (論文編號：TW0031)

Kalman Hidden Markov Model Detect User Gesture on Proximity Capacitive Sensor

Chao-Ting Chu, Wei-Chu Chao, Zhi-Xuan Lin, Chen-Yu Chang

This paper presented the Kalman Hidden Markov Model detect user gesture on proximity capacitive sensor. The human interactive gesture signal analyses have been a research topic smart home fields that algorithms build in local device to recognize real time. The Kalman filter algorithms have been a research topic in prediction signal, and Hidden Markov Model also is a dynamic recognition model to object identification and classification. This paper integrated Kalman filter and Hidden Markov Model to detect user gesture in proximity capacitive sensor. The features of Hidden Markov Model used probability concept train and learn identification model, and Kalman filter optimal predicted Hidden Markov Model results. Therefore, the Kalman Hidden Markov Model methods to identify user gesture has satisfactory response.

展示攤位：PS1_5 (論文編號：TW0032)

Microcontroller Frequency Domain Converter and Fuzzy Speech Recognition Analysis

Chao-Ting Chu, Wei-Chu Chao, Ze-Wei Huang, Zhi-Xuan Lin

This paper presented a microcontroller frequency domain conversion and fuzzy speech recognition analysis. The smart home recognition technologies have been a research topic in internet of thing fields that smart algorithms build in real time processor to recognize user identification. Recently, the speech recognition has been developed for smart speaker that detected around voice to recognition human speech, and control smart appliances system, immediately. Hence, we utilize low cost microcontroller with fast Fourier transform to converter speech signal, and the processor used fuzzy expert knowledge identify algorithms to implement speech recognition. In the experimental results, we show the different speech signal and fuzzy expert knowledge recognized different patterns.

展示攤位：PS1_6 (論文編號：TW0033)

Rotation Memory Proximity Two-Dimension Inductance Neural Network Identify Gesture Situation

Chao-Ting Chu, Wei-Chu Chao, He-Xian Lin, Zhi-Xuan Lin

This paper presented a rotation memory neural network (RMNN) identify user gesture situation in access control system. The access control system combined user gesture analysis have been a research topic in smart home fields that algorithms build in doorway real time detect user identification situation. The neural network have been used in many fields that including identification, control and classification. Neural network features is used neurons weight train and learn target results, and rotation memory used last information record neural signal to train weight state. Therefore, the RMNN methods to identify user gesture has satisfactory response.

展示攤位：PS1_7 (論文編號：TW0039)

Deep Learning for Pig Size Detection in Smart Farm Imaging

Chao-Ting Chu, Zhi-Xuan Lin

This paper presented the deep learning for pig size detection in farm imaging. The livestock industry in Taiwan is currently grappling with a critical shortage of manpower, necessitating prompt technological advancements. Compounded by the challenges of rural youth outmigration and declining birth rates, the industry faces a significant labor gap, resulting in reduced productivity. To address this issue, this study proposes the implementation of deep learning techniques in camera systems to enable real-time detection of pig sizes. By accurately assessing the condition of each pig, this innovative approach helps bridge the manpower shortage and enhances operational efficiency in the livestock sector, ultimately contributing to its sustainable growth.

展示攤位：PS1_8 (論文編號：TW0045)

Discrete Power Board solution on PDS

Gary Tsai

For Power Delivery System design, the power rails (e.g., CORE/GT rails) routings need to be well considered to meet Intel ACLL criteria which is listed in Intel EDS. In the meantime, the board layers planning is another key of design from cost perspective. So here is the idea to shrink the main board layers (probably from 10L to 8L) of Core/GT powers and use the Discrete Power Board (DPB) to compensate the ACLL and cost reduction aspects. We expect that customer can use the Discrete Power Board for each design from proto phase to MP (mass production) phase. This is about how to connect Discrete Power Board and main PCB to make the design seamlessly to meet design target and goal of product pricing. The concept of connection between main board and discrete power board is to use copper pillar with better DC characteristics for current flow from VR to SoC power balls.

展示攤位：PS1_9 (論文編號：TW0047)

Assessing the Durability of 2.3D Package Substrate Utilized for Heterogeneous Integration in Unmanned Aerial Vehicles under Vibration-Induced Stress and Temperature Fluctuations using Meshless Approach

Ching Feng Yu, Jr-Wei Peng and Chih-Cheng Hsiao

Unmanned aerial vehicles (UAVs) have become increasingly prevalent in various applications, ranging from surveillance and reconnaissance to delivery and disaster response. To enhance their performance and reliability in demanding operational environments, this paper presents a comprehensive study on the heterogeneous integration of UAVs utilizing 2.3D hybrid substrate technology. The study aims to analyze the performance of UAVs under vibration and temperature cycling conditions using a meshless method. Specifically, the focus is on conducting fatigue analysis of integrated electronic components and evaluating their reliability. In recent years, UAV technology has advanced significantly, leading to the integration of various electronic components within the limited space of these aerial platforms. However, the harsh operational conditions, such as high-frequency vibrations and extreme temperature fluctuations, can negatively impact the performance and longevity of these components. Therefore, it becomes crucial to assess their behavior under such conditions to ensure the reliability and functionality of UAVs. Fatigue analysis plays a vital role in evaluating the durability and reliability of electronic components subjected to cyclic loading. By applying the proposed analysis technique, the study investigates the fatigue behavior of the integrated components. This analysis provides insights into the potential failure modes and mechanisms, allowing for the identification of critical areas that require attention and improvement in the design and manufacturing processes. The results obtained from the study demonstrate the effectiveness of the 2.3D hybrid substrate technology in enhancing UAV performance and reliability. The integrated electronic components exhibit satisfactory resistance to vibration-induced stress and temperature cycling effects. This outcome showcases the potential of the proposed approach in ensuring the robustness and durability of UAVs in challenging operational scenarios. Overall, this study contributes to the field of UAV technology by presenting a comprehensive investigation on the heterogeneous integration of UAVs using 2.3D hybrid substrate technology. The analysis of UAV performance under random vibration and temperature cycling conditions, along with the fatigue analysis of integrated electronic components, offers valuable insights for improving the reliability and durability of UAVs. The findings of this study pave the way for further advancements in UAV design and manufacturing, ultimately leading to more efficient and dependable aerial platforms for a wide range of applications.

展示攤位：PS1_10 (論文編號：AS0050)

The Challenges and Solutions to the development of BuG Glass from Design Phase to Process Optimization for CMOS Image Sensors

May May Gan, Ying Heong Chiew

The demands on the imaging sensors are steadily increasing to support lane detection and traffic sign detection following the rapid development in the automotive industry. In general, lens is placed on the top of the image sensor to protect the sensor from harsh environments. With the latest lens development, black mask under glass (BuG) is introduced due to its glare reduction ability as compared to transparent glass. However, the presence of BuG arises risks and challenges in the dicing process due to its uneven surface mounted on dicing tape which requires huge effort for mechanical dicing to achieve chip-free process at the same time maintaining particle-free under the glass. This paper focuses on rectangular anti-reflective (AR) borosilicate glass. The bottom layer of the glass is laminated with black mask functioning as glare suppressor. This paper elaborates on the challenges of glass mounting method, selection of tape and blade and the dicing process optimization. BuG glass can be mounted either faced up or faced down. Both methods were assessed in this study. The mask faced up method is more dicing friendly as the dicing surface is smooth. However, glass transfer is required as an additional process before proceeding to glass attach process. This process induces risk such as particle trapped, encapsulation bleed and extra cost for transfer purpose. On the other hand, the mask faced down method is not required to undergo glass transfer process but more prone to chippings and crack due to uneven dicing surface on the tape. Selection of tape play an important role in ensuring cutting quality. Two types of tape were evaluated during the screening phase - polyolefin (PO) base film and polyethylene terephthalate (PET) base film. PO tape provides better adhesion as compared to PET base film tape due to its elongation properties. Thick adhesive layer is much preferred because it adheres better on the uneven black mask surface, thus, preventing saw dust sticking under the saw street. Characterization and design of experiment (DOEs) on blade selection between metal and resin bond blade was performed to reduce the mechanical stress on the chipping points. Overall, metal blade shows a promising result because it can be diced at a higher feed speed, wear rate is lower and not easily clogged compared to resin blade. By manipulating the dicing parameters such as higher spindle revolution and lower feed speed, chipping size can be controlled below 50um and Cpk>1.67 In conclusion, selection of tape, blade and parameters optimization play important roles in ensuring the product quality. Manufacturing cost and productivity should be taken into consideration to generate more profit and remain competitive in the industry. Keywords— iBGA, black mask under glass (BuG), anti-reflective (AR), glass dicing, polyethylene terephthalate (PET), Polyolefin (PO), hubless blade, design of experiment (DOE)

展示攤位：PS1_11 (論文編號：TW0055)

Fan-out Wafer-level Packaging Process Integration for Artificial Intelligence Real Dies

T. Y. Ouyang, O. Y. Xiovo, R. S. Cheng, Y. S. Chang, T. Y. Hung, C. K. Lee, and Y. M. Lin

Fan-out wafer-level packaging (FOWLP) is recommended as a promised packaging technique to integrate heterogeneous chips into a system for high-performance applications. In this report, we propose a chip-last FOWLP process to fabricate the system-in-package (SiP) architectures, including artificial intelligence (AI) and memory real dies. We demonstrate a high-functionality package that can interconnect multiple chips into one system. Such a small form factor package structure would introduce many obstacles such as coefficient of thermal expansion (CTE) mismatch effects between different materials and intrinsic stress induced by thermal budget. In this study, the complex design layout of redistribution layer (RDL) routing and optimization of the manufacturing process has been successfully demonstrated. X-ray analysis reveals a void-free performance in the package module. Thermal cycling tests have been performed to confirm the thermal stability of Showa Denko’s granule molding compound implemented in FOWLP. The huge intrinsic warpage of a single module can be modulated by a modified substrate to achieve a relatively low module warpage. The package module was flip-chip bonded to the HDI board and assembly to a functional substrate to demonstrate the functionality of AI and memory dies.

展示攤位：PS1_12 (論文編號：TW0068)

Effect of Microstructures on the grain growth behavior in the Cu Redistribution Lines

Chih-Chieh Tsai, Chih Chen

As technology continues to advance, there is a greater demand for personal electronic devices with improved performance. This has led to increased interest in fan-out wafer-level packaging, which offers higher interconnect density, better electrical characteristics, and improves heat dissipation. Redistribution layers (RDL) are utilized to route the high-density interconnections on the chip to the substrate's low-density connection points. In current 3D-IC packaging, the assistance of RDL is still required. As size decreases, the critical dimensions of the metal wires decrease, allowing for a reduction in the number of RDL while still providing multiple interconnections between chips. This enables a cost reduction in overall packaging. Recently, significant efforts have been made to replace aluminium with copper as the interconnect material for Si-ULSI devices. Copper offers several advantages, such as lower resistivity and higher reliability. It also exhibits greater Electromigration (EM) resistance. In particular, highly <111>-orientation nanotwinned (nt) copper not only has a lower resistivity compared to regular copper but also needs more time for oxidation. It has higher EM resistance, resulting in improved mechanical strength [1-5]. Furthermore, the (111) plane, being the most densely packed surface, has the highest diffusion rate of a face-centered cubic (FCC) crystal [6,7]. This characteristic allows for a reduction in bonding temperature from above 300℃ to 150℃. Lu et al. also discovered the extremely anisotropic grain growth (EAGG) characteristic in electroplates nt-Cu films [8]. Moreover, we can easily fabricate nt-Cu microbumps through electroplating, which effectively reduces the manufacturing cost and is compatible with semiconductor fabrication processes. This reveals the potential application of nt-Cu in the advanced packaging industry. In the back end of the line (BEOL) metallization schemes, TaN/Ta liner has been considered a reliable liner layer for Cu-low k integration. However, because of the poor adhesion between electroplated copper and the Ta layer, a Cu seed layer need to be deposited by PVD to solve the adhesion problem. In this study, the larger grain size and fewer grain boundaries are expected to exhibit better electrical properties characteristic of fore different copper variations in the RDL structure. In the structure, we will PVD a thin Ta liner as a diffusion barrier layer and a Cu seed layer to improve the adhesion. The four variations of copper to be electroplated include regular copper without any additives, highly <111>-orientation nt-Cu, copper with EAGG, and fine-grain copper with commercial additives.

展示攤位：PS1_13 (論文編號：TW0082)

3D Fan-Out Wafer Level Packaging with Embedded Chip

Chao kai Hsu

Fan-Out Wafer-Level Packaging (FOWLP) is a technology that enables the realization of shorter pathways and thinner packaging forms to meet the requirements of high performance and thinness. It is suitable for the heterogeneous integration of chips with different processes and characteristics, catering to the demands of mobile application processors, the Internet of Things (IoT), wearable electronic products, and more. This article reports further advancements using 3D-FOWLP technology, which enables chip stacking, thinning, and cost-effective structures. It features a low-risk process flow, low package warpage, stable electrical performance, and good reliability. The article addresses the challenges faced by fan-out heterogeneous packaging. It successfully achieves the integration of pre-fabricated layers with programmable switch chips, as well as the stacking of MCU, Flash, and BLE custom layers with heterogeneous chips. The warpage of the custom layer is controlled within 500m, and it passes reliability tests.

展示攤位：PS1_14 (論文編號：TW0098)

Tuning microstructures for fabrication of high strength Cu foils

Chen-Ching Lai

Because of the rise of electric vehicles, notebooks, and smartphones in recent years, all products require power to be used. Lithium batteries play an important role in them, more importantly, people will pay attention to the battery life and performance of the product, and then select the product. Copper has become the most important conductor material in electronic devices due to its high ductility and conductivity. In lithium ion batteries (LIBs), copper foil is used as an anode current collector, and copper foil is used as the substrate to coat the surface anode active materials and become the anode of the lithium battery. Anode-active materials mainly include carbon-negative electrode materials and non-carbon-negative electrode materials. At present, carbon-negative electrode materials such as graphite materials are mainly used for commercial applications in the market. When lithium batteries are charged and discharged, lithium will be stored in the negative electrode materials. When a lithium battery is charged, lithium atoms will ionize into lithium ions and electrons in the positive electrode, and then synthesize lithium atoms with electrons in the negative electrode. When discharging, lithium atoms will ionize into lithium ions and electrons on the surface of the negative electrode, and then form lithium atoms in the positive electrode. The negative electrode active material coated on the surface of the copper foil will react with lithium ions to produce compounds during the charge and discharge process of the lithium battery, causing volume expansion and then rolled into the copper foil, so the copper foil needs to have sufficient strength to withstand the volume change caused by the compound. In the past, the copper foil of lithium batteries used rolled copper foils, but it has been replaced by electroplated copper foils in recent years. Generally, the strength of rolled copper is about 400~550MPa, and the strength of electroplated copper is about 300~450MPa. The strengthening mechanism of electroplated copper includes following The purpose of strengthening is achieved by grain refinement, adding little metal elements, and other strengthening methods, but the electrical conductivity may be reduced, while nano-twinned copper can simultaneously increase the strength and avoid the problem of electrical conductivity decline. Nano-twinned copper is known to have high mechanical strength, good thermal stability, and resistance to electromigration. In this study, high-strength nanotwinned copper (nt-Cu) foils were fabricated by rotary electroplating. Two additives were used to improve the mechanical strength and the mechanical properties of copper foil were studied by manipulating the plating temperature and current density. The maximum tensile strength of the copper foil electroplated at room temperature is about 800MPa, and the yield strength is about 510MPa. Compared with the copper foil without additives plated by room temperature spin plating, the UTS is increased by about 60%, and the yield strength is increased by about 64%. Then we carried out electroplating in low-temperature and high-temperature environments respectively. In the low-temperature environment of 10°C, the ultimate tensile strength (UTS) of the copper foil plated with low current density can reach 870MPa, and the yield strength(YS) is 560MPa, while in the high-temperature environment of 35°C the UTS of the copper foil can reach 845MPa, and the yield strength is 540MPa. Both copper foils have a microstructure of fine-grained nano-twinned copper.

展示攤位：PS1_15 (論文編號：TW0107)

Biaxial-Bending BoR Test for Thin Silicon Die and Its Comparison to PoEF Test

Po Jen Hsieh

The three-dimensional integrated circuits (3DIC), stacked-die, or wearable electronics packages gain increasing popularity in system or subsystem packaging applications for ensuring small size, low-profile features, high-pin count, high performance, low power consumption, or flexibility. In such applications, the silicon wafers of integrated circuits (IC) need to be thinned to their target thicknesses, typically in the range of 10 μm to 150 μm. The strengths of the silicon die cut from the wafers must be characterized after wafer thinning and sawing processes to fulfill the package design requirements in order to satisfy short-term manufacturing yield and long-term reliability. The ball-on-ring test (BoR) suggested in ASTM F394‐78 is one of the most popular standard tests for biaxial bending. This paper aims to demonstrate the biaxial bending strength test on thin silicon dies using the classic BoR test and then discuss it in detail by comparing those results with the newly-proposed point load on elastic foundation (PoEF) test. The geometric linear and nonlinear solutions to the BoR test will be reviewed and provided with theoretical and numerical formulations, respectively. The test results will be compared thoroughly with the published data from the PoEF test in terms of bending strengths, load-displacement curves, and failure modes. Via this study, it has been proved that the bending strength data from both tests are quite consistent for the regularly thin dies (with thicknesses of 82 μm and 57 μm) but apparently different for the ultra-thin dies (with a thickness of 42 μm). The lower strength data obtained in the BoR test was found to be caused by its suffering the more pronounced local buckling effect than the PoEF test. Based on the results of this study, although both tests are identical for the regularly thin dies, the PoEF test still provides a better and more reliable method than the conventional BoR test for testing the ultra-thin silicon dies.

展示攤位：PS1_16 (論文編號：TW0110)

Warpage Prediction Model Establishment of Multi-Chip Fan-Out Wafer Level Packaging for Antenna-in-Package

Wen-You Jhu, Ming-Yuan Chen, Hsien-Chie Cheng, Tao-Chih Chang, Yu-Min Lin, Ching-Kuan Lee, Hao-Che Kao

To meet the needs of millimeter wave (mmWave) communication applications in the 5G generation [1], it is necessary to integrate internal electronic components such as antennas, power amplifiers, and transceivers. Due to limited internal space constraints, there is an increasing demand for heterogeneous integration (HI) technologies like System-in-Package (SiP) [2], Antenna in Package (AiP) [3], and Antenna on Chip (AoC) [4]. However, HI technology faces several technical challenges, including warpage, thermal performance, and reliability that need to be addressed. Among them, the warpage caused by the coefficients of thermal expansion (CTE) mismatch between different components is particularly important. If the warpage is too large, it will lead to a deviation in the placement position during the subsequent antenna placement and chip bonding process, resulting in signal interference, empty soldering and short circuits, which can adversely impact the reliability verification process and product yield. Since the technology integrates several functional dies into a single package, the distribution of circuits in the redistribution layer (RDL) is extremely complex and has a dramatic impact on warpage behavior. Therefore, it is extremely important to accurately understand the thermomechanical behavior of RDL. In the past, most studies have used the finite element analysis (FEA) method to establish a process warpage model and verify it with experiments [4,5]. However, this method requires extensive knowledge of mechanics, finite element analysis skills, and considerable time for modeling and analysis. Due to the increasing complexity of packaging structures, development times are becoming longer. In order to shorten the time to market, it is necessary to develop a more efficient and accurate warpage analysis method for evaluating the process-induced warpage of package. The purpose of this study is to investigate the warpage behavior during the fabrication process of an AiP module which is designed by industrial technology research institute (ITRI) using a multi-chip fan-out wafer level packaging (FOWLP) architecture. To achieve this goal, a process simulation framework combining FEA, effective modeling, and the element death/birth method is introduced. Meanwhile, a process warpage prediction model is constructed by combining process simulation and artificial neural network (ANN) algorithms to evaluate the package warpage quickly and effectively for design optimization [6-8]. Package warpage is strongly influenced by the RDL in the structure because it contains a large amount of complex copper (Cu) trace with a high Young's modulus and CTE. In order to effectively grasp the thermomechanical properties of RDL, the geometrical characteristics of complex Cu traces and vias in electronic computer-aided design (ECAD) are captured by the manual trace mapping technique, and the equivalent material properties of RDL are calculated through FEA [9]. It is worth noting that this method can treat RDL as an orthotropic as well as an anisotropic material constitutive assumption, and can obtain a complete elastic material matrix for more detailed and accurate process-warpage simulation [10]. To verify the effectiveness of this effective modeling method, axial tensile and heating tests are carried out on the RDL, and the displacement results are compared with those using the conventional volume-averaging method. Table 1 presents the displacement comparison results. Clearly, the method combined with the mapping technique provides better results than the volume-averaging method. This is due to the fact that the volume-averaging method ignores the effects of in-plane heterogeneity and material anisotropy on the mechanical properties. After calculating the equivalent material properties of the RDL, the RDL and the dielectric layer are further equivalent to a single block to reduce the complexity of the finite element model and improve the calculation efficiency while still maintaining the solution accuracy, as shown in Fig. 1. The 3D FE model of the multi-chip FOWLP structure is shown in Fig. 2 and the fabrication process of multi-chip FOWLP is shown in Fig. 3. The main process steps are the RDL process (Cu plating, and dielectric material coating), Die bonding, underfill curing, molding material curing, grinding, secondary RDL process and de-carrier, respectively. The validity of the numerical analysis model will be verified by comparison with experimental measurements. Through parametric analysis, the influence of various geometric and material factors in FOWLP on process-induced warpage is explored, and key factors affecting warpage behavior are identified. These key factors will be further used to construct the database required for the warpage prediction model. The prediction accuracy and training performance of a prediction model depend on the degree of adaptation of its hyperparameters. Selecting appropriate hyperparameters can not only prevent overfitting, but also improve model convergence and prediction accuracy. Therefore, this study will adjust the hyperparameters in the predictive model through the Taguchi method-based hyperparameter optimization [11, 12]. Through the use of a reliable prediction model, developers are able to assess warpage effectively and efficiently during the initial design phase, which will enable them to optimize the design to reduce warpage, and facilitate subsequent processes such as the secondary RDL process.

展示攤位：PS1_17 (論文編號：TW0115)

Mechanical Evaluation for Recycle Solution of 12 Inch Fan-Out Glass Carrier

Fila Tsai, Karen Chen, Sean Shin, Wei-Hong Lai, Golden Kao, Alexcc Wang, CP Hung

Fan-Out process and silicon wafer grinding. Considering the cost saving purpose, the glass carriers are reused over and over between manufacturing processes. In general, the reprocessed glass carriers will suffer serious mechanical and physical strength reducing problems caused by chemical etching, thermal aging and mechanical scrape in processes, and plus additional damage in the following glass cleaning stage. Disregard of the problems will finally bring highly silicon wafer broken risk during certain process cycle. To get a reasonable recycle time assessment of 12 inch glass carrier, firstly this research evaluates out-of-plane warpage and in-plane displacement at multi-temperature environments through advance Metrology Analyzer (aMA) measurement which is based on 3D Digital Image Correlation (3D-DIC) technology. It is popular used for full-field behavior analysis and calculate the in-plane Coefficient of Thermal Expansion (CTE). The preliminary result shows slightly difference of CTE and warpage between fresh and recycle glass. Additionally, measured the broken strength of 12 inch glass carriers between mechanical and chemical type cleaning processes via four-point flexural bend test method to find out the relation of broken strength decreasing rate by recycle time, finally to indicate a suitable 12 inch glass carrier cleaning calculation flow and the recycling cycle upper limit for manufacturing factory reference.

展示攤位：PS1_18 (論文編號：TW0121)

HIGH-POWER PROCESSOR Cavity Capacitors Correlation for Power Delivery Optimization

Kevin Liang

Considering power delivery network (PDN), processor cavity capacitors quantity with suitable location is key factor of frequency domain to against power virous current occurred. This paper helps review power delivery network by real processor socket pins measurement and create a methodology to optimize cavity capacitors configuration in Intel server platform design.

展示攤位：PS1_19 (論文編號：TW0124)

Low-Temperature Cu Bonding Using Nanocrystalline and <111>-oriented Combined Surface in Fine-pitched Level

Chen-Ning Li, Jia-Juen Ong, Wei-Lan Chiu, Shih-Chi Yang, Hsiang-Hung Chang, Chih Chen

To date, highly <111>-oriented nanotwinned copper (NT-Cu) has been found highly potential to adopt as interconnect in fine-pitched hybrid bonding due to the lowest oxidation rate and highest surface diffusivity. As the dimension of Cu microbumps keep shrinking, the area fraction of unwanted sidewall is raised and caused NT-Cu hard to scale down in the near future. However, the nanocrystalline Cu (NC-Cu) with a smaller grain size (<100 nm) contributes to significant grain boundary diffusion leading to a promising bonding quality. Furthermore, higher internal energy can serve as a driving force of grain growth in Cu-to-Cu direct bonding process. Therefore, NC-Cu is considered as a highly deployable copper interconnects in advanced packaging technology. However, NC-Cu is usually fabricated by PECVD recently. In order to reduce the thermal budget and process time, we tried electroplating since it had higher throughput and no limitation on process ambient. The fine-pitched hybrid structure was fabricated using a damascene process, and then DC electroplated in copper sulfate solution on a Tantalum (Ta) adhesion layer. The pitch and diameter of the NC-Cu microbumps were 20 m and 10 m, respectively. The top and bottom dies were planarized sequentially by the CMP process and the dishing between the Cu and SiO2 layer was controlled within 5 nm. The plan-view electron backscatter diffraction (EBSD) results showed that the grain size was around 90 to 120 nm, and smaller grain could be obtained under low temperatures with high current density. However, the results are yet to be called nanocrystalline which is generally defined as a grain size smaller than 100 nm. Thus, we changed the electroplating waveform to pulse-reverse (PR) in order to increase <111> ratio of the surface. The <111> surface ratio for PR plating is around 60%, and the non-<111> area is mostly attributed to the sidewall with random orientation. Therefore, we carried out a combined bonding mechanism by using both highly-<111> and nanocrystalline sidewalls to accomplish bonding with better bonding quality. The thermal compression bonding (TCB) was conducted at 200°C for 1 h in a vacuum ambient with a compressive pressure of 20 MPa. To observe the microstructure and bonding quality of the interface, cross-sectional analysis was executed by using a focused ion beam (FIB) and scanning electron microscope (SEM). The bonding quality was then quantified by die shear test. We compared the results with conventional Cu, and it showed that the bonding strength of combined surface Cu with <111> and nanocrystalline structure was the highest in shear strength, which indicated that the combined mechanism was a feasible method for fabricating copper microbumps with better quality and reliability.

展示攤位：PS1_20 (論文編號：AS0130)

Printed Circuit Board (PCB) Design Electrical Characterization and Optimization in Immersion Cooling Environment

Huafang Ju; Mengen Zan; Shaozheng Hou; Jimmy Hsu; Yinglei Ren; Yuanming Hu; Yibo fan; Lili Deng

Immersion cooling is gaining significant traction and emerging in many scenarios to improve cooling efficiency. Electrical characterization of information technology (IT) components may be affected from air cooling to immersion cooling. This paper focuses on immersion cooling impact on PCB, especially microstrip line through modeling, simulation, and measurement. At the same time, optimization method is addressed for microstrip line design in immersion cooling.

展示攤位：PS1_21 (論文編號：EU0135)

Ideal flow design of the bending of bi-material sheets

Marina Rynkovskaya

The ideal flow theory is an efficient tool for the preliminary design of metal forming processes. The class of plane strain solutions for rigid perfectly plastic models is called ideal flow solutions if the principal stress trajectories are material lines throughout the deformation process. This condition is an extra equation to the conventional system of constitutive equations. Therefore, the overall system is overdetermined. Nevertheless, this system is compatible, though some restrictions on boundary conditions apply. In the case of non-stationary processes, an ideal flow solution determines a loading path that ensures the ideal flow condition is satisfied. Usually, the solution is not unique. Therefore, additional design criteria may be used to achieve uniqueness. According to the review of the theory almost all bulk ideal flow solutions have been found for stationary processes. An exception is the process of bending under tension. All these solutions are for homogeneous materials. They are based on the general theory of bending under tension. This general theory applies to inhomogeneous materials, including bi-metallic sheets. The present paper extends the existing solution to such sheets. This new solution is based on the theory of bending under tension. The solution is in closed form, though it is cumbersome. Therefore, it is straightforward to use it for the preliminary design of the process. The present paper adopts the sheet's final inner and outer radii as additional design criteria. However, other criteria can be used with no difficulty. The loading path that ensures the desired configuration is produced under the ideal flow conditions. It has been found that some loading paths require negative values of the tensile force. In summary, the specific design assumes that a desirable shape at the end of the process is given. Two process parameters control this shape. One of these parameters is the Lagrangian coordinate of the curve where the equivalent strain rate vanishes. The other is the maximum value of a (i.e., the instant when the process should be stopped). The variation of these parameters for several desirable shapes is shown in the paper. After determining the process parameters, one must find an ideal flow part. Several paths are illustrated in the paper. The solution provides a design of the bending process of bi-material sheets driven by geometric parameters of the final configuration of the sheets. The loading paths that transform the initial configuration into the desirable final configuration without violating the ideal flow conditions have been found. Some loading paths require negative values of the tensile force. As a result, the pressure applied over the inner radius is also negative. Therefore, such loading paths are not feasible for practical use. Nevertheless, the solution can be easily modified by adding a uniform hydrostatic pressure to compensate for the negative pressure over the inner radius.

展示攤位：PS1_22 (論文編號：TW0137)

Photo-imageable White Dry Film for Mini/Micro-LED

Chen-Cheng Yu , Ming-Tzung Wu, Shuang-Huei Chen, Yao-Jheng Huang, Te-Yi Chang

Display products are inseparable from life, and traditional technologies are no longer able to satisfy consumers’ desire for vision, prompting developers to explore the possibility of producing displays with higher specifications. The next generation of display technology, Mini/Micro-LED, offers high contrast, high brightness and low power consumption, and is even more cost effective than OLED. These advantages have made it one of the projects that many manufacturers are striving to develop. In order to achieve the high-contrast requirement, the backlight module is the one of the most critical components. An ideal solution is to use a photo-imageable white dry film solder resist that is compatible with current printed circuit board (PCB) manufacturing processes using dry film lamination and lithography. However, there are many challenges to white dry film development. Some necessary functional materials may cause ink instability. Due to the interaction of materials, temperature change, and particle density, the dispersed ink materials are prone to phase separation and aggregation, resulting in incomplete curing, poor developability, and poor weather resistance. In this research, photo-imageable white dry film solder resist has developed. The white solder resist ink contains the modified resin, pigment, reactive oligomers, functional monomers, photosensitizers, additives, dispersants, etc. To improve weather resistance, the resin is modified by introducing anhydride bonding structure, and has molecular weight (Mw) 5000-10000, PDI≦2.0, and viscosity≦20,000cps. After formulating, the prepared ink material is coated and processed into a white dry film. The developed white dry film has excellent bendability, high resolution (L/S ≦100um), 88% reflectivity and 2.0 b* value at 50um thickness. And it also passes adhesion test 100/100 and reflow test 288°C/10 sec for 3 cycles without peeling damage. he white dry film solder resist in this research not only has developability, but also demonstrated excellent properties such as flexibility, high reflection and low yellowing for integration. In addition, both delivery time and cost can be greatly reduced through dry film process, bringing acceleration on the development of Mini/Micro-LED. The resin can also be introduced with double bonds, long carbon chains and functional groups for high-frequency applications to meet the requirement of millimeter wave components.

展示攤位：PS1_23 (論文編號：TW0139)

Low Temperature Cu-to-Cu Bonding for Heat Pipe Application

Guan-You Shen

In the past few years, portable electronic devices have the trend of being light, thin, short, and small. However, the need to dissipate a large amount of heat within limited space has become a critical issue. Heat pipes have emerged as a simple and effective solution. To meet the demand for size reduction, traditional heat pipes need to be designed to be lighter and thinner. In response to this, ultra-thin heat pipes (UTHP) and micro heat pipes have been developed. Unlike traditional heat pipes that utilize cold rolling processes, the fabrication of ultra-thin heat pipes and some micro heat pipes involves techniques such as laser welding and diffusion bonding to accommodate small, precise, and uniquely shaped designs. Integrating heat pipes with other materials is also a method that further reduces volume and weight. For example, combining heat pipes with highly toughness polymer materials is a good choice. However, the glass transition temperature of polymers is much lower than the temperature range (600-800 degrees) typically used in diffusion bonding. Therefore, reducing the bonding temperature while not increasing the bonding time is crucial. Electroplated nanotwinned copper (NT-Cu) with a highly preferred orientation of <111> is an excellent solution. The <111> surface has the highest diffusivity, more than three times that of other surfaces, enabling copper-copper bonding to be achieved at lower temperatures and shorter times. By electroplating nanotwinned copper and subsequent chemical mechanical polishing or electropolishing for surface planarization, the <111> preferred orientation can be enhanced from 2.7% to 50%. Under the bonding condition of 250 degrees for 30 minutes, a bonding strength of over 30 MPa can be achieved. In comparison, samples without electroplated nanotwinned copper cannot achieve successful bonding under the same conditions. This process significantly reduces the bonding temperature without increasing the bonding time. Therefore, we designed simple heat pipe samples(figure 1) and conducted helium leak tests. After the helium leak test, the most extreme parameter was a downforce of 50 MPa at 300 °C for 30 minutes. Both chemical mechanical polishing and electropolishing were successful, maintaining a leakage rate of 10-12 torr/s. In contrast, without electroplated nanotwinned copper, the leakage rate for copper bonding under the same conditions increase exaggeratedly to 10-2 torr/s, causing the heat transfer fluid inside the heat pipe to escape during vaporization, resulting in the loss of heat dissipation functionality. The results of the helium leak test clearly demonstrate the effectiveness of this technology in reducing the bonding temperature of heat pipes, making it highly suitable for the development of lightweight and thin heat pipes.

展示攤位：PS1_24 (論文編號：TW0146)

Electromigration Reliability of Micro Joints with ENEPIG Surface Finish

Zhao-Yu Yang, Shun-Cheng Chang, Chih-Tsung Chen, Hung-Cheng Liu, Kuo-Hsing Lan, Pin-Chung Lin, and Cheng-En Ho

The continuous pursuit of multiple functions in the ultrathin electronics causes a significant increase in the number of micro joints with a substantial decrease in the joint size. In terms of chip-carrier boards for high-end chip packaging applications, the number of micro joints can be more than 10000/unit with a joint size as low as below 90 μm (diameter, djoint) today . With djoint decreasing from 500 μm (traditional BGA scale) to below 100 μm, the current density (j) in the power solder joints inevitably increases to orders of magnitude larger than that in traditional ones (djoint ≈ 500 μm) because j inversely increases with the square of djoint. A remarkable atomic transport might be induced by such a high j (generally termed as electromigration), threatening the electrical/mechanical reliability of microelectronic products. Electromigration-induced joint failures mainly involve a series of void propagation along the solder/pad interface, local solder melting, serious pad’s depletion, and substantial intermetallic compound(s) formation. In recent years, numerous researchers had predominantly devoted their efforts to the modifications of joint geometry, solder alloy, and surface finish, to enhance the electromigration resistance of micro joints. However, only limited data regarding the reliability of advanced tri-layer finish, electroless nickel (Ni-P)/electroless palladium (Pd-P)/immersion gold (Au) (ENEPIG) [6]. For ENEPIG, the surface layer Au (IG) is for oxidation resistance and can greatly increase the wettability between solder and pad. The electroless Ni(P) (EN) behaves a diffusion barrier, effectively preventing out diffusion of Cu to the Au surface. The insertion of a submicron-thick electroless Pd(P) (EP) between Au and Ni(P) avoids the undesired galvanic corrosion over the Ni(P) finish resulting from the Au plating process (black pads). The focus of this study is to investigate the electromigration reliability of micro joints with ENEPIG through finite element analysis, electrical and microstructural characterizations. Experimentally, two types of surface finishes, organic solderable preservative (OSP) and ENEPIG, were employed for the joint’s electromigration test. Fig. 1 shows the schematic illustration of micro joints utilized in this study: (a) OSP/Sn-0.7Cu/OSP; (b) ENEPIG/Sn-0.7Cu/ENEPIG; (c) OSP/Sn-0.7Cu/ENEPIG. The thickness of OSP was 0.3 µm and that of Au/Pd(P)/Ni(P) (ENEPIG) was 0.1 µm/0.1 µm/5 µm. The diameter of Sn-0.7Cu joints was 70 µm and that of Cu pad was 65 μm. Upon electron current stressing test at 150 °C, a 0.422-A direct current was applied to a series of micro joints, producing an average current density of 104 A/cm2 at the solder/pad contact window (65 μm in diameter) and a detectable temperature rise (+3 °C) of solder surface due to Joule heating. The results of the current stressing test showed that serious depletion on the Cu pad and Ni(P) finish might be caused at the entrance of micro joints due to the current crowding effect. Interestingly, moderate electromigration-induced joint damages with higher electrical resistance were obtained with the ENEPIG surface finish, reflecting that the Ni(P) finish can act efficient diffusion barrier although it possesses a higher resistivity than Cu. The research results indicated that the type of surface finish plays a crucial role in the electromigration reliability and an appropriate surface finish can efficiently advance electrical/mechanical characteristics of micro joints.

展示攤位：PS1_25 (論文編號：AS0151)

All-GaN HEMTs and Planar Transformer Based 48V Voltage Regulator Common Module (VRCM) Design

Shijuan Qin, Feng Huang, Zhiwei Huang , Ariel Guo, Weijie Yuan, Horthense D. Tamdem , Bryant Tsai

An GaN (Gallium Nitride) based 48V to 12V Voltage Regulator Common Module (VRCM) is proposed on this paper for datacenter 48V rack. To achieve higher power density a single core integrated planner transformer is also proposed. Last, the prototype of 1MHz 1kW module is demonstrated, peak efficiency of 98.27% with 54V Vin and power density of 1000W/inch3 are achieved.

展示攤位：PS1_26 (論文編號：TW0162)

Numerical Study of the Angle Effect of Vortex Generators on Thermal Hydraulic Performance at Low Reynolds Number

Jin-Cherng Shyu

Vortex generator has been proven to enhance the heat transfer coefficient of air-cooled fins without significantly increasing the flow resistance. By inducing secondary flow on the heat transfer surface, it interferes and destroys the development of the thermal boundary layer along the wall. Fiebig et al. [1] studied the vortex generators of delta winglets and rectangular winglets. It was found that each vortex generators had the best heat transfer performance with angle of attack of 60°. At a given Reynolds number, the heat transfer performance of the delta wing was the best. Wang et al. [2] used a water tunnel to measure the performance of rectangular wing at varying arrangement and water flow direction with an attack angle of 50°. The experimental results showed that the reverse flow performance of inline arrangement was better than that of forward flow. The pressure drop depended only on the density of the vortex generator. Leu et al. [ 3 ] installed delta winglets on the surface of the fin-tube heat exchanger and performed the flow visualization to compare the results obtained by 3-D numerical simulation. When the wind speed ranged from 0.5 to 3 m/s, the heat transfer coefficient was the highest at an angle of attack of 60°. Using the VG1 heat exchanger performance evaluation method, it was found that the heat transfer area can be reduced by 25% with the angle of attack of 45°, yielding the best performance. In addition to the angle of attack, the angle between VG and the bottom plate, the inclination angle, has begun to be noticed and discussed. Khan and Li [ 4 ] used three-dimensional numerical simulation to analyze and optimize the design of the delta winglet pair and rectangular winglet pair on flat plates. The effects of attack angles, inclination angles and Reynolds numbers were discussed. The results pointed out that, when the inclination angle of the rectangular winglet pair was 60°, the Nusselt number was the highest compared with other inclination angles. However, for the delta winglet pair, the Nusselt number increased with the increase of the inclination angle, and the optimal inclination angle was 90°. It was also pointed out that the angle of attack yielding the best heat transfer performance was 45° and 60° for the rectangular winglet pair and the delta winglet pair, respectively . Yang et al [ 5 , 6 ] found that if the fin spacing is too low, the vortex could be suppressed, especially at low Reynolds number. As the fin spacing was 1.68 mm, the thermal performance was the best. Four types of heat sinks, including flat plate, interrupted fin, fin with dense vortex generators and loose vortex generator arrangement were tested at low Reynolds number. The results showed that the performance of most cases was even lower than that of flat plates at low frontal air velocity, because the discontinuous conduction path resulted in a decrease in heat transfer performance. Various parameters that affect the performance of VG have been discussed in the literature. From the above literature survey, it can be found that the shape of VG is an important factor affecting the vortex strength, and the delta winglet pair is the most effective type of vortex generator that can enhance heat transfer with favorable angle of attack between 45° and 60°. The effect of the angle of delta winglet pair on the thermal and hydraulic performance at low Reynolds number is of great importance. However, it is rarely discussed at present. therefore, the objective of this study is to discuss the effect of angle of attack on the heat transfer and fluid flow of delta winglet pair at Reynolds numbers less than 800 by means of three-dimensional numerical simulation. Nusselt number, friction factor and thermal enhancement factor (TEF) were used to evaluate the performance of those delta winglet pairs (DWP). The results showed that the DWP with an inclination of 30° showed the lowest Nesselt number enhancement compared to a flat plate at a given angle of attack. As the angle of attack of DWP was 30°, the Nesselt number was the highest among all. With Reynolds number of 783, the Nusselt number was 1.3 times higher than that of plain flat plate. The highest TEF was 1.07 when the angle of attack of the DWP was 30° at Re number of 783.