Sessions Index

Bio:

Dr. Andrew Tay is currently an Adjunct Professor in the Department of Electrical and Computer Engineering, National University of Singapore (NUS) and a Visiting Scientist at the Singapore Hybrid-Integrated Next-Generation μ-Electronics Centre (SHINE), NUS. Prior to this he was a Professor of Mechanical Engineering at NUS. He obtained his B.E. (Hons I and University Medal) and PhD in Mechanical Engineering from the University of New South Wales, Australia. His research interests include electronics packaging (thermo-mechanical failures, delamination, effects of moisture, solder joint reliability); thermal management of electronic systems and EV batteries, infrared and thermo-reflectance thermography, solar photovoltaics reliability, and fracture mechanics.
He is currently a member of the Board of Governors of the IEEE Electronics Packaging Society (EPS), the EPS Director of Chapter Programs, and a Distinguished Lecturer of EPS. He was the inaugural General Chair of the 1st Electronics Packaging Technology Conference (EPTC) in 1997 and currently the Chairman of the EPTC Board. He was awarded the 2019 IEEE EPS David Feldman Outstanding Contribution Award, the 2012 IEEE CPMT Exceptional Technical Achievement Award, and the 2012 IEEE CPMT Regional Contributions Award. For his outstanding contributions in the application of engineering mechanics to electronics and/or photonics packaging, he was awarded the ASME EPPD Engineering Mechanics Award in 2004. He was also awarded an IEEE Third Millennium Medal in 2000. He is a Fellow of ASME and a Life Fellow of IEEE.

Abstract:

Shrinking features and growing device complexity in today’s advanced devices have led to increased challenges in characterizing the thermal behaviour of these devices and their failure. With higher power densities, having a full understanding of the static and dynamic thermal behaviour of the devices is essential for ensuring optimal trade-offs between performance and device reliability. With sub-micron devices, the challenge is even greater as high spatial and temporal resolutions are required. In this presentation, some of the latest techniques of thermal analysis will be described and compared. Two popular non-contacting techniques will be dealt with in greater detail. It was found that thermoreflectance thermography can best meet the challenges imposed by these advanced devices by providing sub-micron spatial resolution and temporal resolution in the picosecond range. When failures occur in a device, a hot spots are usually generated. Thermal analysis can be used to determine the location of hot spots and hence aid in the failure analysis of the device. It can also help to characterize the thermal behaviour, thermal properties, and the thickness of thin films in the device in situ and non-destructively. Using a novel quantum spin crossover
(SCO) material, electromagnetic power intensity can be correlated with temperature. Hence,via a SCO coating, a thermal imaging system can be adapted to characterize the electromagnetic power intensity field of antennas in a much quicker and cheaper manner than current methods. Several case studies will be presented.

 

Bio:
Susmita Mistri is currently pursuing a Ph.D. in the International Program in Photonics at the College of Electrical and Computer Science Engineering, National Yang Ming Chiao Tung University, Hsinchu, Taiwan. She is affiliated with the Institute of Electro-Optical Engineering. Her research focuses on power semiconductor circuit design, high-speed PCB layout, and wide-bandgap devices, particularly GaN and SiC technologies. Her current work involves evaluating the switching characteristics of GaN transistors in advanced converter topologies for high-frequency, high-efficiency power applications.

Abstract:
The ongoing advancements in wide-bandgap semiconductors (WBG), particularly Gallium Nitride (GaN) power devices, have opened new possibilities in high-efficiency, high-frequency power conversion. GaN transistors offer remarkable advantages over traditional silicon-based (Si) MOSFETs, including lower switching losses, faster transition speeds, and improved thermal performance. To fully exploit these advantages in practical converter designs, it is essential to rigorously characterize their dynamic switching behavior under realistic operating conditions. This study presents an experimental evaluation of GaN device switching using a double pulse test (DPT) embedded within a DC-DC Fly-Buck converter topology. The objective of this work is to evaluate GaN switching characteristics under realistic converter stress conditions, rather than in an idealized test environment. The Fly-Buck converter is a modification of the traditional synchronous buck converter that provides isolated outputs through a coupled inductor. It offers a useful platform for evaluating switching devices, as it reflects many real-world effects, such as parasitic elements and coupled magnetic behavior. The test circuit applies a gate-source voltage (VGS) of -3.8V to 6V, typical for low-voltage GaN operation, while the drain-source voltage (VDS) of 50V represents isolated DC-DC converter applications. The double pulse sequence was carefully configured: a first pulse includes a 10 µs initial pulse (T1) to charge the inductor current, a 2.5 µs dead time (T2) allowing the energy to transfer and freewheel, followed by a 2.5 µs second pulse (T3) to trigger the transistor’s turn-on switching under load current conditions. This timing isolates the switching event, allowing accurate observation of transient behavior.
During testing, high-speed measurements of gate-source voltage, drain-source voltage, and current waveforms were captured to observe switching transients such as turn-on delay, turn – off delay, voltage overshoot, voltage ringing, current rise time, and reverse recovery effects of the output rectifier. The results showed that the GaN device switched cleanly and quickly, with minimal energy loss and low levels of overshoot. Fast switching also reduced the stress on the output diode, improving overall circuit performance. Additionally, the fast-switching speeds minimize diode reverse recovery, thereby reducing switching stress and improving overall converter efficiency. The use of a DC-DC Fly-Buck converter as a test platform offers several advantages, including realistic parasitic effects and device stress conditions, which are often absent in isolated device tests. This approach ensures the measured data is highly relevant for actual power converter designs. Furthermore, this work addresses practical challenges such as managing PCB layout parasitics and ensuring clean gate drive signals, which are protecting the device during high-speed switching. The study of Fly-Buck-based double pulse test (DPT) method provides a robust and application-relevant approach for characterizing GaN transistor switching behavior. These findings support the use of GaN technology in compact, high-frequency isolated converters and play a key role in advancing next-generation power supplies with higher efficiency and power density, driving progress in modern power electronics.

 

Bio:
Yi-Chun is currently a 2nd year MS student in the Department of Mechanical & Electro-mechanical Engineering at National Sun Yat-sen University. Her research project focus on understanding the relationship between laser parameters to the dicing quality of 4H-SiC, using a combination of microstructural and micromechanical characterization techniques. This work was funded by ASE and partly NSTC.

Abstract:
Silicon carbide (SiC) in its 4H hexagonal structure is an emerging semiconductor material with excellent thermal, mechanical, and electrical properties. However, due to its high hardness, SiC wafer is also extremely difficult to cut via conventional mechanical methods due to rapid wear and surface damages from the diamond blade. Therefore, a laser-based non-contact technique were developed for dicing the SiC wafer more efficiently but also precisely.
This study focuses on establishing the relationship between laser scribing parameters (speed, power, and frequency) with dicing quality (surface roughness, fracture strength, and Weibull modulus) using a combination of microscopy and mechanical testing techniques.
We first analyzed how the depth and tip distribution of the laser-induced grooves affect the fracture surface roughness. The stress values obtained from the three-point bending tests were then subjected to Weibull analysis, through which we explored the correlation between the statistical parameters and the quality of the resulting fracture surfaces. As shown in Figure 1, varying laser scanning speeds result in different groove depths and fracture surface roughness. Higher laser speeds tend to produce more distinct and uniformly distributed tip features. According to the data in Figure 2 and Table 1, specimens processed at higher laser speeds exhibit improved Weibull plots, indicating that fracture can be initiated under a lower applied load (σth), while achieving higher average fracture stress (σavg) and reliability (Weibull modulus, m)
Experimental results indicate that deeper grooves with sharper and more uniformly distributed tip features lead to improved fracture surface roughness quality. The statistical parameters obtained from Weibull analysis further reveal the differences caused by varying laser scanning speeds and demonstrate a clear correlation with surface roughness characteristics.
The findings of this study contribute to enhancing the cleaving quality of semiconductor wafers and improving surface integrity and process stability. Moreover, the Weibull analysis method adopted here is broadly applicable to other material systems, providing a scientific basis for evaluating and improving the stability, reliability, and performance of manufacturing processes.

 

Bio:
Ayumi Saito was born in Osaka, Japan, in 1999. She received the bachelor's degree in engineering science from Kyoto University, Kyoto, Japan in 2022, the master's degree in micro engineering from Kyoto University, Kyoto, Japan, in 2024. She is currently a group member of the reliability technology group, ROHM company Ltd., Kyoto. Her current research topic includes the study of mechanical properties of epoxy resin for improving the reliability of the power modulus.

Abstract:
We investigated changes in the tensile mechanical properties of EMCs at 150°C by creating different oxidation levels. Please refer to the attached PDF file for the details.

 

Bio:
Ji-Min Lin born in Taichung, Taiwan, in 1985 and received the B.S. and M.S. degrees of Electrical Engineering, National Sun Yat-Sen University, Kaohsiung, Taiwan in 2009. He is currently working in the RF and Signal integrity simulation design field with 15 years of experience for USI, Universal Global Scientific Industrial Co., Ltd

Abstract:
This paper presents an effective approach for identifying the root cause of design issues in power module layouts through physical modeling. The study begins with a design case involving high switching loss and waveform ringing issues in a SiC-based power module, which is more sensitive to parasitic effects induced by the PCB layout due to its faster switching speed compared to IGBT-based power modules. To address this issue, we introduce a physical modeling methodology—commonly used in RF circuit analysis but relatively new in the field of power module design. This method enables engineers to analyze equivalent circuits by mapping them directly to the physical layout and understanding the impact of layout-induced parasitic effect.
Equivalent circuit modeling can generally be categorized into two types: numerical modeling and physical modeling. Numerical modeling is typically generated by simulation software, accurately representing frequency response and providing precise simulation results of circuit behavior. However, it is often difficult to figure out the location of design issues.
To overcome this challenge, we propose a physical modeling methodology that maps PCB layout structures directly to equivalent circuits. This approach helps designers visualize and quantify parasitic inductance and resistance in shared paths between control loop and power paths. Through simulation using a PCB model created by the physical modeling method, we demonstrate that parasitic inductance (Ls) in shared paths is a key factor contributing to increased Eon/Eoff switching losses and voltage ringing. In the SiC power module design, the high-side switching path exhibits nearly three times the parasitic inductance compared to the low-side, resulting in high switching loss issue.
The construction of the equivalent circuit is based on actual current flow. Each circuit element is calculated step-by-step using Z/Y matrix at switching frequencies. This process allows designers to trace current flow paths and identify layout-induced design issues. Based on acceptable switching loss, we define a threshold for the parasitic effect in critical paths and establish design guidelines for layout optimization. In order to avoid this issue completely, we propose the Kelvin connection to separate the control loop from the power path.
This study provides a comprehensive design flow for power module, particularly for SiC-based designs, which are more sensitive to layout-induced parasitic effects due to their faster switching speed. The proposed flow identifying the location of layout-induced issues, defining parasitic thresholds for critical paths, defining design guidelines for layout optimization, and finally proposing good circuit architectures.

 

Bio:
Keisuke Wakamoto was born in Hyogo, Japan, in 1989. He received the B.S. degree in applied physics from the Tokyo University of Science, Tokyo, Japan, in 2013, the M.Eng. degree from Kyoto University, Kyoto, Japan, in 2015, and the Ph.D. degree in engineering from the Kyoto University of Advanced Science, Kyoto, in 2023. He is currently the Group Manager of the Reliability Technology Group, ROHM Company Ltd., Kyoto. His current research interests include die attachment reliability studies by mechanical testing.

Abstract:
We attempted to suppress the CCM by intentionally creating anisotropic porosity in the horizontal direction of the sintered silver (s-Ag) die layer using two pressing methods. "FP" and "LP" refer to the s-Ag formed by pressing the entire top surface of a die attached assembly (DAA) or the SiC chip of a DAA, respectively. The applied force was adjusted to 60 MPa pressure on the pressed area. After DAA process, the DAAs were encapsulated with EMC using thermocompression. The relaiabitly testing methodologies used here were thermal shock tests (TST) and nine point bending tests (NBT). Scanning tomography images after 500 cycles of TST and NBT showed that the LP reduced the inner degradation ratio by up to 21.1% compared to the FP. Cross-sectionalscanning electron microscopy revealed that the FP progressed cracking in the s-Ag die layer, whereas the LP showed no evidence of cracking. The research results demonstrated that our anisotropically porous s-Ag is more reliable than an isotopically porous s-Ag.

 

Bio:
Dr. Yan-Cheng Liu is also the S8 Session Chair, who has long been dedicated to power module packaging topology design, reliability analysis, power system conversion, and power management technology development, and has made significant contributions to the field of power electronics research.

Abstract:
This study aims to expand the traditional lifetime model through correction terms and optimize the lifetime prediction platform. The lifetime model for power cycling (PC) is often limited to fixed module designs, such as specific semiconductor devices, module specifications, or substrate layout. As a result, the lifetime model is difficult to apply to different module variations. To address this limitation, this study focuses on improving the scalability and accuracy of the lifetime model. Considering the failure mechanism of the die-attach solder layer, the influence of power chip size on the number of power cycles is explored. A lifetime model that can be applied to a variety of module designs is established and verified using both commercial and ITRI-developed SiC half bridge power modules. This modified lifetime model can significantly reduce the prediction error between the traditional model and experimental results. It is expected that similar module types produced with different power chip size can still effectively use the modified lifetime model for accurate reliability evaluation.