Sessions Index

Bio:

  E. Jan Vardaman is president and founder of TechSearch International, Inc., which has provided market research and technology trend analysis in semiconductor packaging since 1987. She was the editor of Recent Developments in Tape Automated Bonding published by IEEE Press. She is the co-author of How to Make IC Packages (by Nikkan Kogyo Shinbunsha), a columnist with Printed Circuit Design & Fab/Circuits Assembly, and the author of numerous publications on emerging trends in semiconductor packaging and assembly. She served on the NSF-sponsored World Technology Evaluation Center (WTEC) study team involved in investigating electronics manufacturing in Asia and on the U.S. mission to study manufacturing in China. She is a senior member of IEEE EPS and is an IEEE EPS Distinguished Lecturer. She received the IMAPS GBC Partnership award in 2012, the Daniel C. Hughes, Jr. Memorial Award in 2018, the Sidney J. Stein International Award in 2019, and she is an IMAPS Fellow. She is a member of MEPTEC, SMTA, and SEMI. She serves on the JEDEC Task Force JESD-94 Working Group Application Specific Qualification Using Knowledge Based Test Methodology. She has served on the IEEE CPMT Board of Governors for two terms. Before founding TechSearch International, she served on the corporate staff of Microelectronics and Computer Technology Corporation (MCC), the electronics industry’s first pre-competitive research consortium. She received her M.A. from University of Texas, in 1981.

Abstract:

The need for energy efficient AI will be addressed and projections for the future will be provided. This presentation will examine the current trends in power dissipation for today’s AI products. Package options in production and under developing will be presented. Tradeoffs in package architectures, materials (including thermal interface materials), and colling options are described.

 

Bio:

     Terrence Tan is a Senior Director at Microsoft, based in Penang, Malaysia, where he leads the Custom Silicon Test and Manufacturing Operations within the Silicon, Manufacturing and Packaging Engineering group. His responsibilities span Product, Test, Assembly, Quality, and Debug Engineering. With over 20 years of experience in silicon manufacturing, Terrence specializes in co-optimizing packaging, assembly, and test, and has led multiple high-volume manufacturing ramps for advanced silicon products.

Abstract:

     As global computation increasingly shifts to the cloud, Microsoft Azure stands at the forefront with massive infrastructure powering this transformation. To deliver optimal performance, efficiency, and scalability, end-to-end system optimization has become essential. Microsoft is investing in custom silicon to build a vertically integrated solution stack—from software to hardware—tailored for the demands of cloud and AI workloads. This presentation will delve into the silicon, packaging, and manufacturing strategies driving this vision, with a focus on the critical need for co-design optimization across packaging, design, and test. As traditional boundaries between these domains blur, collaborative engineering becomes vital to meet aggressive power, performance, area, and reliability (PPAR) targets.

 

Bio:

     Dr. Suresh Ramalingam is currently VP for Disruptive Packaging Platforms, Office of CTO at Applied Materials. Prior to Applied Materials he was a Corporate Fellow at AMD. His career spans 31 years in Flip chip /Photonics/2.5D & 3D/CPO Packaging Development at Intel, JDS Uniphase, Xilinx, and AMD respectively. He is an IEEE Fellow for his leadership and technology innovation to commercialize 2.5D Silicon Interposer. Dr. Ramalingam holds 137 patents, 50+ publications, SEMI and Ross Freeman Awards for Technical Innovation, ECTC and IMAPS Best Paper Awards and contributed a book chapter on 3D Integration in VLSI Circuits. He graduated in 1994 with a Ph.D. in Chemical Engineering from Massachusetts Institute of Technology, Cambridge after completing his bachelor’s degree from Indian Institute of Technology, Chennai.

Abstract:

     With the remorseless pace of LLM and generative AI model evolution, Advanced Packaging scaling is stressed like never before. TSMC public roadmaps project the need for being ready with >7X reticle CoWoS integration by 2027 and even larger beyond. CPO connectivity for scale out switches is an emerging trend, and future roadmaps could see a need in the scale up domain as well. Power delivery density is another challenging area as GPU compute devices are expected to push well beyond 2kW.
     With these trends, current packaging approaches to scaling 2.5D large integration sizes, assembling on ever larger substrates including photonic connectivity will be challenged and new approaches may need to be explored. In this talk we will explore the challenges, future roadmaps, and the potential of silicon-core based packaging platform

 

Bio:

Abstract:

As AI applications expand from cloud-based data centers to edge computing, TSMC’s 3DFabric^® plays a crucial role in advancing AI and edge technologies. While chip designs increase in density, size, and functionality, challenges such as HBM integration, reliability, and thermal management arise.

CoWoS-R technology offers greater flexibility, enhanced rout-ability, and effective thermal solutions for high-power, high-integration systems.  However, finer pitches lead to higher resistance and RC delay, creating SI/PI performance trade-offs. Designers must co-optimize SoC and HBM integration to fully leverage CoWoS-R technology, carefully balancing the benefits and challenges associated with finer pitch advancements.