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S18: Advanced Design, Modeling & Testing II

Oct. 27, 2022 15:40 PM - 17:40 PM

Room: R504b
Session chair: Sheng-Jye Hwang, Professor, NCKU / Lewis C.Y.Huang, VP, Senju

TGV Cu metallization technology trend
發表編號:S18-1時間:15:40 - 16:10

Invited Speaker

Onishi Tetsuya, Managing director, Grand Joint Technology Ltd.

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Raman Spectroscopy and Hyperspectral Imaging for Wafer-On-Wafer (WOW) Processing
發表編號:S18-2時間:16:10 - 16:25

論文編號:EU0082
A. Myalitsin, Z.-W. Chen, N. Araki, T. Nakamura, T. Fukuda, T. Ohba

Demand for more powerful devices requires 3D integration (3DI). However, conventional 3DI processing is limited by the minimum thickness of the silicon wafer and the maximum connection density. In contrast, wafer-on-wafer (WOW) technology with bumpless interconnects can produce stacks of wafers with only a few μm thickness each. [1] During this process wafer warpage can occur, which requires careful monitoring and correction. Usually, alignment markers are placed on each wafer and the deformation confirmed with transmission IR. However, this has several drawbacks, such as low spatial resolution and lack of depth perception. In contrast, confocal Raman spectroscopy is not only non-destructive and contact-free, it also has sub-micrometer resolution in XY plane and can probe semiconductor devices at a certain depth. In this report we describe how confocal Raman imaging can be used in WOW manufacturing.
Edge-trimmed 300 mm DRAM wafers were temporarily bonded on support wafers with temporary adhesive and subsequently thinned with a grinder (DGP8761, DISCO Corp.), first by coarse grinding down to 50–60 µm thickness, and later by fine grinding down to the final thickness. During fine grinding, an automatic feedback sequence was applied to improve the total thickness variation within the 300 mm wafer.
Hyperspectral Raman images were measured in backscattering geometry, with a confocal Raman microscope (Confotec MR250, SOL Instruments). The sample was raster scanned with a motor stage (pitch 4 μm/pixel). Two different lasers, 532 nm and 785 nm, were used in the experiment. The absorption depth of silicon strongly depends on the wavelength in the visible range. Therefore, Raman spectra measured with 532 nm excitation are representative of the structure close to the surface (<1 μm), and Raman spectra measured with 785 nm excitation represent the structure ~5 μm below the surface. The data was analyzed with a custom code written in IgorPro 9 (Wavemetrics).
Figure 1 shows typical Raman spectra at the scribe line, near the center of the wafer. The peak of silicon at 520.7 cm-1 is clearly visible with both excitations. The Raman spectrum measured with 532 nm excitation has a significantly higher fluorescence background, possibly from organic contaminants on the surface.
Raman imaging was performed at the cross-section of two scribe lines, shown in Figure 2(a). The area was chosen because it contains alignment markers from both wafers, upper and lower. Markers located at the upper wafer (indicated with red arrows) are visible in the bright-field image. The cross-shaped marker in the lower wafer, however, is not. Raman images of the intensity of the silicon band are shown in Figure 2(b) (532 nm excitation) and Figure 2(c) (785 nm excitation), respectively. Close to the surface, the scribe-line crossing appears homogeneous, without noticeable difference in contrast. Only markers from the upper wafer appear as dark rectangles, since they block the excitation laser above the silicon. On the contrary, the 785 nm laser probes deeper into the silicon. Some of light reaches the lower wafer marker and is reflected back. Therefore, more Raman signal is created from silicon just above the marker. As a result, the cross-shape of the marker appears in the Raman intensity image. We see that the cross is not centered on the scribe line, due to wafer warping. This result demonstrates that Raman imaging can be used for post-process analysis of wafer warpage. Further, it can be extended to in-line alignment monitoring in WOW manufacturing.
Next, we discuss the Raman shift due to stress in the silicon wafer. Tensile stress shifts the band at 520.7 cm-1 to lower frequencies, while compressive stress leads to higher frequencies. [3] In silicon, near the surface, the shift due to stress is linear and can be described by the following equation [4]:
σ (MPa)=-470 ∆ω (cm^(-1))
Two areas were investigated, one near the center of the wafer and one close to the edge of the wafer. The silicon band was fitted with a single Lorentzian function. Resulting images of the peak position are shown figure 3. The peak position is almost same inside each area, indicating that the stress distribution is locally homogeneous. However, there is a significant difference between the central and the edge areas. Near the edge the peak has shifted ~0.5 cm-1 to lower frequency, which corresponds to a tensile stress of around 235 MPa. On the other hand, near the center, the peak shift is shifted ~0.3 cm-1 to higher frequency, indicating compressive stress of around 141 MPa. This is consistent with wafer warping which occurs during the WOW production process. Detailed correlation analysis between macroscopic warping and microscopic stress observation from Raman scattering is currently underway.
In summary, we investigated the bare silicon structures on a scribe line of a WOW stack with confocal Raman spectroscopy. By changing the excitation wavelengths different depths of the silicon could be measured. In particular, alignment markers in upper and lower wafers were identified simultaneously. We emphasize that the lower marker is only visible in Raman imaging and not in conventional reflective laser scanning. Further, stress distribution in the wafer was visualized, with tensile stress located closer to the edge of the wafer and compressive stress near the center of the wafer. Overall, we demonstrated that confocal Raman imaging provides not only an alternative to transmission IR, but has also several unique advantages, such as higher resolution (< 1 μm), spatially resolved stress distribution in the silicon and 3D imaging capabilities.
References
[1] T. Ohba, T. et al. ”Review of Bumpless Build Cube (BBCube) Using Wafer-on-Wafer (WOW) and Chip-on-Wafer (COW) for Tera-Scale Three-Dimensional Integration (3DI)” Electronics 2022, (11), 236.
[2] Z.-W. Chen et al. ”Ultra-Thinning of 20 nm-Node DRAMs down to 3 μm for Wafer-on-Wafer (WOW) Applications”, 2021, IEEE 71st Electronic Components and Technology Conference (ECTC), 1131.
[3] Z. Iqbal and S. Veprek. “Raman scattering from hydrogenated microcrystalline and amorphous silicon” J. Phys. C: Solid State Phys. 1982, (15), 377.
[4] S.-K. Ryu, et al. "Micro-Raman spectroscopy and analysis of near-surface stresses in silicon around through-silicon vias for three-dimensional interconnects", J. Appl. Phys. 2012, (111), 063513.


 
System Level IR Drop Impact on Chip Power Performance Signoff for RISC-V System on Chip
發表編號:S18-3時間:16:25 - 16:40

論文編號:AS0097
Kin Fei Yong, Chin Theng Lim, Wei Khoon Teng

Understanding of how a chip power performance is impacted by the IR drop of a power delivery network (PDN) enables system operating conditions to be optimized. It allows IR drop impacts to a silicon chip to be identified and fixed early during design phases.
Conventionally, the static and dynamic IR drop analysis for a silicon chip only considers the impact of silicon level power switching gates and metal routing. Such an analysis approach assumes the power supply from voltage regulator module (VRM) to silicon bumps is noise-free and steady, without taking the impacts of system level components into considerations. In our opinions, such an analysis approach is unduly optimistic and causes IR drop signoff to be less reliable.
This paper uses a RISC-V CPU as a case study to illustrate the importance of the external components in an IR drop analysis. The characterization results show that an IR drop of 100mV caused by PDN impedance can result in the targeted clock speed to be reduced by up to 500MHz, which is equivalent to a 50% performance degradation for a 1GHz CPU and is significant. Then, the impact of system level IR drop caused by package, board and VRM to a silicon chip power performance is further shown. A comparison between the conventional Redhawk chip IR drop simulation and our approach is presented. Our modelling methodology, which uses a system-level distributed PDN to increase IR drop analysis accuracy has also been described in detail. It is shown that external factors including package, board and VRM can induce up to 5.7% additional IR drop, or, 0.057V for a 1V power supply. This may cause the targeted clock speed to be reduced by up to 250MHz in the actual silicon. It is demonstrated that the intrinsic resistance and impedance of PDN if not being managed properly could negate the power delivery efficiency and impacting silicon performance. This PDN parasitic effect becomes more prominent when complex activities at silicon edges draw a large amount of current from a power supply.
It is concluded that when signing off the chip power target, we must analyze the PDN at system-level including VRM, board, package, decoupling capacitors, metal routing and power switches in the silicon concurrently.
This approach allows the potential impacts to be identified upfront during design phases and hence, enables the metal routing and power planning to be optimized as needed, enables early discovery of IR drop issues to mitigate costly “down-binning” or worst, re-spinning a silicon to reach the design goals.
This paper is organized into the following sections:
Section I: The DC IR drop and di/dt noise external to the silicon are taken into consideration in chip power analysis.
Section II: The relationship between supply voltage to core clock speed.
Section III: shows the simulation results with different core activities scenarios. It is shown that additional voltage supply noises could encroach the IR drop margin significantly.
Section IV: provides comparisons of the worst-case impacts between analysis with and without external IR drop.


 
DDR Debug Methodology for Board Design Quality and System Robustness
發表編號:S18-4時間:16:40 - 16:55

論文編號:TW0103
Zoe Liu, Thonas Su, Jimmy Hsu, Denis Chen, Paul Chen

System performance is major indicator of a server or workstation. Besides the CPU’s (Central Processing Unit) computing power, the DRAM (Dynamic random-access memory) used in the memory system has a direct impact on the performance. To provide high bandwidth and large memory space, the memory system must operate in a high frequency and the system needs to have the capability to provide as many DRAM slots as possible, respectively. DDR4 (Double Data Rate 4th generation) has been introduced since 2014 and the current Intel server SoC (System-on-Chip) platform support it to be operated in 2933 MT/s (Mega Transfers per Second) with two DRAM modules populated in a channel. Through the capability of supporting multiple channels (e.g., 4 channels), a system can support up to several Tera bytes of memory. From system designer’s point of view, it is vital to test the robustness of the memory system in the EV (Electric Validation) phase. To achieve the goal, Intel not only asks designers to conduct “system test” by running test tools but also provides the “Intel Rank Margining Tool (RMT)” to help designer understand how much eye height and eye width margin exist before the memory system has risk. Since a severe low margin usually leads to a re-spin of the mainboard, the test and debug activity are both critical to ensure the quality of the mainboard design. In this paper, a systematic and scientific debug methodology is proposed and demonstrated to identify an abnormal DDR low margin issue found in an Intel Xeon server platform in an OEM’s (Original Equipment Manufacturer) project. This system is based on an Intel SoC processor, which supports up to 4 channels of DDR4 memory. Several DQ (Data) bits run into low eye height and eye width margin in the RMT test. This implied there would be a potential risk in the memory system which may decrease the robustness or increase the DPM (defeats system per million) after the HVM (High Volume Manufacturing). A proposed DDR debug methodology was adapted to find the root cause. Through the process, several DDR signals (aggressors) had been identified as low margin aggressors by EV engineers and the low margin phenomenon was solved after the design implemented SI (signal integrity) engineer’s suggestions.


 
A Novel Modelling Methodology for Underfill Molding Process On 2.2D Heterogeneous Integrated Substrate
發表編號:S18-5時間:16:55 - 17:10

論文編號:TW0040
Yu-En Liang, Chia Peng Sun, Chih Chung Hsu, Dyi Chung Hu, Er Hao Chen, Jeffrey Changbing Lee

With the rapid growth of market demand for portable mobile data access devices, the market's requirements for functional integration and packaging complexity are also increasing. At the same time, higher integration, better electrical performance, lower latency, and shorter vertical interconnect requirements are forcing packaging technology to shift from 2D packaging to more advanced 2.5D and 3D packaging designs. To meet these demands, various types of stacked integration technologies are used to integrate multiple chips with different functions into smaller and smaller sizes. Even so, the key factors that affect the packaging challenges are still similar, such as cost-effective manufacturing process, fine pitch interconnect within the micro-behavior, and so on. Specifically, they are in the chip / wafer level miniaturization and integration issues that must be overcome. In the previous paper, we have presented a novel 2.2D solution that used thin film RDL directly bonded to substrate. This 2.2D structure can create a die last integrated substrate with a very flat and rigid base with fine lines on top and coarser lines at the bottom side. This simplifies the integrated substrate structure and further improves the cost and cycle time. However, to meet the rapid design change in the early phase, the simulation tool for underfill analysis is needed to meet the sizes variations from 20x20mm, 40x40mm, and up to 60x60mm.
For the simulation of dispensing behavior, 3D modeling is unavoidable. However, the computing cost will become unaffordable due to the increasing number of bumps and simulation area sizes. In this study, instead of a detail model removing the describing bumps, a novel Equivalent Bump Group (EBG) model with dispenser simulation is introduced to save at least 10 times faster simulation time. The concept of the EBG model is established as a series of weighting factors to modify the contribution of capillary force for the bump effect of capillary-driven underfill flow. A validated case shows that the modeling solution of melt front by EBG model has a good agreement with detailed model for given dispensing passes settings. Moreover, filling time for multi-array package due to the flow pattern controlled by the dispensing design is also investigated by the EBG model. Not only the model provides a better understanding of the physics of the capillary underfill process but also it is proven to be an effective tool for assessing the dispensing conditions.
Keywords—3D CAE modeling, capillary underfill, multi-chip package, micro bumps, dispensing process, Equivalent Bump Group (EBG).


 
Effects of Corner/Edge Bond and Side-fill for Automotive MCM Applications
發表編號:S18-6時間:17:10 - 17:25

論文編號:TW0115
Kuo-Hua Heish *, Chao-Chieh Chan, Ming-Jhe Wu, Chih-Yang Weng, Chun-Jen Cheng, Yu-Da Dong

For the high reliability and harsh environment applications such as automotive grade MCM (multi-chip modules) or SiP (System in Package), normally requires under-fill to achieve the needed thermal cycles, mechanical shock and vibration reliability. And, these high reliability applications often incorporate high process cost, spending on PCBA flux cleaning, baking, plasma treatment even under-fill capillary time consuming. Despite of above manufacturing process cost, the environmental regulations also challenges the manufacturer to consider more cost effective and environmental manufacturing processes with moderate reliability to meet modern automotive industrial requirements.
This study focus on non-cleaning corner / edge bond reinforcement techniques including material selection, verification, and process design to improve the solder joint reliability of BGAs assemblies to meet the minimum automotive industrial standards (AEC-Q104 Failure Mechanism Based Stress Test Qualification for Multichip Modules). The reliability testing protocol used here, included pre-conditioning (3X multi-reflow) and thermal cycling (-40 to 85 °C). Four adhesive materials (commercially available) were studied with test vehicles including die attachment and BGAs with plans to expand the study on WLCSP BGAs. Process development was also conducted on the edge bond process to determine optimum process conditions.
For edge bond processing, establishing an edge bond that maximizes bond area with proper fillet height without encapsulating the solder balls is key to prevent the process quality issues as well as reliability improvements.


 
Predict the Reliability Life of Wafer Level Packaging using K-Nearest Neighbors algorithm with Cluster Analysis
發表編號:S18-7時間:17:25 - 17:40

論文編號:TW0032
H. L. Chen, B.S. Chen and K.N. Chiang*

Moore’s law was proposed by Gordon Earle Moore, who believes that the number of transistors that can be accommodated on an integrated circuit would double about every 18 months. Since it is approaching the physical limit, Moore’s law is no longer applicable. Packaging technology becomes more important in the post Moore era. The development of electronic packaging can be roughly divided into five stages, namely TO-CAN, DIP (Dual In-line Package), PQFP (Plastic Quad Flat Pack), PBGA (Plastic Ball Grid Array) and the CSP (Chip Scale Package) used in this research. The evolutions are to improve signal transmission speed, storage capacity and the pursuit of higher packaging density. The reliability of packages is very important. Different sizes or manufacturing methods will affect their lifetime. Before these packages are put on the market, they must be tested and experimented to ensure their reliability. However, it will waste a lot of resources and time costs, resulting in less profit.
Finite element analysis is a numerical method that can subdivide a large physical system into a finite number of smaller and simpler elements. The study uses ANSYS to simulate WLCSP (Wafer Level Chip Scale Packaging) through thermal cycling test, and used empirical formulas to estimate the lifetime of solder balls. Also, the mesh size at the maximum DNP (Distance from Neutral Point) is fixed. Make the simulation closer to the experiment results. After the verification of simulation and experimental data, the feasibility of the model is established, thereby saving the huge time cost of packaging testing and experimentation.
However, finite element analysis will produce different results depending on the researcher. In order to avoid this factor and save the time spent in constructing the model, this research introduces artificial intelligence and combines supervised learning and unsupervised learning to estimate the solder ball lifetime. In this study, we used the verified finite element model to obtain different lifetime according to different sizes, and then introduced a large amount of data into AI algorithms to achieve the purpose of quickly predicting the reliability of the package.
The algorithm used in this study is KNN (K-Nearest Neighbors) which can be used for classification and regression, and uses different data numbers, different preprocessing methods, different distance definitions, and different weighting methods to compare the impact of the algorithm’s predictions on the lifetime of our packages. In addition, we combine unsupervised learning methods like K-means to assign data of the same characteristic into each cluster. Try to simplify the complexity of the model, save calculation time and improve the performance of KNN.

Keywords – Wafer Level Package, Finite Element Analysis, Thermal Cycling Test, Reliability Assessment, Artificial Intelligence, Supervised Learning, Unsupervised Learning, K-Nearest Neighbors, K-means


 


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