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S15: Fan-Out and Heterogeneous Packaging

Oct. 27, 2022 13:10 PM - 15:10 PM

Room: R504c
Session chair: David Tarng, Director, ASE Taiwan / Shih-Kang Lin, Professor, NCKU

Heterogeneous Integration of Substrates
發表編號:S15-1時間:13:10 - 13:40

Invited Speaker

Dyi Chung Hu, CEO, Siplus

As society moves to AI, machine learning, 6G, AR/VR, metaverse, autonomous driving, etc., efficient electronic systems with high performance and small form factors are needed.
Traditionally system packaging is divided into levels. Solders and cables are used for the interconnections between different packaging levels. However, if we can reduce the levels of system packaging, we can increase the system performance by reducing the interconnection length. The recent development of chiplets solution has confirmed the trend.
There are two primary directions used in heterogeneous integration for high-performance system integration. One direction is die-to-die integration. Leading companies like TSMC with “SoIC” and Intel with “Foveros” solutions. The other direction is substrate integration. “Substrate integration” integrates a fine line substrate with a coarser line substrate. Examples are 2.5D substrate solution and EMIB by Intel.
Various “die-last integrated substrate” solutions have been developed for the past ten years. For example, Shinko has developed 2.1D and 2.3D solutions, and SiPlus has developed 2.0D and 2.2D solutions. 2.0D structure is thin film RDL directly on a core-less substrate. 2.1D structure is thin film RDL on a cored substrate. In comparison, 2.2D structure is thin film RDL solders to a cored substrate.
Both 2.XD solutions have the advantages of removing solder or/and TXV (TSV or TLV) in the integrated substrate structure. Depending on the requirements of cost, performance, and time to the market, users can select the most suitable 2.XD structure to meet their needs.
In this talk, the development history of the integrated substrate and structure performance comparison of 2.XD integrated substrate will be discussed.


 
Low-temperature Pb-free solder design
發表編號:S15-2時間:13:40 - 14:10

Invited Speaker

Shih-Kang Lin, Professor,Materials Science and Engineering , National Cheng Kung University

To release warpage problems in the step-soldering process, low-temperature Pb-free solders with low cost and high reliability are in demand in the electronic industry. Eutectic Sn-58Bi with high mechanical properties, good wettability, and low melting temperature at 139 °C has drawn great interest in the industry. However, the brittle nature of the Bi-rich phase and microstructure coarsening during thermal aging is a significant issue in employing the Sn-58Bi solder. In the invited talk, CALculation of PHAse Diagram (CALPHAD)-type thermodynamic calculations using the PANDAT software and corresponding key experiments were performed for Sn-Bi-Ga, Sn-Bi-In-Ga, Sn-Bi-Ti, Sn-Bi-Ag, Sn-Bi-Zn, Sn-Bi-Ag-In, and Sn-Bi-Ag-Zn systems. Each system had different advantages, which can meet various applications in the future. Furtherly, the calculated and experimental methods agreed with each other. The relationship with solidification paths, microstructure, and tensile properties was highlighted.


 
Heterogeneous Integration Fan-Out Package Solution for HPC/AI Application
發表編號:S15-3時間:14:10 - 14:25

論文編號:TW0061
Mark Liao, David Wang, Vito Lin, Teny Shih, Yu-Po Wang, Don Son Jiang

SUMMARY
This paper will provide an overview of memory integration evolution trends seen in the industry across different package platform, including memory on PCB, memory on module and memory in package. It also figure out major advantage of Fan-Out package with HBM integration. Finally, package level reliability w/ fan-out HBM integration also be demonstrated.
List of Keywords: Heterogeneous Integration (HI); Artificial Intelligence (AI); High-Performance Computing (HPC); Silicon Interposer; Fan-Out Multi-Chip Module (FO-MCM), Redistribution Layer (RDL); High Bandwidth Memory (HBM)

INTRODUCTION AND MOTIVATION
Leading-edge applications such as Artificial Intelligence (AI), High-Performance Computing (HPC), 5G and IoT are driving demand for increased electronic device performance. On the other hand, the innovation in package technology is also related to an increase in the functional integration of large system-on-chip solutions. Therefore, major focus on heterogeneous integrations have prompted the chip industry to develop a new set of solutions as advanced packaging.
Heterogeneous Integration (HI) by Fan-Out Multi-Chip Module (FO-MCM) solution is driving the “More Than Moore” vision. With higher memory bandwidth requirement, High Bandwidth Memory (HBM) is major candidate to replace traditional GDDR to meet higher data rate for end product application.

TECHNICAL APPROACH
As heterogeneous integration increases, the convergence of die, package, and PCB will increase as well. For example, Fan-Out with memory integration corresponding more IO count requirement for fine-pitch micro-bump and Redistribution Layer (RDL). In other word, it represented to request both finer RDL line and more RDL layer count. Furthermore, the end-user mainly determines package requirement and therefore defines the complexity of both chip and package. It trigger high-density FO-MCM package technology to meet the demand.
High-density FO-MCM incorporates several chips in the same package, including HBM. Traditionally, HBM was mainly found in 2.5D package. In general, standard HBM generation’s product got specific IO pin and serdes location. It is more suitable to approach various Fan-Out package compared to SOC homogeneous integration without specific serdes. Basically, from structure simulation point of view, figure out suitable package platform according to various product design from customer side.

RESULTS AND DISCUSSION
Compared to 2.5D package, FO-MCM package showed lower stress to meet heterogeneous integration packaging requirement. In conclusion, with the construction of FO-MCM package with HBM integration, package level reliability verification is demonstrated successfully by Pre-condition, unbiased highly accelerated stress test (uHAST), high temperature storage (HTS) and thermal cycle test (TCT)


 
HIGH TEMPERATURE RESISTANT PROTECTION TAPE FOR PANEL LEVEL EMBEDDED CHIP PACKAGE ON SUBSTRATE
發表編號:S15-4時間:14:25 - 14:40

論文編號:AS0013
Lei Dong, Joann Wang, Aizoh Sakurai, Xiao Han, Wei Zou, Robin Gorrell, Benson Chen, Jenny Zhu

As a trend of the advanced package, Embedded Chip Package (ECP) shows a high growth value at semiconductor package field in these years. During ECP substrate manufacturing, a high temperature resistant protection tape (referred as tape hereinafter) is used to enable the chips aligned in the substrate and embedded with a laminating sheet. In the process, the substrate with copper trace patterns and pre-formed cavities is attached to the tape; chips can be packaged in the cavities by laminating a B-stage epoxy sheet on the top surface; and the epoxy sheet flows into the cavities, can be cured and bond to the substrate panel through a high temperature and high-pressure bonding process. Ultimately, the protection tape needs to be peeled off from the substrate easily without residue.

Easy to use, easy removal, low residue and free of contamination after high temperature and high-pressure hot-pressing process are the key requirements for the protection tape used in this embedded die process. High temperature resistance silicone tapes tend to contaminate substrate surface with silicone residue; Other acrylic high temperature resistant tapes, although being predominantly used in the embedded-chip-in-substrate manufacturing process, still suffer from the residue or delamination issues under higher temperature and pressure conditions. To avoid residue, some manufacturers applied an additional buffer layer to prevent tapes from directly contacting with substrates, which adds extra process steps and cost to remove this buffer layer.

In this paper, we discuss a novel non-polar & silicone-free (NPSF) high temperature resistance tape that was developed for the embedded-chip-package-on-substrate manufacturing. This tape demonstrated dramatically reduced residue on substrate surfaces, even after a thermal bonding process up to 225℃ for 2 hours with a high pressure at 430 psi, which enables continuously build redistribution layer (RDL) without bubble or delamination issue. The tape also showed good chemical resistance on various organic solvents. Furthermore, die shifting defect can be controlled to less than 50μm for a chip package size of 1 x 1 mm. With this tape, epoxy material would not bleed out from the cavities under tape protection. Compared to other tapes on the market, 3M NPSF tape gives significant benefits with higher process yield and lower process cost for embedded chip package applications.


 
RF Devices Integrated by Fan-Out and System-In-Package Technology
發表編號:S15-5時間:14:40 - 14:55

論文編號:TW0058
Cheng-Yuan Kung, Hung-Yi Lin, Chin-Cheng Kuo, Cheng-Syuan Wu, Yu-Ting Chen, and Meng-Wei Hsieh

Higher performance and smaller form factor are always the critical subjects for mobile device in recent years. To meet this demand, System-In-Package (SiP) has become a certain path for innovation and an unstoppable trend for decade. Multi-functional active chips and related passive components can be pre-assembled into a system or sub-system through heterogeneous integration design on laminated substrate. However, as this technology has almost approached its limits, innovation is needed on the corresponding package of SiP for now and the future.
Fan-Out packaging is package with connections fanned-out of the chips surface by using redistribution layer (RDL), enabling more external I/Os, better electrical and thermal performance, precisely RDL can enhance RF performance by accurate impedance control and routing to inductor for impedance matching. In general, Fan-Out technology can be classified into two types, being Chip-First and Chip-Last. Chip-Last Fan-Out take the advantages of lower cost and yield due to the Known-Good-Die (KGD) approach, good compatibility to current packaging infrastructure and easy to integrate heterogeneous elements (Si-chips, non-Si chips and passive devices with different thickness).
In this study, the benefits of evolving SiP with organic substrate to Fan-Out SiP (FOSiP) for new generation mobile RF module with higher performance and smaller form factor has been illustrated. A designed and manufactured FOSiP module with 6 RF devices integrated by several core features and building blocks would be demonstrated, including chip-last RDL manufacturing, carrier system, wafer level assembly and shielding sputtering. First, Fan-Out RDL provides fine line design capability which is better than substrate to enhance the function matching in SiP. Second, carrier system makes thin wafer handling possible. In addition, wafer level assembly delivers high speed and high accuracy SMT and Molding Under Fill (MUF) technique for advanced encapsulation. Finally, shielding sputtering provides an option to apply on specific RF applications.
As results shown, this FOSiP module could have 40% footprint and >50% thickness reduction comparing to conventional SiP module made by organic substrate. Besides, the electrical performance (S-parameter) has been also measured with good agreement as expectation. Through this validation, FOSiP provides a new platform to fulfill the demand from these markets to make the next generation mobile products possible.


 
A Study of Material Extraction and Moisture Effect on mmWave Fan-out Package Design
發表編號:S15-6時間:14:55 - 15:10

論文編號:TW0071
Chiung-Ying Kuo

In recent years, with the development of science and technology, the demand for artificial intelligence (AI), Internet of Things (IoT), 6th generation mobile networks and even autonomous driving applications has increased significantly. These systems all require high-speed signal transmission and a large amount of data processing. Therefore, the multi-channel data transmission and the required frequency must reach the mmWave (~66GHz) level when designing the SiP module. Small size and multi-channel big data transfer requirements, the advanced package such as fan out chip on substrate (FOCoS) is good candidates for high performance computing products.
For mmWave and high-speed design on Fan-out package, impedance characteristic and Redistribution Layer (RDL) trace loss are very important. So, how to get accuracy Dielectric Constant (Dk) and Dissipation Factor (Df) is vital work. The paper is using the Transmission Line (TL) method to get the Dk and Df value. The frequency is up to 60 GHz. Thermal and stress effects on the Fan-out FOCoS package is crucial key. Moisture has obvious effects on Polyimide (PI) Dk/ Df value. This paper also studies the moisture effect on outer and inner RDL layer.
As Fig. 1 shows, the GSG design of 2-layer RDL is used for Dk/ Df extraction. The Cu thickness of the designed RDL1/ RDL2 is 9.3/ 7.3um, PI thickness is 9um, width/ space is 15/ 15 um respectively. Use different line lengths to get de-embedded measurement data for simulation correlation. And then get the broadband PI Dk/ Df value from transmission line method and verify the Dk/ Df value by using T-resonator. There is good correlation between measurement and simulation when applying this Dk/ Df value in the simulation model as Fig. 2. The samples are put on the chambers for oxidization. In this paper, the moisture effect on inner/outer RDL has been demonstrated.


 


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