Oral Sessions


S8:Advanced Design, Modeling & Testing I

Oct. 26, 2022 15:40 PM - 17:40 PM

Room: R503
Session chair: Kuoming Chen, Director,UMC / Chang-Chun Lee,Professor, NTHU

A comparative study of single-phase immersion cooling between FC70 and PAO6
發表編號:S8-1時間:15:40 - 16:10

Invited Speaker

Chi-Chuan Wang, National Yang Ming Chiao Tung University

The present study investigated the single-phase immersion cooling in a 1U server with FC70 & PAO6 with the following outline:
1. General background for immersion cooling.
2. FC70 & PAO6
3. Effects of inlet location, flowrate, fin pitch of the heat sink, and supplied power on the thermofluids performance.
4. Summary

LAB Flip Chip Reflow Process Robustness Prediction by Thermal Simulation
發表編號:S8-2時間:16:10 - 16:25

Ching-Ho Chang, Ruey Kae Zang

Mass reflow (MR) soldering is a very popular and stable process in the industry. The applications of MR include flip chip, ball mounting, surface mount technology (SMT), and even reliability tests. More recently, laser assisted bonding (LAB) uses a laser beam as a thermal energy source to focus solder melding on the die area. Compared with traditional MR, this type of localized heating provides several advantages in flip chip assembly. However, the standardized process or best-known method (BKM) for laser power and duration currently does not exist.
According to the previous research, part of the laser beam will be reflected from the surface of the material. In this study, the optimization method was used to find the absorption rate of die by infrared (IR) imaging. The absorption rate was correlated under different devices and scenarios. To fit the instantaneous temperature distribution of the IR image, a transient thermal simulation model with the detailed trace was used. A heat flux is applied on the die surface and part of the substrate to represent the laser beam.
The simulated results of the temperature distribution in the chip area and the distribution on substrate matched the IR image. From the data analysis, the power density required in the simulation is related to not only the power itself but also to the emission time and the substrate area directly exposed to the laser beams. To predict the LAB parameters for a customer cosigned substrate, this study proposes a generic substrate structure that can be used in the LAB process setting without using actual substrate designs. Without the inner trace layout of the substrate, the error margin for the maximum die temperature is expected to increase from within 5% to within 7%.
From the current inspection data, the solder temperature target for parameter setup should be 266°C. The ideal solder temperature range (above 243°C and below 276°C) is established for the laser parameters setup of a future New Product Introduction (NPI). This work provides a methodology that: a.) is capable of predicting localized die temperature using the LAB process, b.) is capable of defining index of solder joint conditions, c.) establishes LAB power and emission time prediction capabilities, and d.) evaluates mechanical stress with localized heating distribution effects.

Thermal Assessment for Chiplets System-in-Package
發表編號:S8-3時間:16:25 - 16:40

Yu-wei Huang

Due to the development trend of portable electronic products are inclined to be thin, small, and well-functioning, the system-in-package (SiP) has been one of the essential packaging architectures in recent years. Because of high-density integration, the thermal management of the system board has been a crucial issue prior to the successful implementation of SiP. The primary heat sources of portable electronic products are resulted from central processing unit (CPU), memory, communication chips, and batteries. Generally speaking, the operating temperature of the CPU with the graphics card is preferably below 90 oC. Therefore, it is necessary to ease the heat generation that can effectively maintain the components’ performance.
However, for the portable electronic products, the heat generation requires to transfer to the external surface of the module/system sufficiently. Then, through passive cooling mechanism, the heat generation can be transferred to the environment through natural convection and radiation. Due to numerous components on the system board, there may be other practical considerations. Moreover, the system's overall module and housing design significantly impact the operating temperature. Therefore, this study only considers the thermal design points and the feasibility of this architecture. This research proposes a novel SiP (system-in-package) architecture, referring to Intel's Lakefield, the industry's first 3D stacking and foveros packaging mobile products. Retains the dimensions and face-to-face bonding technology between the computing chiplet and the base chiplet, changing the memory module from the original PoP (Package on Package) form to a more integrated C2C (Chip to Chip) form. Also, refer to the number of I/Os and TSVs per component and adjust to apply to this architecture. This study used an equivalent technology on the micro-bumps to simplify the model and speed up the simulation time. The research shows that the heat conduction results of the bump layer using the volume equivalent model are highly consistent with the actual model. Therefore, applying this equivalent layer results in this SiP architecture. To further investigate the thermal impact of this architecture, a heat source of 7W was given to the module, referenced from Lakefield's thermal design power (TDP). The logic chiplet is the most significant heat source in the architecture and is the area most in need of heat dissipation. Furthermore, Ellison empirical equation is used to evaluate the natural convection and radiation. It has been verified by simulation that the heat is transferred to other parts of the module through solder paste, thermal via, copper plate, and graphite film to improve the state of heat accumulation on the chip, which can significantly reduce the chip temperature. Thermal vias and metal plates can help package modules dissipate heat vertically and horizontally, respectively. Through the heat dissipation design, the maximum temperature of the chip and the module can be maintained below 90oC to ensure the regular operation of the chip. After the heat dissipation design of this architecture, even if it works in the TDP state and uses passive heat dissipation, it can have reasonable temperature control.

Thermal Performance of Single-Phase and Two-Phase Immersion Cooling in Data Center
發表編號:S8-4時間:16:40 - 16:55

Chun-Kai Liu, Tan-Yi Chang

The boosting of digital technology (e.g., Internet of Things, artificial intelligence, big data, 5G, cloud computing) demonstrates an increasing need for data centers. This increase has triggered the growth of data center infrastructure as processing, storage, and communication system in the digital world. The data center itself has contributed 1.5% to the total world electricity consumption and this is expected to increase with time. The proportion of energy used in the data center covers 52% for information technology (IT) equipment, 38% for cooling, and 10% for supporting devices. One of the problems faced by these centers over the years is the cooling of the electronic components. Thermal management of data center systems is a key bottleneck to technology [1]. Single-phase liquid cooling is limited to low heat transfer coefficients (<2 kW/m2 K) [2] while two-phase cooling such as flow boiling suffers from hydrodynamic instabilities. Immersion cooling has emerged as a potential solution to overcome these barriers by enabling the boiling of a cooling fluid directly from electronic components, thereby removing thermal interface materials and packaging constraints encountered in the aforementioned approaches [3]. The thermal performance of two-phase immersion cooling is studied by numerical [4] and experimental measurement [3]. The high heat transfer coefficient of two-phase immersion cooling can increase the heat flux of components.
In this paper, we study the thermal and flow characteristics of electronic components in single-phase and two-phase immersion cooling by CFD software STAR CCM+. The heated electronic components are mounted on PCB and immersed in the tank filled with dielectric liquid FC40, as shown in Figure 1. The heating power is 50W for each electronic component. FC40 has a boiling point of 165℃. On the other hand, in the two-phase immersion cooling, pool boiling and condensing of dielectric liquid are generated in the liquid tank. The dielectric liquid FC72 with boiling point 56℃ is used, as shown in Figure 2. The VOF Multiphase Rohsenow Boiling Model is adopted to study the pool boiling behaviors. The results show that natural convection can be found in single-phase immersion cooling. The highest temperature of the heated electronic component is 98.13℃ and the temperature difference of the components is 4.25℃, as shown in Figure 3. In two-phase liquid cooling, the liquid is boiling on the component surface and condensation in the cooling tube, as shown in Figure 4. Due to the phase change of liquid, the difference in volume fraction of vapor above the components can be found above the components. Latent heat release of the liquid in boiling increases the heat transfer of electronics components. The highest temperature of the electronic components is 68.71℃ and the temperature difference of the components is only 0.39℃, as shown in Figure 5. Two-phase immersion cooling has better thermal performance than single-phase immersion cooling.

Research on Grid Search Method of Support Vector Regression in Reliability Prediction of Wafer Level Packaging
發表編號:S8-5時間:16:55 - 17:10

C. H. Lee, C. Y. Chang and K.N. Chiang*

Due to the increasingly developed and demanding accelerated thermal cycling of integrated circuits is crucial to reduce the development time of electronic packaging. Therefore, developing effective methods for shortening the development time has been a demanding issue for designing the new electronic packaging. Using the finite element method (FEM) to predict electronic packaging reliability is efficient. However, the accuracy FEM model is to be completed by experts who have a strong background in mechanical engineering. Thus, the recent work focuses on applying artificial intelligence (AI) algorithm, which only needs the input geometry features (the die and stress buffer layer thickness and the pad size, etc.) to predict electronic packaging reliability. For AI models, the optimal parameters of models influence their performance. Thus, finding the optimal parameters of the AI model is vital for the training process. This research used a regression AI model, Support Vector Regression (SVR), trained by the massive structure-reliability database of wafer-level packaging (WLP) created from FEM results, to investigate the grid searching methods for finding its optimal parameters. Grid search algorithm is a classic method for finding the optimal parameters of the AI model, which divides the range of parameters into certain parts and then calculates each data part to find the optimal parameters. This total searching time is very time-consuming. To find the optimal parameters of SVR more efficiently, we adopted the most typically used radial basis function (RBF) kernel. The reason is that the variables of hyperparameters in the RBF kernel are less than the polynomial kernel and have the behavior of the linear kernel and the sigmoid kernel for specific parameters. Furthermore, this research will investigate different grid searching methods, including grid search algorithm and bisection methods, to find the optimal parameters of the SVR model. After that, we proposed the new grid searching method, the fast grid searching method by plane fitting, which used the least-squares method to establish the convex function by the previous results data. The convex function provides the searching path gradient to update the hyperparameters of the SVR model. The gradient descent approach is most common to update the parameters, which is widely adopted in finding the optimal parameters, to calculate the update parameters. According to the calculated results, the fast grid searching by the plane fitting method can significantly reduce the grid searching time, whether in large or small training datasets. It can obviously be seen that the fast grid searching by plane fitting can efficiently decrease the time-consuming of searching the optimal parameters in SVR, and it can be available for quickly searching.

Quantified tabbed lines and ground void impact on real DDR5 eye margin
發表編號:S8-6時間:17:10 - 17:25

Dirack Lai

Tabbed lines have been proposed to reduce or eliminate far-end crosstalk (FEXT) and impedance management with the ground void beneath SMT connector landing pad implementation for DDR5 channel from simulation and tabbed transmission line measurement by a VNA or TDR. In this paper, a method to quantify the tabbed lines and ground void impact on real DDR5 eye margin is proposed. This method starts with the test board design with fours zones of tabbed, non-tabbed, void and non-void ground and follow up with impedance check by a TDR. The final step is to perform four zones memory margin result as comparison to quantify the tabbed lines and ground void impact on real DDR5 eye margin. The quantified results could be good indicators for tabbed lines implementation decision and ground plane void patch mechanism.

TSV Parasitic Extraction in Heterogeneous Integrated 3DIC Systems
發表編號:S8-7時間:17:25 - 17:40


The TSV (Through Silicon Via) is one of the crucial components in making complex 2.5D and 3DIC systems. The TSVs enable short and wide vertical connections between the top and bottom stacked dies and allow for ultrahigh density and bandwidths, as well as for lower power consumption for data transmission. That is especially significant in logic–memory communication where speed and bandwidth are crucial for efficient memory data access. TSVs are also used on the interposers as a vertical connection between the 3DIC dies and the package. The through-silicon-vias introduce new parasitic components into 3-D ICs and those parasitics can have a significant impact on system performance due to their impact on delay, noise, power consumption, and area. Accurate extraction of TSV parasitics, as well as TSV interactions, is important for achieving desired system design PPA requirements. This paper discusses various TSV types and TSV arrangements, and the approaches used in dealing with the TSV parasitics. Those approaches include pre-characterized TSV parasitic models and parametrized tables for TSV couplings, as well as various approximations of the substrate, either as dielectric or as conductor, used to simplify TSV extraction. All of those approaches have their advantages and disadvantages which will be discussed in detail and compared. The main contribution of the paper is that it presents a novel methodology of dealing with the TSVs that can go through multiple dies and the methodology to accurately extract TSV parasitics as well as their couplings with the neighboring metal lines and with the other TSVs. We demonstrate our methodology on a PSMC memory on a logic test case with two types of TSVs, one of which is going through both die. Taking the holistic approach of the memory on a logic system, with one LVS and one PEX deck set, would be impractical due to the two sets of devices fabricated in different technology. Instead of using the holistic approach, we show how to efficiently separate memory and logic die by dividing the long TSVs that go through both dies and how to then accurately extract the TSVs parasitics that consist of the parasitics of the TSV themselves and the couplings between the TSV and the metal lines and the TSV to TSV parasitics. The results show that the couplings between the TSVs through the substrate are frequency-dependent and that the other simplified approaches can be considered as the special cases of our general approach.


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