Oral Sessions

Advanced semiconductor packaging is widely used in 5G, AI, high-performance computing and other fields. The packaging forms include high-density flip-chip packaging and fan-out wafer level packaging. As the number of I/Os of packaging modules increases significantly, and the pitch and gap are getting smaller and smaller, there is a great challenge for the properties of encapsulant materials. However, the evaluation of encapsulant materials are strongly needed application-side’s cooperation and the evaluation process is complicated and time-consuming, resulting in a long material development time. In response to the needs of developing advanced semiconductor encapsulant materials, a rapid evaluation platform is established, including material property evaluation, preparation of flip chip test vehicles with hundreds to thousands of I/Os, complete assembly process, reliability evaluation and failure analysis. Conducting rapid evaluation of advanced semiconductor encapsulant materials could understand the issues of the material that might be faced on test vehicles, quickly improve or optimize material properties to meet application requirements and strengthen the opportunity that new materials imported into semiconductor packaging application.

 

As the smartphone and tablet PC markets grow rapidly, high-performance, multifunctional, and high-speed signal transmission of devices are required, and at the same time, small form factor is essential. Semiconductor packages are driving high-tech as core components, and FCCSP and SiP are leading the trend of thin and small in the application processor, baseband, RF-FEM - Radio Frequency Front-end Module, GPU, and AI market. Thin substrates are being adopted to reduce the thickness of key packages according to the trend of lightness, thinness, and shortness, and especially in SiP, IC active chips and thin passive components tend to be packaged together, so technology to reduce the thickness of packages is a key trend in mobile devices.
In this paper, the limit in the existing manufacturing line is 14um pitch by the circuit embedding method, and below that, facilities, materials, and lines configuration of a new concept are absolutely required. As a countermeasure, a single-layer fine pitch part may be formed in the fine pitch silicon interconnection IC to be mounted on a cavity substrate, the actual die may be connected to the fine pitch silicon interconnection IC, and the IC chip and the cavity substrate may be interconnected. The fine pitch silicon interconnection IC has the strength of being able to sufficiently respond to markets with a 4um circuit pitch or less by proceeding with a semiconductor fab process. Key developments of fine pitch silicon interconnection IC mounting technology include z-axis chip mounting technology in cavity structure of different depth, fine pitch silicon interconnection IC embedding technology, development of cavity substrate/fine pitch silicon interconnection IC bonding technology, and formation of high modulus solder resist(HSR) layer circuit formation. Due to the characteristics of the construction method, the circuit of the HSR layer cannot be formed by the circuit embedding method and the circuit can be formed by the mSAP method, and an embedding substrate manufactured by the embedding of the 4um fine pitch silicon interconnection IC was developed.

 

1.Introduction
2.Activities of International Standard for Embedded Device at IEC
3.Conclutions

 

In the near future, electrical and mechanical design will be integrated, and a design environment that smoothly links with analysis will become important. Based on this idea, I will introduce ZUKEN’s 3D design environment "Design Force".