Oral Sessions

As Server and AI technology gain traction and spread, production amount of High-bandwidth memory continues to increase. Additionally, micro bump is said to be replaced by hybrid bonding to achieve lower power consumption, reduced stack height and low latency. To meet these trends, we have developed copper plating chemical for both TSV filling and hybrid bonding.

 

In package substrates and power devices used in high temperature and high humidity environments, improving reliability to ensure long-term stable operation is an important issue. We report on our investigation into enhancing the connection reliability between substrates and molding resin by using the PR pulse electroplating method in copper sulfate plating to form a roughened copper film with a high surface area ratio on the substrate.

 

We demonstrate ultra-compact VCSEL-based optical transceivers for Co-Packaged Optics, which has been researched under the NICT BRIGTEN project. The VCSEL transceivers employ the record narrowest 0.3-mm pitch land grid array for a wideband electrical interface. The small land grid array contributes to minimize their footprint as small as 15.9 mm x 7.7 mm. We report the design of the optical transceivers, an electrical pluggable interface, and a testing station built for optical link characterization. We also report the characteristics of optical link employing the VCSEL transceivers.

 

Currently, Sn-3Ag-0.5Cu solder is recommended as a Pb-free solder material for reflow, flow, and manual soldering for mounting general-purpose electronic boards. However, due to the recent rise in material prices, there is a shift to low-Ag solder with reduced Ag content and Sn-Bi solder, which has poor heat resistance but a low melting point. On the other hand, Sn-Zn solder is also a candidate as a Pb-free solder material that does not contain expensive Ag, but because Zn is easily oxidized and a flux is required to remove the strong oxide film, its practical applications are limited from the perspective of environmental pollution risks. Therefore, we covered Sn-Zn solder with formate and conducted a basic study on fluxless soldering.
First, a Sn-8Zn solder sheet (5 mm × 5 mm × 0.1 mm) was immersed in boiling formic acid and then rinsed with distilled water for 10 s. Next, a 10 mm × 10 mm × 1 mm Cu plate (material: C1020P) was polished to #4000 only on the joining surface, and ultrasonically degreased in acetone for 10 min. Next, the formate-coated solder sheet and a Si chip (5 mm × 5 mm) were placed on the Cu plate, in that order, and a spring was placed on top to fix the sample. The sample was then soldered by heating at 200°C to 300°C for 10 min in a N2 atmosphere. To confirm the initial joining state of each sample, cross-sectional observation, SAT (scanning acoustic tomography) observation, and shear strength testing were performed, and the results were compared with our previous work on Sn-8Zn solder joining of Cu plates. When comparing the joint strength of a sample in which Cu plates were soldered together using formic acid reflow with a sample fabricated using this method, the method used had a joint strength that was more than five times higher.
Next, a sample was fabricated in which a Cu plate and a Si chip were die-bonded using a formate-coated Sn-8Zn solder sheet. Next, a structural analysis of the solder joint and joint interface was performed. Note that no formate coating was applied to the Cu plate or Si chip. Next, this sample was subjected to a heat cycle test, and the degree of crack generation and cross-sectional observation of the solder joint and composition analysis were used to clarify the mode of joint degradation. Furthermore, the mechanism behind the improvement in joint strength was clarified by cross-sectional analysis of the joint.

 

As the world's computational load increases with the growth of artificial intelligence (AI) applications, limitations in further enhancement of computer performance are becoming increasingly serious issues. To date, scaling down of semiconductor integrated circuits (ICs) has been driving the high-performance semiconductor technology. However, the semiconductor miniaturization technology now faces a limitation, which is known as the limits of Moore’s law. To address the increasing computational load "Chiplet integration" architecture is expected to drive the next Moore's Law.
Key technologies for the chiplet integration include Si interposer, Redistribution Layer (RDL) interposer, and RDL-Bridge. In RDL, polymers with low Dk/Df (dielectric constant and loss tangent) are used for the interlayer dielectric film, and the manufacturing process typically involves forming wiring by copper plating in vias opened by photolithography. However, for high-density RDL with via diameter under 3 μm, via formation based on the photolithography is difficult for such polymeric materials with low Dk/Df. Therefore, to fabricate a high-density RDL, semiconductor microfabrication technology is required for via formation in the polymer interlayer dielectric film. ULVAC is developing new plasma etching equipment (Φ300 mm or panels up to □600 mm) and processes for the polymer interlayer dielectric films.
In this study, we report on the development of plasma etching technology to form φ2.0 µm fine vias for next-generation high-density Fan-out RDL and RDL-Bridge using polymer interlayer dielectric films with low Dk/Df. As a result, we achieved an anisotropic etching profile with a depth of 4.5 µm and an aspect ratio of 2.25 in the polymer interlayer dielectric film, showing the potential of the semiconductor microfabrication technology for high-density RDL formation.

 

"We succeeded in forming the sharp Cu microbump with a pitch of 10μm by an original process using imprint, photolithography and plating method. It will
contribute to cost reduction and performance improvement such as bandwidth expansion and power consumption reduction in the multi-chip packaging."