Sessions Index

Bio:

Ning-Cheng Lee is founder of ShinePure Hi-Tech. Before that, he has been with Indium from 1986-2021, and with Morton Chemical and SCM from 1982 to 1986. He has more than 30 years of experience in the development of fluxes and solder materials for SMT industries. He received his PhD in polymer science from University of Akron in 1981, and BS in chemistry from National Taiwan University in 1973.

Abstract:

For electronic industry, due to miniaturization trend, low temperature soldering received great attention mainly attributable to low yield caused by thermal warpage. Obviously the lower the soldering temperature, the lower the thermal warpage.
On the low temperature solder alloys, the most popular system is Bi-Sn based alloys, mainly due to cost consideration. While In-Sn system is also feasible to alleviate the thermal warpage issue, the high cost of In confined it to specialty applications where the cost is no longer a major concern.
During the course of adopting Bi-Sn system, industry experienced a series of significant challenges mainly on the reliabilities. In the first place, the brittleness of Bi-Sn made the handling of manufactured devices being vulnerable, particularly for portable devices. Hot tear is another major issue, which often is associated with Bi-stratification of BGA joints.
In this presentation, the challenges on Low Temperature Soldering will be discussed.

 

Bio:

Charles Lin, founder of Bridge Semiconductor, began his career in 1987 at MCC in Texas. He joined the IME of Singapore in 1993 and moved back to Taiwan to lead the Packaging Division of ERSO/ITRI in 1994. After two years, he returned to Singapore as the CTO of Gul Tech, and then CEO of APS, before assuming the roles of Chairman and CEO of Bridge since 2000.
Charles did his post-doctoral fellowship at the University of Texas, Austin, received his Ph.D. from Case Western Reserve University in 1985, and graduated with a Bachelor’s Degree in Chemistry from the National Taiwan University in 1977.

Abstract:

In recent years, several advanced packaging architectures—driven largely by the demands of high-performance computing—have been introduced by wafer fabs and packaging subcontractors. These approaches utilize “ultra-fine interconnects” as a crucial element to connect logic and high-bandwidth memory chips. Such interconnects are typically realized in different forms, for example: silicon interposers with through-silicon vias (TSVs), currently the most prevalent; organic RDL, offering a more cost-effective alternative; and embedded silicon bridges, regarded as the most balanced option in terms of both performance and cost.

Apart from high-performance computing that embeds a silicon bridge, embedding active chips in a substrate also offers distinct advantages over conventional technologies. This face-to-face stacking structure enables highly compact modules and extremely short current loops, resulting in lower interconnect resistance and parasitic inductance. These improvements can reduce both conduction and switching losses, thereby enhancing overall system efficiency.

Fabrication of an embedded die substrate essentially means building a circuit board around the semiconductor die. There are many ways to achieve this goal. Still, the predominant issues are die placement accuracy, substrate warpage, die cracking, dimensional stability, and many more. In this paper, we present a low-cost approach to overcome these drawbacks by embedding the die in a pre-formed cavity of a molded lead frame. The dimension of the cavity is defined by the etched portion of a metal slug, which is surrounded by a plurality of etched-formed pillar arrays in the molding compound. With a typical thickness of 0.15–0.25 mm, the molded lead frame serves as a free-standing metal core, allowing buildup layers to be deposited on both sides, therefore effectively minimizing substrate warpage.  

 

Bio:

Experience
Taiwan Foresight Co.Ltd
President
September 2010- Present (12 years 4 months)

Zygo Corporation
Field Technical Director
February 2004- September 2009 (5 years 8 months)

Corning Incorporated
Assist Product Engineering Mgr.
April 2003- January 2004 (10 months)

E Ink Corporation
process engineer
1998- 2000 (2 years)

Education
NCTU
Master's degree (1994- 1996)

Abstract:

Selective laser etching (SLE) is a technique we conduct for making through glass via (TGV), that allows the fabrication of straight, taper and even arbitrary shaped via path. In this work we attempt to achieve both via quality and throughput with unique Advanced Optical Engine (AOE) femtosecond laser modification and following by in-house KOH wet etching. As an extensive variety of works have been dedicated that perfect straight via at range 15um~100um diameter (up to 1:100 aspect ratio and >>100 selectivity) at high throughput as result. The AOE optimized to maximize throughput in TGV (Through Glass Via) processing. By transforming the intensity distribution of a high-energy femtosecond laser beam from a Gaussian profile to elongated cylindrical beams, in order to achieve superior precision and efficiency. The use of AOE facilitates cylindrical modifications within the glass volume, utilizing single or burst-mode laser pulses. Its adjustable ring size allows precise control over the diameter of the modified cylinder volume. Coordinating it with fully motorize fix gantry Z and XY high speed high accuracy air bearing motion control stage, AOE is compatible with various types of glass, enabling seamless processing of materials volume up to 600mm x 600mm in 1 mm in thickness. This work utilized AOE femtosecond laser system and in-house KOH wet bench etching system with in situ AOI to illustrate volume production stability in TGV specification of top/bottom diameter, roundness, and position accuracy over thousands of >10K Ø100um TGV 1.1t samples @ 1000 shot/second.

 

Bio:

1.SMTA TAIWAN CHAPTER President
2.IMPACT technical Committee
3.ECTC Technical Committee
4.TPCA Semiconductor Committee
5.IMAPS Taiwan BoD
6.IPC/JEDEC /AEC /SEMI Standard Committee
7.iST Group AVP
8.NCTU Polymer MS /EMBA

Abstract:

 With the AI/HPC coming, high performance server, network and telecom products are required to support increasing infrastructure performance demands. The package size for above application will be getting bigger and bigger to afford GPU/CPU/ASIC plus multiple HBMs on one organic substrate. The mechanical and thermal-mechanical strain on PCB pad caused by the big AI/HPC package will be far more than that from conventional flip chip package. In additional, the ultra-low loss material and Cu foil of PCB are introduced for the high speed/ high frequency requirement, which will be concerned with the interfacial adhesion among low loss resin, glass fiber surface treatment and Cu surface roughness. Therefore, find methodology to characterize PCB pad cratering risk will be necessary for potential risk prediction in the service life field.

Cold ball pull testing is used to validate the resistance of PCB pad cratering for the different ultra-low loss dielectric materials (Dk=3~4.2 and Df <= 0.005 @ 1GHz) in the study. The materials were fabricated in multiple PCB shops using a common test board design utilizing a coupon to result in a 16 mil nominal pad size for the pulls. After fabrication, a 20 mil SAC305 ball was SMT attached to the 16 mil nominal pads for pulling. Each material had 3 coupons with 50 pull locations on each to generate 150 data points for statistical analysis. The peak pull force differences of the material builds can be compared to differentiate the results. As a result, the different ultra-low loss dielectric material’s performance to withstand PCB pad cratering can be compared comprehensively with the cold ball pull test.