Sessions Index

Bio:

Hidenori Abe is CTO for semiconductor materials at Resonac Holdings Corporation and Executive director of Electronics Business Headquarters at Resonac Corporation. He leads electronics materials R&D and strategy for semiconductors, substrates and displays. He was previously head of the Electronics R&D Center and Packaging Solution Center, which is an open innovation hub in advanced packaging development. In that role, he directed the launch of JOINT2 in 2021, an advanced packaging consortium targeting 2.xD and 3D packages.
He served as General Manager of CMP Slurry Business Sector for three years and, before that, was Manager of the Marketing Promotion Group in the Innovation Promotion Center. In his role with the Marketing Promotion Group, he promoted new R&D projects, especially those targeting new market segments using new technologies. He also served as Manager of the Business Development Group in the Packaging Solution Center where he had responsibility for promoting the company’s open laboratory to partners such as customers and equipment makers, and for marketing wearable-related materials.

Abstract:

The cutting-edge semiconductors necessary for the evolution of AI are supported by advances in equipment and material technology. The emergence of chiplet package structures has led to increased complexity in packaging, making collaboration between materials manufacturers and equipment manufacturers more critical than ever.
Resonac, a co-creative chemical company that provides a variety of semiconductor materials such as CMP slurry, etching gas, materials for HBM, epoxy molding compounds, substrate core materials, and more, is advancing materials technology development through open innovation activities. Resonac has started a Packaging Solution Center to propose one-stop solutions for customers and has established the co-creative packaging evaluation platform “JOINT2” with leading companies to accelerate the development of advanced materials, equipment, and substrates for 2.xD and 3D packages, especially large panel level interposer and large packages. Additionally, we will soon start an open innovation activity in Silicon Valley called “US-JOINT.” In this presentation, we will describe our co-creation strategy.

 

Bio:

Yoshihisa Kagawa is a general manager of Research Division in Sony Semiconductor Solutions Corporation. He joined Sony Corporation in 2004 and he has been a specialist for BEOL and 3D chip stacking process integration. Currently he manages the development of process integration for stacked CMOS image sensors.

Abstract:

Evolution of CMOS image sensors has been realized by the heterogenous integration technologies such as CuCu hybrid bonding, TSV, multi-layers stacking, μ-bump, CoW and so on. Current trends of 3D integrated CMOS image sensors will be discussed.

 

Bio:

Academic Background:
Ph.D. and M.S., Political Science, National Taiwan University
M.S., Electrical Engineering and Computer Science, University of Michigan
B.S., Electrical Engineering, National Taiwan University

Abstract:

Whether in the cloud—inside massive data centers and AI factories—or at the edge, in our smartphones, laptops, and wearables, users everywhere demand energy efficiency.
In today’s world, electricity is computing power, and computing power is national power.
That’s why every major nation now races on two fronts: expanding its energy supply, while also building ever more efficient AI infrastructures. At the very peak of this pursuit lies one goal — the creation of the world’s most energy-efficient logic chips.
And yet, only one foundry on Earth — TSMC in Taiwan — possesses the capability to mass-produce such advanced AI chips.
On the surface, this is a source of national pride. But beneath that pride lies growing pressure — pressure born from the “struggle of Power Transition” between the US and China.
So where should Taiwan go from here?
What international and domestic forces will shape the fate of Taiwan, TSMC, its vast supply chain — and even the great-power rivalry between the United States and China?
Let’s hear Dr. Wu’s analysis…

 

Bio:

M.Bilal HACHEMI, Ph.D., is a Senior Market and Technology Analyst at Yole Group and currently works within the Manufacturing & Global Supply Chain activities. He contributes on a day-to-day basis to the analysis of semiconductor packaging and IC substrates, Glass Core substrate technologies, their related materials, manufacturing processes, and supply chains.

Prior to joining Yole Group, Bilal conducted experimental research in nanoelectronics and nanotechnologies, with a focus on emerging dielectric materials and their ferroelectric sustainable applications. Over the course of his career, he (co-)authored several papers published in high-impact scientific journals and participated in numerous international conferences. Bilal received a Ph.D. in Nanoelectronics and nanotechnologies from Grenoble Alpes University, France. He also completed a management master’s degree at IAE Grenoble.

Abstract:

The impact of the current megatrends driven by Generative AI (GenAI), HPC and data center hardware is spreading over all the segments of the semiconductor value chain, redefining design requirements from Si die to packaging and system-level assembly, and challenging the manufacturing capabilities, from yield to metrology. Among the most strategically impacted industries, yet historically underappreciated, is the advanced IC substrates (AICS). As computing and memory-hungry applications drive increasing demand, IC substrates are no longer just passive mechanical support, they have become a key number in the equation of high-end performance products due to the added functionalities to AICS, and its contribution to enlarging the packaging size while keeping the same level of stability and controlled warpage. This paper provides a comprehensive overview of the IC substrates’ market and technology trends while being at one of the most challenging periods of its history.
We begin by mapping the recent AI accelerators and HPC processors, from AICS’ perspective, and few AICS’ cross sections of NVIDIA’s H100 & H200 to AMD’s MI300X, where the shift toward large-scale sizes, has imposed a new set of functional and physical requirements on AICS. These include significantly increased substrate sizes (exceeding 120 mm x 120 mm), L/S, and layer counts, interconnect densities, power distribution networks, and embedded passive components. From a market standpoint, we identify a split of the AICS industry. On one end, legacy FC-BGA organic IC substrates, continue to serve the highly demanding markets like AI in high-volume data centers. On the other, a new class of large-format, ultra-high-density substrates is emerging, led by glass core substrate and not only. We map these market and technology trends into a roadmap per technology, extending to 2030. We also assess geopolitical and economic influences, including governmental incentives, CAPEX expansions, that are reshaping IC substrate R&D and manufacturing priorities.
In conclusion, this paper frames advanced IC substrates as no longer just mechanical enablers, but as co-design partners in the age of GenAI. With AICS absorbing growing complexity in signal integrity, power delivery, thermal management, and even photonic integration, they are now central to performance scaling in AI systems.