Heterogeneous Integration for Extreme-Scale AI/HPC:Packaging Beyond the Reticle
發表編號：S36-1時間：15:50 - 16:14 |
Invited Speaker
Speaker: Richard Graf, Distinguished Engineer, Marvell
Bio:
Richard is a distinguished engineer in Marvell focused on architecture of new standard and custom products utilizing advanced packaging technologies. Richard has 25+ years of engineering experience in Marvell, GF, and IBM and 50+ US issued patents.
Abstract:
As frontier AI models scale 4 to 5× per year while HBM capacity only doubles every ~2 years, the semiconductor package has become the primary bottleneck — and the primary lever — for extreme-scale AI/HPC systems. This talk surveys five interlocking engineering challenges (interposer scaling, 3D DRAM integration, power delivery, thermal management, and assembly/ecosystem readiness) that must be solved simultaneously to build packages approaching 10,000 mm² and exceeding 1 kW and argues that the package architect's role is expanding from interconnect substrate design to full heterogeneous system architecture.
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Power Delivery from system to die
發表編號：S36-2時間：16:14 - 16:38 |
Invited Speaker
Speaker: Bassam Abdel-Dayem, Principal Engineer, AWS
Bio:
Packaging and System level Architect
Abstract:
Power is becoming a packaging nightmare with large didt, where the technology needs to innovate and solve to deliver the next generation packaging architectures.
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AI Data Center Energy Efficiency: Challenges and Solutions
發表編號：S36-3時間：16:38 - 17:02 |
Invited Speaker
Speaker: E. Jan Vardaman, President, TechSearch International
Bio:
E. Jan Vardaman is president and founder of TechSearch International, Inc., which has provided market research and technology trend analysis in semiconductor packaging since 1987. She is the author of numerous publications on emerging trends in semiconductor packaging and assembly. She is a senior member of IEEE EPS and is an IEEE EPS Distinguished Lecturer and received the Distinguished Achievement Certificate for Technical Leadership and Expertise in May 2024. She received the President’s Award in 2026 from the Global Electronics Association (GEA) for her contributions to the electronics industry. She received the IMAPS GBC Partnership award in 2012, the Daniel C. Hughes, Jr. Memorial Award in 2018, the Sidney J. Stein International Award in 2019, and she is an IMAPS Fellow. She served on the IEEE CPMT Board of Governors for two terms. Before founding TechSearch International, she served on the corporate staff of Microelectronics and Computer Technology Corporation (MCC), the electronics industry’s first pre-competitive research consortium. She
received her M.A. from University of Texas, in 1981.
Abstract:
AI data centers are driving the value of the semiconductor industry as well as developments in advanced packaging for GPUs/ASIC based accelerators, CPUs, and XPUs. Concerns of energy use and water consumption are driving a system-level approach to provide better solutions. Memory demand is driving the need for an increasing number of HBM stacks, larger interposer sizes, and increasingly complex substrates that require more area. This presentation describes the packaging challenges and potential solutions including increased use of hybrid bonding and co-packaged optics. Trends in system architectures, packages, materials, and cooling options are described.
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AI Server and Rack Scale Power Loss Analysis
發表編號：S36-4時間：17:02 - 17:26 |
Invited Speaker
Speaker: Falconee Lee, Engineering Manager, Intel
Abstract:
The rapid expansion of AI workloads has created scenarios where an 8-GPU server can consume up to 10kW, and an entire rack may exceed 100kW, emphasizing the vital need for power efficiency. This technical presentation provides an in-depth analysis of power loss across power topology, components, Busbar, PSUs, Power shelfs, PCBs, trays, GPU cards, and cables within AI servers and at the rack scale. It also offers proposals and examples for future optimization.
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From Package to Fleet: Building a Reliability Control Plane for AI Infrastructure
發表編號：S36-5時間：17:26 - 17:50 |
Invited Speaker
Speaker: Terrence Tan, Senior Director, Microsoft
Abstract:
Advanced packaging, chiplets, HBM, and D2D fabrics are creating new classes of cross-domain failure mechanisms that cannot be managed solely through traditional manufacturing screens. The presentation focuses on how reliability, telemetry, and AI-driven diagnostics must evolve alongside heterogeneous integration to enable reliable deployment of large-scale AI infrastructure.
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