Sessions Index

Bio:

Dr. De-Shin Liu obtained his Ph.D. in Engineering Mechanics from the University of Missouri-Rolla in 1989. He then served as a senior structural safety project engineer at General Motors in Warren, Michigan, from 1989 to 1991. Currently, he is a full professor in the Department of Mechanical Engineering at National Chung Cheng University in Chia-Yi, Taiwan. His research interests include computational mechanics, micro-impact testing methods, 3D printing techniques for soft materials, and structural failure mode analysis, with applications in electronic packaging design and medical device development.

Abstract:

Three-dimensional (3D) chip stacking has become a key technology in Taiwan’s advanced semiconductor industry, driven by the trend toward System-on-Chip (SoC) integration. Through-Silicon Via (TSV) technology is central to this development, enabling vertical interconnections between chips with reduced signal path lengths, lower resistance, and improved signal integrity. However, TSV structures present reliability challenges. The formation of vias reduces the mechanical strength of the silicon die, and thermal-mechanical mismatches between the silicon substrate and metal filler can induce high interfacial stresses, especially under thermal cycling, potentially leading to structural failure. To address these concerns, the presentation will introduce the Heterogeneous Infinite Element Method (HIEM), a novel simulation approach for analyzing heterogeneous 3D structures. HIEM significantly reduces the degrees of freedom in global models without simplifying the Through-Silicon Via (TSV) interlayer configuration, thereby maintaining high accuracy and computational efficiency. Numerical examples will be presented to demonstrate that HIEM is a powerful tool for optimizing TSV layouts and enhancing the reliability of 3D integrated circuits.
Keywords (Through-Silicon Via, Numerical Method, 3D Packaging Reliability)

 

Bio:
Professor Yu-Lin Shen received his Ph.D. in engineering from Brown University in 1994, and M.S. and B.S. in materials science and engineering from National Tsing Hua University in Taiwan. He was a post-doctoral research associate at Massachusetts Institute of Technology before joining University of New Mexico (UNM) in 1996. He is currently Professor and Chair of the Department of Mechanical Engineering at UNM. Professor Shen has been active in research and teaching in the areas of mechanical behavior of materials and solid mechanics. He is particularly well versed in applying modeling techniques to address micro-mechanical problems related to thin films, microelectronic devices and packages, and composite materials. He has published about 200 research papers, mostly in the form of journal articles. His book titled “Constrained Deformation of Materials” was published by Springer in 2010. In 2005 Professor Shen was elected Fellow of the American Society of Mechanical Engineers (ASME). He has been rated among the World's Top 2% Most Influential Scientists List (Career Impact and Single-year Impact ) by Elsevier/Stanford University.

Abstract:
The pursuit of miniaturization, enhanced performance, and energy efficiency in semiconductor devices has driven innovations in advanced packaging technologies. Among these, glass substrates and through glass vias (TGVs) have emerged as promising solutions, due to their advantages in enhancing device functionality and performance. Traditional organic substrates and silicon-based interposers face limitations in electrical performance and scalability. Glass substrates offer several benefits. Their inherently low dielectric loss and high electrical resistivity make them suitable for high-frequency and radio-frequency (RF) applications. Glass is non-conductive, thus eliminating crosstalk in dense circuits. Additionally, glass provides exceptional dimensional stability and surface flatness, enabling precise lithography for fine-pitch interconnects. The transparency of glass also opens doors to photonic integration. Glass’s thermal stability further ensures reliability during high-temperature processes such as reflow soldering, while its tunable coefficient of thermal expansion (CTE) can be better matched to adjacent materials to minimize thermal stress. TGVs complement these advantages by enabling vertical interconnections in 3D packaging, enhancing device density and shortening electrical pathways. Compared to through-silicon vias (TSVs), TGVs can achieve lower parasitic capacitance, therefore improving signal integrity.

Despite their potential benefits, glass substrates and TGVs still face significant hurdles. The brittleness of glass raises concerns about mechanical reliability during handling, dicing, and thermal cycling. Fabricating high-aspect-ratio TGVs is technically challenging; processes like laser drilling or chemical etching must balance precision with cost-effectiveness. Metallization of TGVs also poses adhesion issues, requiring novel deposition techniques. Furthermore, CTE mismatch with external materials still exist, and internal CTE mismatch and modulus mismatch between glass and copper TGVs also lead to localized stresses, risking delamination or cracking. As in all substrates in electronic packaging, shape change caused by warpage has always been a concern for structural integrity.

In this presentation we highlight our recent numerical study on the warpage resistance of glass substrate containing TGVs. The resistance is characterized by the bending rigidity of the plate-like structure. A series of finite element analyses are performed, taking into account the square array of TGVs inside the glass matrix. The simulations utilize a representative composite structure, with appropriate boundary conditions imposed to ensure symmetry and periodicity. Various TGV concentrations under both the unidirectional bending and biaxial bending are considered. Bending rigidity is determined by the prescribed curvature and the reaction moment obtained from the computational analysis. It is found that a higher TGV fraction results in a greater bending rigidity and thus warpage resistance, which is due to the higher stiffness of copper compared to glass. A higher TGV fraction, however, leads to higher magnitudes of local normal stresses. When plastic yielding of copper is taken into consideration in the modeling, the TGV/glass interface region near the free surfaces is prone to localized plastic deformation. Permanent warpage occurs after the bending moment is completely removed. Implications of the numerical findings on potential damage of the TGV structure are discussed.

 

Bio:
The speaker is a graduate student at National Tsing Hua University, focusing on reliability simulation of packaging structures. Her work involves finite element analysis and the use of equivalent modeling methods to closely reflect real-world conditions.

Abstract:
Three-dimensional finite element analysis (FEA) is commonly used to assess solder joint fatigue, a frequent failure mechanism in wafer-level packaging (WLP) under thermal cycling conditions. However, such simulations typically involve hundreds of thousands of elements, resulting in high computational costs. To resolve this issue, multi-point constraints (MPC) and equivalent beam elements are introduced to reduce the element and make the simulation efficiently.
A 3D FEA model incorporating MPC and equivalent beams is developed in this study. MPC is applied to the four solder balls located farthest from the neutral point, while non-critical solder joints are substituted with equivalent beam elements. The cross-sectional area of the equivalent beam was modified to align its mechanical response with that of the solder ball under realistic conditions. All materials are assumed to behave linearly, except for the solder joint. The solder joint follows the Chaboche kinematic hardening model, and the geometry of the solder joint is derived using Surface Evolver. The model is subjected to thermal cycling based on JESD22-A104D Condition G. Finally, the Coffin-Manson equation is used to estimate fatigue life.

 

Bio:
Dr. Cadmus Chang-Ann Yuan is currently a Professor at the Department of Mechanical and Computer Aid Engineering, Feng Chia University in Taichung City, Taiwan, investigating the AI algorithms and finite element methods for industrial applications.

Abstract:
AI-driven applications have rapidly become a major force in semiconductor development, leading to increased demand for advanced packaging solutions. Among these, heterogeneous integration (HI) has emerged as a critical enabler for high-performance computing due to its capacity to support complex interconnect architectures and high-density component integration. One notable example is the Chip-on-Wafer-on-Substrate (CoWoS) technology, which leverages silicon interposers to integrate logic and memory dies for enhanced bandwidth and system performance.

However, accurately modeling HI structures using finite element (FE) methods remains computationally expensive due to their geometric and material complexity. To mitigate this, prior studies have proposed using equivalent beam models as simplified representations of solder joints. Banijamali et al. demonstrated their application in 3D IC packages, while Cheng et al. and Yuan & Chiang extended the methodology to BGA and WLCSP packages, respectively. These beam models, especially when constructed with multiple sections, can replicate key thermo-mechanical behaviors such as temperature-dependent stiffness and creep response.

This study builds a full vertical stack, comprising the molding compound, chip, substrate, solder joint (or its equivalent beam), and PCB. Moreover, this study builds the equivalent beam models under various boundary conditions, including conventional node merging, multi-point constraints (MPC), and full column integration. The solder joint is modeled using the Anand viscoplastic law, while the equivalent beam adopts the Chaboche nonlinear hardening model. Through external nodal loading (shear, axial, and moment), the mechanical responses—expressed as reaction forces and moments—are compared between the solid solder model and the simplified beam models.

The results aim to find the most suitable configuration for efficiently and accurately predicting solder joint behavior in complex HI packages. Furthermore, the methodology is extendable to other interconnect types such as flip-chip and micro-bumps, offering a scalable framework for reliability prediction in next-generation semiconductor systems.

 

Bio:
Prof. Yu-Jui Liang is an Assistant Professor in the Department of Aeronautics and Astronautics at National Cheng Kung University (NCKU), Taiwan. His research expertise includes finite element modeling (FEM), composite materials, computer-aided engineering (CAE), and electronic packaging analysis. Dr. Liang is actively engaged in interdisciplinary research combining structural mechanics, numerical simulation, and advanced material design, with applications ranging from aerospace systems to semiconductor packaging. He also leads collaborative projects with both academic institutions and industry partners.

Abstract:
As semiconductor IC packaging advances, increasing design complexity necessitates higher resolution in numerical model meshes, leading to an exponential growth in computational demands. Traditional Computer-Aided Engineering (CAE) methods, which rely on constructing model with detailed geometries, are becoming impractical due to hardware limitations. To address this challenge, a novel equivalent finite element model is proposed for warpage prediction in printed circuit boards (PCBs) by using the pixel-based approach of equivalent material properties. This approach streamlines simulation by optimizing mesh handling and computational efficiency, significantly reducing processing time while maintaining predictive accuracy.

 

Bio:
The speaker is currently a graduate student at National Tsing Hua University, specializing in reliability simulation of advanced packaging structures. Her research focuses on finite element modeling and thermomechanical analysis to assess structural integrity and failure risk under actual operating conditions.

Abstract:
As Moore’s Law steadily approaches its physical and economic limits, the semiconductor industry is undergoing a paradigm shift—moving beyond traditional transistor scaling toward advanced packaging technologies that can enhance performance at the system level. In this context, the “More-than-Moore” roadmap has gained significant traction, particularly with the rise of heterogeneous integration and chiplet-based architectures. These approaches allow multiple functional dies to be modularized and integrated within a single package, offering improved design flexibility, enhanced manufacturing yield, and greater integration density. However, this structural evolution also introduces a range of reliability challenges. Complex packaging configurations give rise to issues such as thermomechanical stress accumulation, coefficient of thermal expansion (CTE) mismatches, mechanical warpage, and solder joint fatigue failures—factors that can severely impact device fatigue life and operational stability.
To address these reliability concerns, this study proposes a simulation framework that combines the Global-Local Finite Element Method (FEM) with Equivalent Beam Theory. The framework incorporates Multi-Point Constraints (MPC) and refined meshing techniques to enhance both simulation accuracy and computational efficiency. SAC305 is employed as the solder material, and thermal cycling conditions are defined from –40 °C to 125 °C based on JEDEC standards. Thermal-mechanical coupled simulations are conducted using ANSYS APDL, enabling the precise identification of high-stress concentration areas and probable failure location within the package.
Moreover, this study investigates how the proposed methodology can be effectively applied to the rapidly evolving field of chiplet-based package designs. These packaging technologies are widely considered critical to the next-generation semiconductor ecosystem, particularly in high-performance computing. The ultimate objective of this research is to establish a validated and practical finite element model capable of predicting the reliability and failure mechanisms of advanced chiplet packages. By comparing simulation results with empirical data from real package structures, the model's accuracy and practical utility are confirmed. This FEM framework not only provides powerful design assistance, significantly shortens development cycles and reduces trial and error costs, but also improves overall design robustness and market competitiveness. Ultimately, it empowers engineers to conduct early-stage risk assessments and design optimizations, meeting the growing demand for reliability and performance in advanced semiconductor packaging.
Keywords – Chiplet Packaging, Global-local Finite Element Method, Failure Analysis, Thermo-mechanical Stress.

 

Bio:
Jed Chien is a simulation specialist with over 10 years of experience in CFD and FEM, focusing on semiconductor packaging, underfill processes, and digital twin technologies to improve design efficiency, reduce development cycles, and enhance product reliability through advanced modeling and process optimization. Previously, Jed in charge of mold flow simulations Lab for fluid fields at ASE-CL, applying software verification to semiconductor engineering across various flow and fluid mechanics scenarios.

Abstract:
This paper focuses on predicting and optimizing flux residue and process parameters in packaging products using flux, without being limited by scale model constraints, such as simulating a 1/10,000 size difference (bump size/pitch <5µm versus space height >50,000µm). The study aims to assess how various factors—such as nozzle size, angle, distance, and flow parameters—affect the flux residue during flux cleaning, particularly for products with large, small, or fine-pitch bumps. The use of common parameters across all products may not achieve effective cleaning results, and residual flux ions in high humidity conditions could cause ionic migration, leading to metal deposition between electrodes and short circuits. Additionally, halogen compounds in residues may cause electroplating corrosion, affecting wire bonding strength and curing quality.

This study employs CFD software to analyze flow fields, construct working space models in a part of strip, and evaluate multiple conditions, including the nozzle of cone angle, spacing, movement speed, distance, and flow rate. Observations are made on the flux through bumps and the effects of nozzle diffusion on each package. The transient moving simulation with varying angles examines how water flow rates impact the bumps under the die.

The technical breakthrough lies in modeling the multiphase interaction of water and air flows, accurately reflecting the actual conditions within water tubes and mixing nozzles. Conventional approaches often result in initial divergence due to design limitations such as diffusion angles and splashing effects. In contrast, the patented nozzle utilizes a multi-arc conical geometry instead of a traditional cone. This design, when interacting with the bump mesh layer—characterized by a 1/10,000 scale difference it can induce abnormal momentum inversion due to angular diffusion and Finite Volume Method (FVM) cell zone discretization. Through optimization of geometric configurations and refinement of governing equations, the simulation achieved significantly improved convergence behavior.

This methodology enables a comparison of flux residue in FC device cleaning processes, taking into account varying process parameters and equipment capabilities across different package types particularly in fine-pitch bump configurations. The simulation results indicate that packages oriented perpendicularly to the cleaning nozzle experience the lowest water mass flow rates 0~90kg/(m^2 s). In contrast, packages with a pitch distance of 8 mm or greater from the nozzle demonstrated enhanced flow penetration within the bump regions. Furthermore, the bumps located at the center of three adjacent packages exhibited the least exposure to cleaning flow, suggesting a potential risk of incomplete flux removal in those areas.