Sessions Index

Abstract:
The temperature of lithium-ion batteries (LIBs) affects their performance and lifespan. Extremely high temperatures can accelerate side reactions within the cell such as solid electrolyte interphase (SEI) decomposition and anode-electrolyte reaction, which lead to thermal runaway. Therefore, numerical investigation of thermal behavior and thermal stability analysis for LIBs are crucial for mitigating thermal runaway and designing battery thermal management system (BTMS).
In this study, thermal behavior of a cylindrical 18650 LiFePO₄ battery is numerically investigated under extremely high charging and discharging conditions. An electro-thermal model and a thermal abuse model are coupled in the numerical model, and thermal stability under various C-rate and convective heat transfer coefficients (h) are evaluated. In this study, a cylindrical 18650 LiFePO₄ battery with a nominal capacity of 1.4 Ah is considered. Thermal behavior of the cell is analyzed using the two-dimensional heat conduction equation which considers the domain of 9 mm in the radial (r) direction and 65 mm in the axial (z) direction. For heat generation terms, electro-thermal heat (QElectro-thermal) and thermal abuse heat (QThermal-abuse) is considered. QElectro-thermal is the heat generation rate during charge or discharge operations, and QThermal-abuse represents the heat generation rate generated by side reaction of battery components. Thermal behavior for LIBs during charging and discharging is evaluated by varing the C-rate from 6 C to 16 C and h between 0 W/m2K and 25 W/m2K. As the C-rate increases, electro-thermal heat generation also increases, which accelerates side reactions and leads to a higher rate of heat production. Therefore, the surface temperature increases steadily during charging and rises more rapidly, which leads to a shorter time to thermal runaway. Thermal runaway onset time (tonset) serves as a parameter of the risk of thermal runaway, which represents that a shorter onset time implies a higher risk of thermal runaway. Maximum temperature (Tmax) also represents the severity for thermal runaway. tonset decreases and Tmax increases as the C-rate grows, which means risk and severity of thermal runaway are intensified with increasing C-rate.
When h increases, more heat is removed as growing h, delaying or suppressing side reactions. Therefore, the overall heat generation is reduced, and thermal runaway is either significantly delayed or entirely prevented. However, Tmax rises with higher h, which represents growing severity of thermal runaway. This can be attributed to the time-integrated heat accumulation. Enhanced cooling delays the thermal runaway, extending the operation time. Consequently, the total internal heat accumulated over this prolonged period becomes greater than the surface heat dissipation.

Abstract:
The continued scaling of heterogeneous integration and three-dimensional chip stacking has intensified the demand for reliable fine-pitch interconnect technologies, with Cu–Cu hybrid bonding emerging as a promising alternative to conventional solder-based interconnection approaches for advanced semiconductor packaging. Previous studies have mainly relied on simplified stress analyses or parametric studies that examined the effects of individual material and process variables, such as crystallographic orientation, impurity content, temperature, and pressure. While these studies provide useful trends, numerical simulations capable of capturing the overall Cu–Cu bonding process from initial contact to bonding-interface elimination at the process level remain relatively limited.
This work presents an experimentally validated numerical simulation study of the Cu–Cu bonding process using thermocompression bonding as a controlled experimental platform. The main objective is to move beyond empirical correlations between bonding conditions and bonding quality, and to describe how temperature and pressure affect the evolution of the Cu–Cu bonding interface. To achieve this, a multiscale simulation approach was developed by combining thermo-elastoplastic finite-element analysis, pressure-gradient-driven material transport, and phase-field modeling.
The proposed simulation approach describes Cu–Cu bonding as a two-stage process. In the first stage, pressure-gradient-driven material flux consolidates the initially rough and discontinuous Cu–Cu interface. Finite-element simulations show that local hydrostatic stress and pressure gradients near contacting asperities lead to nanoscale void closure at the bonding interface. In this stage, applied pressure primarily governs interfacial void elimination, whereas temperature induces compressive thermal stress due to the coefficient of thermal expansion mismatch between Cu and the substrate.
In the second stage, once interfacial voids are sufficiently reduced and the local pressure gradient is relaxed, bonding proceeds through grain-boundary-mediated microstructural evolution. A phase-field model coupled with elasticity was used to describe grain growth, grain-boundary migration, and bonding-interface elimination during annealing. The simulation captures how curvature-driven and strain-energy-assisted grain-boundary motion contributes to the gradual disappearance of the original bonding interface, leading to microstructural coalescence across the Cu–Cu interface.
The proposed multiscale simulation study was validated through comparison with experimental bonding results, including bonded-area evolution, interfacial void morphology, grain-growth behavior, and bonding-interface elimination. The validated simulation approach was further applied to a representative Cu–Cu hybrid bonding configuration using a patterned-wafer geometry derived from the Cu pad dimensions and pitch of the provided samples. This patterned-wafer simulation captured dielectric confinement and pad-to-pad mechanical interactions during annealing, revealing the constrained stress state of SiO₂-embedded Cu pads. Consequently, this work provides a comprehensive and experimentally supported numerical description of the Cu–Cu bonding process from initial interfacial contact to microstructural coalescence, offering practical guidance for simulation-assisted process design, bonding-condition optimization, and reliability improvement of fine-pitch Cu interconnects for advanced heterogeneous integration.

Abstract:
Capillary underfill (CUF) is a critical enabling process in advanced high-density packaging, where progressively narrow inter-chip gaps and dense micro-bump arrays pose severe challenges for resin flow prediction and process control. Complex interactions among surface tension, capillary pressure, and extreme geometric confinement frequently give rise to flow-front instability, flow retardation, and bubble entrapment—defects that are difficult to anticipate and costly to correct. To overcome these challenges and the prohibitive computational cost of conventional three-dimensional (3D) simulation, this study presents a Hybrid Dimensional Simulation Framework integrated with an Equivalent Bump Group (EBG) model. By coupling 3D bulk flow with thin-gap Hele–Shaw regions and homogenizing bump-array resistance into equivalent permeability parameters, the framework achieves dramatic reductions in computation time while preserving high physical fidelity—a scalability advantage that amplifies with increasing packaging density. Validated against glass-based multi-chip experiments, the framework delivers three key capabilities: (i) evaluation of temperature-dependent rheological properties for optimal material selection; (ii) optimization of dispensing strategies, including multi-pass waiting times and dispensing path recession distances; and (iii) reliable identification of bubble entrapment risk zones under varied process conditions. Excellent agreement between numerical predictions and experimental observations confirms this framework as an efficient and scalable digital tool for defect prevention and process yield improvement.

Abstract:
Real world process physics is crucial for transforming outcome prediction from an idealized mathematical calculation into a high-accuracy manufacturing tool, since simplified models often underrepresent process-dependent behavior. In semiconductor packaging, wire-bonding forms electrical interconnections, and the resulting wire-loop profile directly affects electrical performance and yield. Without in-situ and accurate simulation tools, production tuning would rely heavily on operator experience and trial-and-error. In this study, we enhance the well-known linkage-spring model (LSM) from a simplified loop-formation model into a practical prediction framework by incorporating real process considerations and data-driven calibration. Validation using in-house experimental measurements shows that the proposed method achieves prediction accuracy suitable for practical industrial wire-bonding applications while maintaining computational efficiency.
In the classical LSM, the bonding wire is discretized into inextensible rigid segments connected by rotational springs. The governing equations are nonlinear algebraic equations composed of geometric compatibility and moment equilibrium. The former enforce consistency between the projected wire geometry and the prescribed capillary position, whereas the latter express spring moments as functions of the relative rotations between adjacent segments. Since the formulation contains no time-dependent terms, each capillary step is treated as a quasi-static equilibrium problem and is solved using Newton’s method by minimizing the residuals. Although this formulation efficiently captures large loop deformation, its reduced-order discretization makes localized plastic kink formation sensitive to segment resolution and difficult to model accurately.
To overcome this limitation, several physics-aware correction rules are introduced to embed practical bonding behavior into the simulated loop evolution. These rules guide the model by imposing process-dependent constraints, including local rotation limits, length-dependent stiffness correction, pull-out length modeling, non-plastic state restoration, and numerical stability controls, among others. With these correction rules, the successful simulation rate increases to over 98% across more than 10,000 in-house measurement cases, whereas the classical LSM shows limited robustness for practical loop cases.
Key model inputs, including the critical bending angle for plastic kink formation, correction-rule parameters, and several material properties, are difficult to determine directly from the bonding process, introducing uncertainty into the model setup. Therefore, a genetic algorithm (GA) is introduced to calibrate these uncertain parameters by minimizing the profile error between the simulated and experimental loop profiles. With GA tuning, the average within-tolerance rate across all measured cases increases from 43.1% to 83.5%, demonstrating greatly improved profile prediction accuracy while reducing manual tuning and improving the practical reliability of the LSM-based prediction framework.
Keywords: Genetic Algorithm, Linkage-Spring Model, Numerical Simulation, Wire-bonding, Loop Profile Prediction.

Abstract:
The continuing miniaturization and functional integration of electronic devices have increased the structural complexity of semiconductor packaging substrates. As finer microvias and multilayer build-up structures are introduced, ensuring interconnection reliability becomes increasingly important. Thermal stresses generated by differences in the coefficients of thermal expansion of the constituent materials can cause cracking, delamination, and electrical failure during manufacturing or service. Thermal cycling tests (TCTs) are therefore widely used to evaluate substrate reliability. However, the best conditions are often selected empirically, and increasing the temperature range to accelerate failure may alter the dominant failure mechanism. In particular, both the glass transition temperature (Tg）of the build-up insulation film and the applied temperature range (△T) may influence the mechanical response of the substrate and the resulting reliability evaluation.
In our previous study, TCT conditions with upper temperatures below and above the build-up film (Tg) were compared. However, because those conditions also had different △T values, the individual effects of exceeding Tg and increasing △T could not be clearly separated. In this follow-up study, three TCT conditions were designed to independently examine these two factors.
Two three-layer stacked microvia substrates with identical materials, dimensions, and circuit designs but different interconnection qualities were evaluated. Different electroless Cu plating processes were applied at the microvia bottoms, resulting in substrates with different degrees of voiding. The build-up insulation film had a Tg of 153 °C. TCT was conducted with a 15 min dwell at each temperature under three conditions: -55/150 °C, -30/175 °C, and -55/175 °C. Daisy-chain resistance was monitored in situ, and failure was defined as an increase to more than twice the initial resistance.
The -55/150 °C and -30/175 °C conditions had the same △T of 205 °C, while their upper temperatures were below and above Tg, respectively. Under the below-Tg condition, the substrate with less voiding at the microvia bottoms showed clearly superior reliability. Under the above-Tg condition, however, the failure distributions of the two substrates became substantially closer. This indicates that exceeding Tg, rather than △T alone, reduces the sensitivity of TCT to differences in interconnection quality.
The effect of △T was further examined by comparing -30/175 °C and -55/175 °C. Although the two conditions had different △T values of 205 and 230 °C, respectively, both exceeded the build-up film Tg. Under both conditions, TCT showed limited sensitivity to differences in substrate interconnection quality. However, the larger △T caused failures to occur within a narrower cycle range, indicating that the magnitude of the temperature excursion affects the dispersion of failure cycles.
These results suggest that once the upper test temperature exceeds Tg, TCT may no longer effectively distinguish differences in substrate interconnection quality, regardless of △T. Therefore, to accurately compare interconnection reliability, the upper test temperature should remain below Tg. At the same time, increasing △T appears to narrow the failure-cycle distribution. Further investigation is required to determine whether the same effect of △T is also observed when the upper test temperature remains below Tg.

Abstract:
Mass transfer and repair in advanced packaging—spanning MicroLEDs, VCSELs, and chiplets—require algorithms that can plan multi-step discrete shifts under practical constraints such as minimizing motion and adapting to defects. We introduce a differentiable transfer module that embeds discrete shift operations into a trainable computation graph, advancing differentiable combinatorial optimization. Compared to local proximity search, our approach achieves superior repair performance and supports flexible objectives such as minimizing transfer steps. Unlike reinforcement learning, it avoids handcrafted feature extractors, converges faster, and scales to large arrays. Beyond MicroLED repair, the framework extends to advanced packaging tasks such as chiplet transfer, wafer bonding, and overlay correction, offering a scalable approach for discrete alignment in next-generation semiconductor manufacturing.

Abstract:
As semiconductor process scaling approaches its physical limits, advanced packaging technologies such as System-in-Package (SiP), chiplet, and CoWoS-like packaging have become important for sustaining system performance. However, the coefficient of thermal expansion (CTE) mismatch among various materials within the structure induces thermal stress, leading to fatigue failure in solder joints and micro-bumps. While finite element analysis (FEA) is widely used to evaluate such reliability concerns, using a fully detailed 3D solid model results in a very large number of mesh elements, leading to high computational cost and an efficiency bottleneck in reliability analysis.
To improve simulation efficiency, this study extends the equivalent beam approach to two complex packaging architectures: chiplet and CoWoS. First, full models are used to conduct JEDEC accelerated thermal cycling test (ATCT) simulations to identify the earliest failure locations. Subsequently, an equivalent beam model is introduced to replace all solder balls and the micro-bumps of the memory and compute dies. Although one-dimensional beam elements cannot precisely capture local shear deformation, they can still correctly identify the earliest failure hot spots, thereby reducing simulation time.
In addition, an integrated model is proposed to balance efficiency and accuracy. This model retains the 3D solid mesh only in the failure-prone hot-spot regions, while replacing the remaining areas with equivalent beams. By integrating the global-local finite element method, adjusting the equivalent beam cross-sectional area, and controlling the mesh size, this model reduces overall computational cost while keeping fatigue-life prediction error within an acceptable range.
The results indicate that, across different packaging structures, the effect of uniformly adjusting the equivalent beam radius on fatigue life is inconsistent. Future research will further investigate the effects of solder ball dimensions, material properties, boundary conditions, and varying architectures. By validating with additional test vehicles, the goal is to establish a general, reliable standard procedure for equivalent-beam analysis in advanced packaging.
Keywords – Chiplet; CoWoS-like; Accelerated thermal cycling test; Equivalent beam model; Global-local finite element method; Mesh size control