Sessions Index

Abstract:

​Owing to the rapid development of the semiconductor industry, the heat dissipation from electronic devices increases drastically with increasing device logic gate number and operation speed. The heat dissipation of a single chip doubled from 70 W in 2001 to 150 W in 2011 and expected to 2,800 W in 2027. The cooling technologies have undergone changes from direct air cooling to forced convective liquid cooling and evolutionary to two-phase evaporating cooling in the past years. For resolving the high-density heat dissipation problem, it is popularly to reduce the channel size to accommodate more heat transfer area on a small heating base area and to be the so-called microchannel heat exchangers. The heat transfer performance of coolant flow in microchannel heat exchangers increased several times through the flow passage shape improvement and channel surface modification. However, the exponential growth rate of heat dissipation is much faster than the improvement in heat transfer performance of micro channel heat exchangers in the past years. What will be the thermal solution for high heat flux devices? Are there any innovative cooling methods that can handle this extremely high flux heat dissipation?

Abstract:
1. INTRODUCTION
Embedded ultra‑thin devices play an important role in automotive applications and in edge‑AI applications employing EMIB. Vibration induces cyclic mechanical stresses in embedded ultra‑thin devices. Firstly, vibration induced stresses can shift electrical parameters and cause drift or drift like behavior. Secondly, vibration induces mechanical stresses that can cause reliability problems in ultra‑thin chips, such as cracking and delamination. However, little is known about how stress develops in embedded ultra‑thin devices during vibration testing, which significantly affects device performance and reliability.

2. METHODOLOGY
In order to address the problems, piezoresistive stress sensors are designed, fabricated, and calibrated in this study for in‑situ stress measurement of an embedded ultra‑thin device during vibration testing. One sensor group consists of four resistors (Fig. 1). Two resistors are designed and placed orthogonally (in two crystal orientations) to measure the longitudinal and transverse components of the applied stress (σx, σy). The resistance of them is around 0.625 kΩ. Another pair of resistors are rotated by 45º and 135º, respectively, with respect to the axis of the parallel direction, and are designed for other purposes.

3. RESULTS
Fig. 2 shows fabricated stress sensors. Fig. 3 shows cross-sectional view of the embedded ultra-thin 50 μm stress sensor chip in the test board. Fig. 4 shows assembled stress sensor chips in the test board. Fig. 5 shows vibration testing setup. Fig. 6 shows setup for in-situ stress measurement. The in situ stress measurement results during the vibration test are shown in Figs. 7–9.

4. NOVELTY AND IMPACT
The novel aspects and significance of this work are shown below:
1. Piezoresistive stress sensors are designed, fabricated, and calibrated.
2. The test board for vibration test is designed and fabricated.
3. The assembly process for embedding the ultra-thin sensor chip into the board is developed.
4. An experimental set-up for in‑situ stress measurement of an embedded ultra‑thin device during vibration has been established.
5. In‑situ stress values obtained during vibration testing are important for enhancing survivability under service conditions, particularly for automotive applications and for edge‑AI applications using EMIB.

Abstract:
■Introduction
Advanced heterogeneous integration technologies increasingly require large-area wafer-level packaging for AI and high-performance computing applications[1]-[3]. However, package warpage caused by thermal stress mismatch between silicon and molding materials remains a critical challenge, resulting in wafer handling difficulties, process instability, and manufacturing yield loss[4] as shown in Figure 1. Previous studies have demonstrated that reducing mold resin volume is effective for suppressing warpage in Chip-on-Wafer (COW) structures using waffle wafers[5][6]. Although significant warpage reduction has already been achieved using waffle wafers, further suppression is required to improve process stability and manufacturability for large-area packages. To address this challenge, a novel counter ring structure is proposed in this study. The structure intentionally retains mold resin along the wafer sidewall and backside edge of the wafer after trimming, generating a balancing stress that counteracts thermally induced package deformation.

■Simulation Setup
FEM analysis was performed to evaluate the effectiveness of a counter ring structure for warpage control in a 300 mm waffle wafer package. Figure 2 shows the proposed structure, where mold resin is retained along the wafer edge to form a balancing ring. Ring width and thickness were used as design parameters. The waffle wafer consisted of 3 mm × 3 mm trenches with a depth of 70 μm, as shown in Figure 3. Material properties were based on experimentally validated models (Table 1). The temperature ranged from 125 °C to 25 °C, with the molding temperature defined as the stress-free state.

■Results and discussion
Figures 4 and 5 shows the simulated warpage of the conventional structure and the proposed counter ring structureAfter resin molding, the waffle wafer exhibited a warpage of 1,073 μm, whereas the counter ring structure reduced it to 395 μm, corresponding to a 63% reduction. The retained edge resin generated a counterbalancing stress that suppressed global package deformation. Parametric FEM analysis revealed that warpage decreased with increasing ring width, reaching approximately 400 μm. Figures 6 and 7 shows the simulated warpage after resin thinning. While resin thinning reduced the overall deformation because of the decreased mold resin volume, the deformation mode changed significantly. In the conventional structure, the wafer maintained a smile-type profile. In contrast, increasing the counter ring width gradually shifted the deformation toward an angry-type profile. This trend indicates that the counter ring controls not only deformation magnitude but also deformation
direction. The transition from smile-type to angry-type deformation suggests the existence of an intermediate condition where wafer curvature approaches zero. Therefore, optimization of counter ring geometry is expected to enable a near-warpage-free condition through stress balancing.
■Conclusions
In summary, a counter ring structure was evaluated as a structural warpage control approach for large-area waffle wafer packages by FEM analysis. Optimization of ring geometry reduced warpage to approximately 395 μm, demonstrating the effectiveness of structural stress balancing. The results also revealed a transition from smile-type to angry-type deformation during resin thinning as the counter ring effect increased. This behavior suggests the existence of a near-warpage-free condition between the two deformation modes. Therefore, the proposed counter ring structure enables active control of both deformation magnitude and direction through geometric optimization. These findings provide a practical design guideline for realizing near-warpage-free large-area wafer packages for future heterogeneous integration technologies.

Abstract:
As redistribution layer (RDL) dimensions continue to shrink toward sub-2 μm and package sizes increase, advanced panel-level packaging (PLP) requires highly reliable temporary carrier systems capable of supporting both ultra-fine patterning and large-area processing. In particular, mechanically debondable carrier systems are attracting increasing attention due to their process simplicity, low cost, and compatibility with large-panel manufacturing. However, conventional mechanical debond technologies suffer from a trade-off between initial peel strength and post-thermal debondability. Insufficient peel strength can cause peel-off failures during build-up processes, while excessive adhesion may result in debond failures after high-temperature processing. In addition, the influence of substrate surface roughness on ultra-fine circuit formation has not been fully clarified.
In this study, a novel mechanically debondable carrier technology was developed to independently control peel strength and thermal stability. The proposed release structure consists of Cu, Ti, and an inorganic release layer. Investigation of conventional structures revealed that thermal diffusion of Ti significantly affects adhesion behavior during thermal exposure, leading to undesirable increases in peel strength after processing. Based on this mechanism, new process parameters were introduced to separately control initial adhesion strength and thermal stability.
The developed technology enabled continuous peel strength control from 5 to 35 gf/cm while maintaining stable mechanical debond performance after thermal exposure at 230°C for extended durations and subsequent exposure up to 350°C. Process evaluations confirmed that stable debonding could be achieved at peel strengths of 30 gf/cm or lower. Furthermore, no process-induced peel-off failures were observed at peel strengths of 10 gf/cm or higher, demonstrating that both process reliability and debondability can be achieved within a practical operating window. The technology also suppressed process-induced delamination associated with panel warpage and thermal stress.
In parallel, the relationship between substrate surface roughness and fine-line patterning capability was investigated. Circuit fabrication studies demonstrated that stable formation of sub-2 μm circuitry can be achieved when substrate surface roughness (Rz) is controlled to less than approximately one-tenth of the target line width. This finding provides a practical design guideline for future ultra-fine-pitch PLP manufacturing and highlights the importance of substrate surface quality in next-generation packaging technologies.
The proposed technology enables independent control of peel strength and thermal stability, overcoming a key limitation of conventional mechanically debondable carrier systems. To the best of our knowledge, this is the first mechanically debondable carrier technology that combines high thermal stability with seamless peel strength tunability over a wide operating range. Furthermore, a practical surface roughness guideline for sub-2 μm circuit formation was established. These results demonstrate a promising platform for next-generation high-density PLP applications in AI and high-performance computing (HPC).

Abstract:
Process-induced warpage driven by the cure shrinkage of Epoxy Molding Compounds (EMC) stands as a critical bottleneck in advanced semiconductor packaging. Traditional modeling often relies on simplified, constant CTE assumptions that fail to capture transient stress states.
This study presents a process-oriented characterization and numerical modeling framework to isolate and quantify the distinct chemical and mechanical shrinkage components across the curing history. A 3-layer substrate/epoxy/diced-silicon test vehicle was evaluated, employing a structurally similar glass-substrate vehicle to minimize confounding thermo-mechanical mismatch. In-situ 3D warpage was monitored using a projection moiré-based TDM system, utilizing a specialized matte anti-reflective coating to suppress optical noise between the transparent glass and reflective silicon. Cure-induced shrinkage changes were decoupled using the epoxy`s gelation boundary into post-gelation chemical shrinkage and cooling-induced mechanical shrinkage. These behaviors were implemented into a dynamic FEA framework. The proposed framework demonstrates an exceptional correlation with experimental transient profiles, significantly improving warpage prediction accuracy and providing an optimization tool for advanced packaging architectures, including HBM and glass cores.

Abstract:
As heterogeneous integration accelerates to address the physical scaling limits of Moore's Law, 2.5D Chip-on-Wafer-on-Substrate (CoWoS) architectures have become a common platform for high-performance computing (HPC) and artificial intelligence (AI) hardware. Placing a high-power System-on-Chip (SoC) together with multiple High Bandwidth Memory (HBM) modules on a single silicon interposer provides high bandwidth. However, this dense integration also causes localized heat accumulation, raising concerns about thermal management and cross-die reliability.
To evaluate steady-state thermal behavior while reducing the high computational cost associated with the multi-scale geometry, this study develops a finite element method (FEM) framework based on Equivalent Material Theory. The dense interconnect features, specifically the micro-bump and C4 bump arrays together with their underfill matrices, are replaced with homogeneous equivalent layers derived from the Rule of Mixture. Multi-Point Constraints (MPC) are applied at discontinuous interfaces to preserve the continuity of the temperature field and the heat flux. In addition, the thermal boundary parameters are calibrated iteratively from empirical formulas to define the nonlinear natural convection and thermal radiation coefficients as a function of surface temperature.
Finite element analysis shows that under the baseline passive cooling configuration, the system exhibits clear inter-die thermal coupling. Due to the high multi-interface thermal resistance along vertical paths, the heat generated by the SoC spreads laterally across the shared silicon interposer, raising the temperature-sensitive HBM. To reduce this coupling, this study evaluates a mitigation scheme that adds a high-conductivity metallic heat spreader. The results show that the heat spreader changes the global thermal dissipation path and reduces the peak temperature. At the same time, it reveals a top-surface thermal cross-talk mechanism, in which heat conducts downward from the spreader, making the HBM an auxiliary dissipation path for the SoC.
The framework provides physical guidelines for structural layout optimization in the early design stage. It is also efficient enough to generate large amounts of thermal data, which can be used to build the thermal-characteristic databases needed for future data-driven thermal prediction models.

Abstract:
To meet the demands for extreme miniaturization, heat dissipation, and high-frequency signal integrity in 5G/RF modules, advanced packaging has shifted from conventional solder balls to ball-less land grid interfaces. Inside these ultra-thin configurations, electroplated copper (Cu) pillars act as the most critical interconnects. While this structural compression successfully shortens signal paths, it consequently forces these Cu joints to bear unprecedentedly high current loads. To address this, Cu pillars were electroplated under distinct current densities of 1, 3, 5, 7, 10, and 15 ASD (A/dm²) to systematically evaluate the correlation between their microstructure evolution and subsequent mechanical reliability.
Electron backscatter diffraction (EBSD) analysis demonstrates that elevated current densities trigger a direct and significant grain refinement, reducing the average Cu grain size from 3.15 μm (1 ASD) to 1.40 μm (15 ASD). Furthermore, these varying current regimes substantially modify the fractions of high-angle grain boundaries (HAGBs) and twin boundaries (TBs). Conversely, at a low current density of 1 ASD, the electroplated Cu pillars exhibit a severe surface roughness at the top. Literature indicates that the applied current density directly dominates the co-planarity of electroplated Cu pillars. As the current density increase from 3 ASD to 6 ASD, the morphology of the Cu pillars transitions from a flat surface to uneven profiles such as dished- or domed-type shapes. Consequently, identifying an optimal current density is essential to achieving a refined, defect-free microstructure while simultaneously minimizing the overall manufacturing process time. Ultimately, this work delivers a comprehensive evaluation focused on the morphological, crystallographic, and mechanical reliability assessment of electroplated Cu pillars under varying current density constraints.