Sessions Index

Abstract:

1. Advanced Packaging and Substrate Evolution for AI/HPC


2. Glass Core Substrate Architecture and Technology Landscape


3. TGV Formation, Material Evaluation, and Metallization


4. Dual-Side Build-Up, RDL, and Experimental Validation


5. Mechanical Simulation, Warpage, and Reliability


6. Manufacturing Challenges and Ecosystem Collaboration


7. Summary

Abstract:

• why glass core for substrate


• TGV with plug-in pre-formed Cu pillar pins


• characterization of electrical performance, mechanical warpage, and thermal dissipation of the proposed TGV structure


• key process challenges to be identified and solved

Abstract:

In this talk, we share how the Hi-CHIP Alliance, together with our industry partners, embarked on an accelerated effort to explore glass interposer process integration. By coordinating across multiple companies, we combined expertise and resources to investigate some of the most demanding challenges in advanced packaging.
This year's work continues the development of the key process modules initiated last year, focusing on the remaining critical technologies required for TGV glass interposer integration. The presentation will cover the progress and technical achievements in front-side RDL formation, glass carrier bonding, TGV glass thinning, TGV reveal, backside RDL and bump formation, as well as glass carrier de-bonding.
The session will highlight the process integration challenges, key technical observations, and lessons learned throughout the development of these process modules. Particular emphasis will be placed on integration sensitivities, manufacturability considerations, and reliability improvements achieved through process optimization.
Rather than presenting a completed product, this presentation focuses on the continued development of these essential technologies and the collaborative efforts required to advance TGV glass interposer manufacturing toward high-volume production.

Abstract:

Glass core substrates are emerging as a promising platform for next-generation AI and high-performance computing packages. Their excellent dimensional stability, low warpage, smooth surface, and potential for high-density through-glass vias enable larger package sizes, finer interconnects, and improved signal integrity. Recent industry investments and system-level demonstrations have confirmed their technical potential. However, major challenges remain, including brittle material handling, TGV formation and metallization, build-up layer integration, reliability qualification, manufacturing yield, and cost competitiveness. Successful commercialization will require close co-design among glass suppliers, substrate manufacturers, equipment vendors, and semiconductor companies to establish scalable, repeatable, and economically viable production processes.

Abstract:

Artificial intelligence is pushing advanced packaging beyond conventional limits in package size, bandwidth, power delivery, and thermal management. This invited talk discusses the opportunities and challenges of applying panel-level heterogeneous integration to next-generation AI chip packaging, with emphasis on the transition from mature CoWoS platforms toward CoPoS and beyond. The talk first reviews panel-level packaging concepts, including RDL-first and chip-first process flows, and explains why larger substrates, higher area utilization, and cost scalability are increasingly attractive for multi-chip AI modules. Key technical barriers will then be examined, including panel warpage, die shift, fine-line RDL uniformity, laser debonding, electrical compensation, and reliability under operating conditions. Finally, highlighting collaborative industry advancements, this presentation showcases joint co-development breakthroughs in balance-film warpage control, maskless DLT patterning, and DDC-based dynamic re-layout, followed by a forward-looking view of “what is the next of panel” for manufacturable AI systems.