Sessions Index

Bio:
Tan Wei Jern has been part of the semiconductor industry since 2012, working in both the Client and Server product segments. His focus has primarily been as Signal Integrity engineer in both platform design and customer product engineering. He has authored 8 papers and one patent.

Abstract:
This paper presents an electrical study on the sensitivity of channel design components in a DDR5 memory interface. The paper seeks to tackle issues caused by complex design elements in combination with ever-increasing memory signal speeds. The optimization and correct implementation of the proposed methods yield improved channel performance in terms of Eye Height/Vref(mV) and Eye Width/Delay(UI) margins. Of note, they maintain design flexibility, while enabling improved eye margins especially at higher memory data rates. The methods focus on channel design on existing signaling by identifying and mitigating harmful signal degradation caused primarily by signal reflection and signal-to-signal coupling, through correct optimization of signal layer assignment and via length, via-in pad implementation and device connector grounding. A poorly designed system might incur additional costs despite not having to. The ability of a highly correlated simulation methodology to predict a feasible routing solution through pre-silicon simulation on platform topologies with high confidence is therefore critical. It helps design engineers push the boundary on the hardware design solution and make necessary trade-offs in the design solution on PCB material. This enables server hardware design to adapt to scalable and fast design times for cost-effective solutions while keeping system electrical healthiness throughout product development by performing reliable SI trade-off analyses and avoiding potential additional costs of a poorly designed system

 

Bio:
Cheng-Yu Tsai received the M.S. degree in Electrical Engineering from National Kaohsiung First University of Science and Technology (NKFUST), Kaohsiung, Taiwan, in 2010. He joined ASE Kaohsiung in the same year and is currently a senior engineer in the Electrical Laboratory. His research interests include signal integrity (SI) and power integrity (PI) in substrate design.

Abstract:
The rapid development of artificial intelligence (AI) and high-performance computing (HPC) has driven the growing demand for bandwidth and data throughput, making chiplet architectures and advanced packaging technologies rapidly become mainstream in the semiconductor industry. As these demands grow, advanced package designs are required to integrate more RDL layers to accommodate increasingly complex signal and power distribution networks, which will inevitably lead to longer simulation times and increased challenges in design verification. To accelerate early-stage design evaluation, this work utilizes optiSLang to integrate the design and analysis workflow. By applying big data analysis and building predictive electrical models, the proposed method enables fast and accurate signal integrity (SI) checks for Die-to-Die interconnections. This helps layout engineers define design guidelines more efficiently in the early phase, thereby improving design accuracy and reducing iterative loops between simulation and design.

In this work, the Die-to-Die interconnect structure between the ASIC and HBM3 in a multi-layer RDL FOCoS package is used as an example. A parametric model is first constructed by defining input parameters such as line width, line spacing, dielectric thickness, and copper thickness. The eye width is defined as the output response. Next, an automated simulation workflow is implemented using optiSLang to perform a large number of design of experiments (DoEs) simulations. Finally, the collected data is used to train and validate a predictive model for signal integrity evaluation.

The signal integrity predictive model developed in this work has been successfully applied to FOCoS packaging and validated against actual design results, demonstrating an eye width prediction deviation of less than 10%. This predictive model not only provides practical design guidelines but also enables fast and accurate evaluation of Die-to-Die signal integrity in the early design phase, facilitating more reliable high-speed package designs.

 

Bio:
Heng Chuan Shu Product Development Engineer focuses on Power Design

Abstract:
Power Integrity (PI), & Power Delivery (PD), are two major power related electrical designs on printed circuit board (PCB), and package, for integrated circuit (IC). Both are inter-related yet each serves different spectrum of the design. Conventionally, PI and PD are designed separately as the design tools and area of focus are distinctive. PI focuses on PCB and package parasitic, ballmap and real estate planning, cap placement, and generally on higher frequency in megahertz ranges. On the other hand, PD focuses on voltage regulator (VR) design, stability, and efficiency on sub megahertz ranges. However, the actual operation mode is the full path loop which consists of both PI and PD domain.

The full path of PIPD design, consists of three major segments – VR, PCB, and IC. In order to validate the VR and PCB design, a tool to represent the IC component is needed. StarDust Load Emulator (SDLE) is an AMD’s proprietary tool that is used to validate VR and PCB design that are dedicated for AMD’s CPU. It has various controllable load patterns to mimic the behavior of CPU at board level thus it is a very useful tool to evaluate the power design of VR and PCB before the silicon arrives.

While the SDLE tool is valuable for power design validation in lab, a full path PIPD co-simulation (cosim) methodology is essential for design verification before the PCB is gerbered out. This helps to reduce the design cycle and cost by determining design flaws before they are found during the lab test. While a SDLE full circuit level model will provide the most accurate simulation output, it has two major problems. First, the circuit level model is not readily available in VR or PCB design environment. Second, the time required to run the full circuit level simulation is very long. As such, a behavioral model is proposed.

Behavioral SDLE model, PCB model, and VR model will then be converted into a common simulation environment, which is a popular commercial tool to run VR simulation – SIMPLIS. The results are then validated with actual lab measurement. The simulation and lab measurement data are highly correlated with less than 1% discrepancy.

 

Bio:
Tina Yang is currently a Platform Application Engineer in Data Center Group at Intel, responsible for high-speed interfaces design for server and workstation products. She received the M.S. in National Taiwan University of Science and Technology in 2012. She worked for Jabil from 2017 to 2019 and for Himax from 2019 to 2021. And she joined Intel Corporation as a signal integrity engineer for SI customer enablement and support and technology development from 2021.

Abstract:
As high-speed input/output (I/O) interfaces continue to evolve, The printed-circuit board (PCB) design has become increasingly challenging and complex—particularly in server and AI system applications. Designers must now address the issues for signal integrity of complex board design, to ensure reliable high-speed performance. From the currently prevalent PCIe 5.0 standard operating at 32 GT/s, to the forthcoming PCIe 6.0 and the future PCIe 7.0—targeting data rates of 64 GT/s and 128 GT/s respectively—each generation presents significant advancements in bandwidth and corresponding challenges in high-speed PCB design. From the perspective of PCB designers, performing accurate signal integrity (SI) simulations is essential at early stage for anticipating real-world behavior and mitigating potential risks prior to product fabrication.
A complete system design demands that designers perform thorough evaluations across multiple stages of development to ensure signal integrity and overall performance. In the early design phase, pre-layout simulations are conducted to assess the system architecture based on anticipated signal transmission quality. These simulations provide critical insights that guide the initial design direction. As the design progresses into the second phase, the results from early evaluations inform decisions regarding PCB topology and signal routing strategies. At this stage, design choices such as trace spacing, via placement, and routing angles can significantly impact signal behavior, making it essential to carefully consider their effects on signal integrity. Finally, in the post-layout phase, designers utilize the actual PCB layout to perform detailed signal integrity simulations. These post-layout analyses are crucial for validating the real-world performance of the design, identifying potential issues introduced during routing, and ensuring that the final product meets stringent electrical and reliability requirements. This structured, simulation-driven approach is fundamental to reducing design risks and achieving robust, high-speed system performance.
This paper examines the differences between various simulation algorithms applied to the same PCB layout design, aiming to understand the strengths and limitations of each methodology. In practical product development, designers must often strike a balance between simulation accuracy and computational efficiency, selecting appropriate algorithms for board-level signal integrity evaluation. Two-dimension (2D) and Pseudo Three-dimension which also called 2.5D simulation algorithms are commonly used due to their ability to significantly reduce analysis time. However, these methods often suffer from limited accuracy, particularly in modeling vertical structures such as vias. For instance, due to insufficient resolution along the z-axis, via modeling in 2D/2.5D simulations can lead to deviations from actual performance, potentially introducing design risks. In contrast, full Three-dimension (3D) electromagnetic (EM) simulation algorithms offer much higher accuracy by capturing the complete spatial behavior of signals, including complex via transitions and coupling effects. Nevertheless, this improved precision comes at the cost of significantly longer simulation times. For complex server motherboard structures, 3D simulations may require several days to even weeks to complete, which can impact product timelines and delay design cycles. The study explores the pros and cons of different methodologies for post-layout simulation, as depicted in Table 1.

 

Bio:
Tan Wei Jern has been part of the semiconductor industry since 2012, working in both the Client and Server product segments. His focus has primarily been as Signal Integrity engineer in both platform design and customer product engineering. He has authored 8 papers and one patent.

Abstract:
This paper presents an efficient DDR5 memory channel electrical modeling and board solution analysis methodology without compromising accuracy on scalable server platforms. The work proposes a hybrid modeling methodology that covers accurate DDR5 channel electrical across high volume manufacturing (HVM) and the risk evaluation coverage on scalable systems based on a golden reference system channel profiler using typical corner models to monitor HVM solution risks. The use of both 3D and 2.5D model extraction methodologies enables a balance coverage between improved extraction accuracy for complex vertical channel structures using the 3D methodology and processing time efficiency for straightforward transmission line segments using the 2.5D methodology. Segments such as System-on-Chip (SOC) Ball-Grid Array (BGA) via region and the memory device connector that feature increased vertical crosstalk benefit from the accuracy of 3D model extraction, while segments such as the memory channel’s main route transmission line that do not exhibit this benefit from time efficiency of a 2.5D extraction method. This shows an overall accuracy improvement compared to a purely 2.5D extraction method and time-saving benefit compared to a purely 3D extraction method. The ability of a highly accurate simulation methodology to predict a feasible routing solution through pre-silicon simulation on platform topologies with high confidence is critical. This enables server hardware design to adapt to scalable and fast design times for cost-effective solutions while keeping system electrical healthiness throughout product development by performing reliable SI trade-off analyses and avoiding potential additional costs of a poorly designed system.

 

Bio:
- Sr. Manager of Signal Integrity Engineering at Wiwynn Corporation - Principle Field Application and Module Design Engineer at Astera Labs - Sr. Engineer of Signal/Power Integrity Engineering at Hewlett Packard Enterprise - A. Director of Signal/Power Integrity Engineering at Wistron Corporation

Abstract:
As the high-speed signal transmission lines routing density continues to increase in AI server systems, signal integrity has become a critical factor in PCB design. Additionally, with the PCIe Gen6 and Ultra Ethernet interfaces coming to be standard links in AI servers design, even minor variations in routing can significantly impact link performance. In these high-density designs, the high-speed routings are exactly combinations of many different routing patterns by segments. However, the normal PCB impedance verification and transmission loss evaluation in the manufacturing process are from one or two routing patterns on PCB test coupons only. That would trigger a thought-provoking question here: can the impedance and loss validation results from the one or two routing patterns’ coupons represent the characteristics on actual in-board routings? To answer this question, we’ve designed experiments with many different patterns’ coupons as DUTs to quantify the characteristics of different routing patterns in this paper. Eventually, we’ve characterized the behaviors of different routing patterns with some findings as routing patterns can impact impedance uniformity and signal loss, especially above 10 GHz.

 

Bio:
Kin Fei is a Principal Engineer at Tenasic Technology with 17 years of experience in electrical engineering. He received his B.Eng. and M.Sc. degrees in Electronic System Design Engineering from Universiti Sains Malaysia. His work focuses on signal and power integrity for advanced SoC platforms, including applications in autonomous vehicles, IoT, servers, and clients. He has extensive experience in X86, RISC-V, and FPGA-based package and board design, and currently leads cross-functional development in SIPI analysis and platform integration for next-generation systems.

Abstract:
Early-stage silicon power grid and Power Delivery Network (PDN) decoupling planning relies on Chip Power Model (CPM) and instances current profile, where the scenario selection of these profiles directly impacts MIM (Metal-Insulator-Metal) capacitor allocation and silicon floor planning. The challenge lies in selecting appropriate switching scenario, vectorless or vectored. Misestimating current demand leads to either overdesigned PDNs or silicon with insufficient IR drop margin.
Conventional methods rely on vectorless current profiles with toggle rate assumptions. This approach often lacks correlation with actual workload switching activity. In contrast, vectored simulations with gate netlist driven by real activity offer higher accuracy but are time consuming. The industry currently lacks a systematic method to select representative simulation windows for vectored analysis or to calibrate vectorless toggle rates in early assessments. As a result, the early PDN and MIM planning decisions made using these methods might risk misestimation.
To address this, we introduce a segmentation and concatenation technique that constructs an equivalent composite full cycle vectored current profile. It achieves up to 7x reduction in simulation time while maintaining comparable accuracy to full window vectored simulations. Based on this golden reference, we evaluate multiple current profiling used in IR drop analysis tool.
Our study includes vectorless profile using different toggle rates, and vectored profiles based on real switching activities. Each activity is evaluated for its impact on peak-to-peak voltage noise, minimum voltage, and overall Dynamic Voltage Drop (DVD) margin. While results converge, selective scenarios can still yield optimistic or pessimistic outcomes depending on context.
In our case study of a DDR5 controller, we observed that early vectorless estimates led to under allocation of MIM capacitance by up to 50%. We also found that DVD was highly sensitive to toggle rate assumptions, underscoring the limitations of uncalibrated vectorless methods. Conversely, vectored simulations yield more realistic DVD, bump level peak to peak voltage noise, and minimum voltage (Vmin), resulting in optimal MIM allocation. Our contributions include:
Segmented concatenation framework that stitches short duration vectored windows into a concatenated full workload current profile, achieving up to 7x runtime reduction.
Scenario coverage methodology that scores candidate vectored cycles based on toggling activity, power profiles, and electrical impact, enabling a judicious subset selection for high fidelity DVD correlation. Ditch the need for full vectored cycles simulation.
Toggle rate sensitivity study, evaluating vectorless parameters to help automate gross model generation for early signoff confidence.
This work offers practical guidance for Power Integrity (PI) and advanced package engineers to perform accurate MIM and decoupling cap planning, enabling SoC projects to converge faster while maintaining robust voltage stability.
This paper is organized into the following sections:
Section I: Full window vectored current profile segmentation and concatenation technique and the wall time reduction.
Section II: Vectorless and vectored current profiling methodology.
Section III: Simulation results with vectorless and vectored current profiles with different switching activities scenarios. It is shown that vectorless DVD was highly sensitive to toggle-rate.
Section IV: The current profiling impacts on on-chip decoupling cap and package decoupling cap strategy.

 

Bio:
Chew has 14+ years working experiences in platform electrical design and solution specializing in signal and power integrity pre-silicon analysis methodology enabling, package and system level HSIO design enablement and solution. She has proven technical and analytical skills with >50 international technical contribution to-date and she is also actively serve as member of technical program committee for various international journals and IEEE technical conferences. Chew graduated from The University of Nottingham, holding a PhD and MSc degree in Engineering where her research areas cover visual information processing such signal transformation and compression, object recognition and detection and motion estimation.

Abstract:
This paper provides an overview of GPU product Universal Baseboard (UBB) integration into data center system design including the introduction of common DC GPU system topology, channel electrical performance as well as methodology for signal performance evaluation and I/O performance tuning.

GPU loss, PCIe link drop and link instability often occur during system integration due to non-optimize PCIe preset selection which required a customize analysis of retimer tuning on each customer platform. Due to the uniqueness of the electrical performance such as system loss budget and impedance discontinuity of the channel in each customer platform, a comprehensive signal integrity (SI) simulation methodology which includes the consideration of worst corner cases and high-volume manufacturing (HVM) variation is introduced. Besides, a post-silicon retimer tuning process is also discussed to improve PCIe link performance during UBB system integration at customer data center.

A comprehensive data collection and analysis performed on actual customer platform shown that there is high correlation of SI simulation and post validation findings. The work presented here helps not only to enable end consumers for a smoother and quick time-to-market adoption of AI GPU products, it could also help to improve the working model efficiency and enlighten customer supports services.