Sessions Index

Bio:

Takashi Matsumoto ined DENSO in 2017 and was in charge of the Automotive Analog ASIC division. In 2025,transferred to the Technology Planning division and was in charge of SoC chiplet technology development.

Abstract:

Chiplets are expected to see widespread adoption in future automotive applications. However, they must be able to endure the tough operating conditions inside vehicles and meet strict mechanical and electrical requirements. In this presentation, we will propose design approaches to address these challenges.

 

Bio:
Ms. Bandharla Dharani is a Process Engineer at ASE, Taiwan, specializing in the panel backside grinding process. She focuses on ensuring panel thickness and Total Thickness Variation (TTV) remain within quality limits while preventing cracks and chips during the grinding process. Her expertise includes process control, troubleshooting, and improving throughput in grinding applications.

Abstract:
The demand of AI technology and High-Performance Computing (HPC) chips gradually increasing all around the world. For high performance and high integration, the requirement of thinner panel is necessary, here where the demand of the BS grinding process increased. The BS Grinding is the process is used to grind and polish the back side of the panel to reduce its thickness and fine surface chips which helps for high performance and integration. Achieving thin panel comes with more difficulties like to maintain Total Thickness Variation (TTV), no crack and Thickness of the panel. In this process Controlling TTV play a vital role due to its importance in Die stack, high yield and heat sink. A fine and uniform surface(thickness) is essential for detailed Integrated Circuit (IC) design and Inconsistent thickness can lead to defects in the circuit layout and also effect the next process like Bask side metallization or during Die stack process. This article introduces the Panel level BS Grinding process how precise for thinning the panel in order; to improve the mechanical and computing strength by overcoming the challenges like TTV, Thickness, Crack and Fine surface. The more even flat provides this leads to higher yields and improved performance in high-performance computing (HPC) and artificial intelligence (AI) applications.

Keywords— BS Grinding panel process, TTV, Fan-out, Fine Surface

 

Bio:
Professor Sheng-Jye Hwang received the Ph.D. degree in mechanical engineering from the University of Illinois at Urbana–Champaign, Champaign, IL, USA, in 1992. He has been a Faculty Member with National Cheng Kung University, Tainan, Taiwan, since 1992, where he is currently a professor. He has more than 96 SCI journal articles published in the areas of polymer processing, electronic packaging, 3D printing and computer-aided engineering. He is actively involved in industry-academic cooperating researches and has several technology transfers to the industry.

Abstract:
With the rapid development of artificial intelligence (AI), high-performance computing (HPC), and 5G communication technologies, traditional IC packaging techniques are increasingly inadequate to meet the demands for high transmission speeds and high-density integration. To address these challenges, the semiconductor industry has been actively developing advanced packaging technologies, including Fan-Out Packaging (FOP), 2.5D/3D integration, and Heterogeneous Integration. To achieve the high-density interconnect structures required by these technologies, the Redistribution Layer (RDL) process has become a critical and essential technology. However, polyimide (PI), the dielectric material commonly used in the RDL process, undergoes volume shrinkage during high-temperature curing, which may lead to uneven topography in the RDL structure. This deformation accumulates progressively through multi-layer stacking processes, adversely affecting the alignment accuracy during chip bonding, and potentially leading to signal short circuits or delays. To address these issues, this study establishes a simulation procedure for multi-layer RDL structures to predict the PI dish depth and topography of each layer. The simulation results are compared with experimental measurements to verify the feasibility and accuracy of the proposed approach.

This study focuses on multi-layer circuit structures in the RDL process by establishing two types of multi-layer models to investigate variations in PI dish and topography after the post-curing stage. The first model explores various line/space (L/S) dimensions, including 5/5 µm, 2/2 µm, 8/8 µm, and 10/10 µm. The second model is constructed based on actual measured topography data. Due to the lack of material properties for uncured PI, a single-layer circuit model was initially developed and simulated using assumed parameters. The results showed a noticeable discrepancy between the simulated and measured topography. Consequently, the material properties were further adjusted to enhance the simulation accuracy, and the refined parameters were applied to the multi-layer circuit models.

To simulate the multi-layer models, this study employed the Output Link, Element Birth and Death, and Morphing tools in Moldex3D to predict PI dish and topography variations in multi-layer RDL structures. The simulation results for models with different L/S dimensions revealed that both the L/S size and the PI thickness above the copper lines significantly influence PI dish and topography, with these effects becoming more pronounced as the number of RDL layers increases. Specifically, for the L/S dimensions of the 5/5 µm model, the deviation between simulated and measured PI dish was approximately 20–30%. Furthermore, the model constructed from actual topography data exhibited high consistency with the measurement results.

In conclusion, the simulation approach developed in this study effectively predicts the variations in PI dish and topography within multi-layer RDL structures, demonstrating its practical applicability. Nevertheless, the accuracy of PI dish prediction still requires further optimization and improvement.

 

Bio:
Nils Anspach is Director of Product Management at LPKF Laser & Electronics, overseeing the company’s Semiconductor and SMT product portfolio. He drives product strategy and market development for innovative solutions, including LPKF’s proprietary LIDE (Laser Induced Deep Etching) technology for glass substrates. With a focus on aligning technology and market needs, he plays a key role in shaping the future of advanced electronics manufacturing.

Abstract:
The proliferation of Artificial Intelligence, from large-scale cloud data centers to power-sensitive edge devices, has created an urgent demand for packaging solutions that deliver unprecedented performance with greater energy efficiency. As chiplet-based designs and heterogeneous integration become standard, the interconnect fabric is now a critical bottleneck, challenging the performance gains of advanced silicon. Traditional organic substrates are reaching their limits in terms of interconnect density, dimensional stability, and thermal performance, which directly impacts the power consumption and signal integrity of AI accelerators.

This paper presents Laser Induced Deep Etching (LIDE) as a pivotal enabling technology for the next generation of advanced packaging. LIDE overcomes the historical challenges of glass micromachining, allowing for the cost-effective, high-volume production of glass interposers with features previously unattainable. This unique two-step process facilitates the rapid, precise, and damage-free structuring of glass, creating micro-crack-free Through-Glass Vias (TGVs) with exceptional aspect ratios (>50:1) and vertical sidewalls.

We will demonstrate how LIDE directly addresses key trends in high-performance computing packaging. Specifically, we will detail its application in creating high-density interconnects and fabricating precise, deep cavities for the seamless embedding of silicon bridges. This architecture dramatically shortens the signal path between logic and memory chiplets, significantly reducing transmission losses and parasitic effects, which is crucial for lowering the power envelope of complex AI systems.

By leveraging the superior electrical properties and thermal stability of glass, LIDE-processed interposers provide a robust platform for 2.5D and 3D integration. The resulting packages exhibit enhanced signal integrity, improved thermal management, and superior reliability. In conclusion, LIDE is not merely an innovative process but a foundational technology that empowers package designers to build the compact, high-bandwidth, and energy-efficient hardware required to power a smarter, more sustainable world—from the cloud to the edge.

 

Bio:
John Chang is an Applications Development Manager in the Lithography Group at Onto Innovation. He holds a Master’s degree in Nanoelectronics and Photonics from National Chung Hsing University and has over 20 years of experience in semiconductor advanced packaging. Throughout his career, he has authored over 20 publications and holds numerous U.S. and Taiwan patents in metrology, lithography, advanced packaging, and AICS.

Abstract:
Advanced packaging technologies, such as ultra high density fan out packaging and 2.5D/3D integration, are essential for the continued advancement of chiplet-based AI applications. Achieving the stringent manufacturing requirements for AICS: specifically larger packaging areas, reduced line and space dimensions, finer ball pitches, and increased layer counts; necessitates the implementation of sophisticated lithography processes characterized by extremely large exposure fields coupled with fine resolution capabilities.

Despite these lithographic advancements, significant challenges persist, particularly concerning overlay accuracy. Overlay errors frequently result from alignment solution inaccuracies and can severely limit the achievable overlay yield, posing substantial impediments to scaling advanced packaging technologies. Addressing alignment solution errors effectively is critical for meeting the increasingly strict overlay budgets anticipated for next generation AI driven applications.

This study rigorously investigates process-induced alignment solution errors within large-panel lithography processes. By systematically analyzing overlay measurement data from a 510mm × 515mm panel substrate, we quantify and characterize alignment solution errors and their direct impact on overlay precision. Further, we propose an innovative early zone correction technique aimed at compensating alignment inaccuracies during the lithographic exposure phase. The early zone correction approach leverages algorithmic analysis to identify correctable zone-based overlay error components, subsequently applying these corrections proactively during lithographic exposure. The efficacy of this approach was validated experimentally using substrates exhibiting known alignment errors. The experimental outcomes indicate substantial improvements in overlay precision and yield, underscoring the robustness of early zone correction in addressing alignment inaccuracies. These findings demonstrate that the combination of extremely large exposure field lithography, fine resolution capability, and early zone correction significantly mitigates the overlay challenges inherent to advanced packaging manufacturing.

 

Bio:
Ting-Chi Chen is a Master’s student at National Yang Ming Chiao Tung University, specializing in Cu-Cu bonding technology for advanced semiconductor packaging. His research focuses on microstructural analysis and interface engineering to improve bonding quality and reliability. He is actively involved in exploring low-temperature bonding processes and their applications in 3D integration.

Abstract:
Direct copper-to-copper (Cu-Cu) bonding has emerged as a promising approach for advanced electronic packaging applications. Nanocrystalline copper (NC-Cu), with grain sizes below 100 nm, has recently garnered increasing attention because its high internal energy and enhanced grain boundary diffusion facilitate significant grain growth during high-temperature processes, which can promote grain growth across the bonding interface and improve interfacial bonding quality. Therefore, the extent of grain growth plays a critical role on NC-Cu in Cu-Cu bonding as increased grain growth provides more driving force for eliminating the bonding interface thereby enhancing the bonding strength. Our study revealed that applied pressure influenced grain growth behavior in NC-Cu in the bonding process. Accordingly, we investigated the correlation between applied pressure and grain size after annealing in NC-Cu, and examined how these factors impacted the overall bonding quality. In this study, a 2.5 µm-thick copper film was deposited on a titanium (Ti) adhesion layer using direct current (DC) electroplating in a copper sulfate solution with specific additives to produce NC-Cu. Chemical mechanical polishing (CMP) was then applied to planarize the surface. The microstructural changes were compared between the samples annealed under a compressive pressure of 10, 20 and 30 MPa at 200 °C for 1 hour, and then the film bonding was done under the same thermal conditions to evaluate its bonding quality.
The plan-view electron backscattered diffraction (EBSD) analysis was used to confirm microstructure of Cu film before and after annealing. The as-deposited NC-Cu exhibited an average grain size of 113 nm. The grain size was slightly greater than 100 nm because smaller grains in the dark regions could not be resolved due to resolution restriction. After annealing at 200 °C for 1 hour under 10 MPa, the grain size increased to 2077 nm, while a smaller increase to 746 nm was observed under 30 MPa, indicating suppressed grain growth under higher pressure. Electrical conductivity of Cu film was evaluated by measuring sheet resistance using a four-point probe, with film thickness confirmed via focused ion beam (FIB) analysis to assess the effect of pressure during annealing on film electrical properties. Cross-sectional analysis of bonded samples using FIB was conducted to evaluate the influence of bonding pressure on the microstructure and bonding quality of the interface. FIB analysis indicated that the seamless interfaces with few number of voids were obtained under all bonding conditions. These indicate that although significant grain growth serves as a primary driving force for Cu-Cu bonding in NC-Cu, the extent of grain growth suppressed under higher pressure in this study is not the only critical factor to influence bonding quality.

 

Bio:
My name is Ya-Hui, Hsu. I am a PhD student in National Central University. I major in chemical and materials engineering. My adviser is Prof. Cheng-Yi Liu. The present work studied the structure of the Ni(P) layer to predict the phase of the intermetallic compound at the interfacial reaction between SnAgCu(Ni) solder and electroless nickel electroless palladium immersion gold (ENEPIG) surface finish. Hopefully, the present work can contribute to advanced packaging technologies.

Abstract:
The present work studied the structure of the Ni(P) layer to predict the phase of the intermetallic compound at the interfacial reaction between SnAgCu(Ni) solder and electroless nickel electroless palladium immersion gold (ENEPIG) surface finish. Through the TEM analysis, we observed that nano–crystalline/amorphous and polycrystalline microstructures of the Ni(P) layer dominate the Ni dissolution rate into the molten SnAgCu(Ni) solder. Interestingly, the Ni(P) layer with nano–crystalline/amorphous microstructure dissolves less into the molten SnAgCu(Ni) solder than the Ni(P) layer with a higher crystallinity.

We believe that the P content expelled from the Ni(P) layers resides on the Ni(P) layer and retards the dissolution rate of the Ni(P) layer. In the opinion, we experimented the dual Ni(P) layer with low phosphorus content, and then covered it with high phosphorus content on the top layer. Compared with the single low–phosphorus Ni(P) layer, we found that the Ni(P) layer with high–phosphorus content does restrain the formation of intermetallic compounds during the reflow process. This phenomenon means that the interface mechanical property could be enhanced by the dual Ni(P) structure.

Moreover, the phase and morphology of the interfacial compound phase are greatly affected by the Ni content in the solder. A larger Ni content in the interfacial compound converts the prismatic-like (Cu,Ni)6Sn5 compound phase to the needle-like (Ni,Cu)3Sn4. At this point, the phases and morphology of the interfacial compound not only depend on the in situ Cu and Ni content in the molten solder, but also the reflow profile. In the experiment, the consumption of Ni(P) was calculated against different reflow times at 250℃, 265℃, and 280℃. The phases corresponding to the present determined Cu, Ni, and Sn composition in the reported Cu–Sn–Ni ternary phase diagram at 250℃ do not match the interfacial (Cu,Ni)6Sn5 compound formed in the 250℃ case. At 250℃, ripening occurred on the interfacial (Cu,Ni)6Sn5 compound grains and eventually caused them to spall from the interface. For 265℃ case, the faster ripening caused earlier formation of the valley and small spacing between the (Cu,Ni)6Sn5 compound grains after 10-s reflowing. After 20-s reflowing, the needle-shaped (Ni,Cu)3Sn4 compound phase begins to form at the valley sites of the interfacial (Cu,Ni)6Sn5 compound layer, which hinders the spalling of the (Cu,Ni)6Sn5 compound grains. For 280℃ case, we believe that the ripening of the (Cu,Ni)6Sn5 compound grains has quickly occurred within seconds. Hence, the needle-shaped (Ni,Cu)3Sn4 compound largely formed between (Cu,Ni)6Sn5 compound grains in 10-second reflowing. After a prolonged 40-s reflowing, the (Cu,Ni)6Sn5 compound grains have completely spalled off from the interface, and the needle-shaped (Ni,Cu)3Sn4 compound covered and dominated the entire reaction interface.

In this case, it is well known that the reflow profile of soldering process is not the only factor to influence the formation of intermetallic compounds at the interface. We found that the design structure of the Ni(P) layer can also control the interfacial reaction. With the ideal, we expect to develop a predictable model in SnAgCu(Ni) solder/Ni(P) layer system to enhance the interfacial mechanical property.