Design and Material selection for Large Adv Package Development
發表編號：S29-1時間：13:00 - 13:30 |
Invited Speaker
Speaker: Andrew Kang, Director, SPIL
Bio:
Andrew has worked around 21 years in Semiconductor industry and published over 40 conference papers /patents. Now he is a director at SPIL’s Corporate R&D. Briefly listed the experience below: 2006~2017: R&D experience in Substrate makers. 2017~2022: Responsible for Substrate ENG department to handle the substrate roadmap, new technology, new material, new factory verification, yield improvement, and NPI substrate qualification in SPIL. 2022~Now: In charge of Substrate ENG, Substrate Design, Material Lab. and Package Simulation including warpage/ stress/ thermal/ electrical.
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Heterogeneous Integration Package in High Performance Computing (HPC)
發表編號：S29-2時間：13:30 - 14:00 |
Invited Speaker
Speaker: Ming-shih Yeh, Deputy Director, MediaTek
Bio:
Dr. Ming-Shih Yeh is currently a Director of Package Technology Division 1 at MediaTek, where he leads Automotive, Edge AI and advanced heterogeneous integration package development. With over 27 years of experience in IC industry, Dr. Yeh has been instrumental in the development of InFO, CoWoS, advanced package materials and in-line metrology, SiP module and Cu/low-K interconnect at MediaTek, tsmc, ASE group and UMC. Ming-Shih received his Ph.D. degree in Department of Nuclear Engineering from National Tsing Hua University in 1997.
Abstract:
1. Market Drivers: why Heterogeneous Integration
2. Key Package Architectures for HPC
3. Product Technology Trends
4. Critical Challenges and Opportunities
5. Ecosystem for Tomorrow’s Heterogeneous Packaging
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The Package is the System: Substrate Evolution and CoPoS Platforms for Energy-Efficient AI
發表編號：S29-3時間：14:00 - 14:30 |
Invited Speaker
Speaker: Wilson Chang, Technical Service Manager, ZDT – LIST
Bio:
Education: Master in Nanoelectronics and Nanotechnology, University of Southampton, UK
Working Experience: 16 years’ experience in IC substrate
ZDT-LIST 2022~present
Kinsus Corp. 2010~2022
Abstract:
Introduction:
- Blurring Boundaries—The Package is the System
- The Mechanical & Electrical Limits of Conventional Organic Substrates
- The Glass Core Substrate (GCS) Revolution
- Geometry Transformation: TSMC's CoPoS
- Advanced Packaging Platform and System-Level Applications: Co-Packaged Optics & Cooling
- ZDT’s Smart Fab: AI-Driven IC Substrate Quality Management and Applications
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Silicon Photonics and Co-Packaged Optics for AI Optical Interconnects
發表編號：S29-4時間：14:30 - 15:00 |
Invited Speaker
Speaker: Pei-Ting Chou, Division Director, Electronic and Optoelectronic System Research Laboratories, Industrial Technology Research Institute
Bio:
Dr. Pei-Ting Chou has served as Division Chief of the Electronics and Optoelectronics System Research Laboratories at ITRI since 2025. He began his professional career in 2006, with experience spanning both ITRI and the industry, particularly in LED and MicroLED technologies, and later expanding into silicon photonics (SiPh) and advanced optical testing platforms. Dr. Chou leads multidisciplinary R&D teams and has received several international awards, including the R&D 100 Award and the Frost & Sullivan Best Practice Award, recognizing excellence in technological innovation and industrial impact.
Abstract:
This presentation will discuss the evolution of AI optical interconnects, focusing on silicon photonics and co-packaged optics. Key challenges in heterogeneous integration, advanced packaging, thermal management, and testing will be highlighted, along with ITRI’s perspectives on technology development and industry collaboration.
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