Sessions Index

Bio:

Herbert Oetzlinger , graduated HTL Braunau 1987 in high power electronics/ electrotechnics, Herbert worked in the Semiconductor industry for 30+ years, focused on wet processing.
Special focus on advanced packaging in electroplating and wet etching/cleaning of wafers and substrates. For many years he was VP of Sales with Semitool Inc, where he excelled with his in-depth knowledge of process and hardware. During this time, Herbert worked with many worldwide leading companies on Fan-out, E-WLB and other new developments in wafer level advanced packaging.
In 2012, he founded Semsysco GmbH and is also heading the company as CEO. LAM - Semsysco is a world leader in high speed electrochemical deposition with a pedigree and expertise in all-around wet processing for wafer and panel level.

Abstract:

In contemporary electronic packaging, the pursuit of miniaturization, enhanced performance, and reliability remains a fundamental driving force. This abstract introduces a novel approach in advanced packaging through the utilization of Through Glass Vias (TGVs) for Glass Core Integration, as a viable alternative to Conventional Silicon (Si) Interposer technology. The presentation encapsulates the background, motivations, technical aspects, and results of our evaluation work in this innovative packaging paradigm.
The background of this research is grounded in the growing demand for smaller form factors, increased functionality, and improved thermal management in electronic devices. Traditional Si interposer technology, while effective, presents limitations in terms of scalability, thermal conductivity, and electrical performance. Thus, the exploration of alternative materials and methodologies is imperative for the next generation of packaging solutions.
Motivated by the exceptional properties of glass, including its thermal stability, electrical insulation, and compatibility with existing manufacturing processes, this study delves into the feasibility of utilizing glass as both a carrier and core material in advanced packaging. Through Glass Vias (TGVs) emerge as a key enabler, facilitating vertical interconnects within the glass substrate.
Key considerations such as through-hole requirements, aspect ratios, seed layer deposition, and adhesion to glass are meticulously addressed to ensure the integrity and reliability of the packaging structure. Innovative process technologies are developed to fabricate TGVs with precise dimensions, high aspect ratios, and robust electrical properties.
The hardware requirements for implementing TGV-based packaging are evaluated, encompassing equipment for laser drilling, seed layer deposition, plating, and planarization processes. Cost considerations are also examined to ascertain the economic viability of this approach compared to conventional methodologies.
Results from our evaluation work demonstrate promising advancements in TGV-based packaging, including enhanced electrical performance, superior thermal dissipation, and significant miniaturization potential. Through detailed analysis and experimentation, this presentation illuminates the transformative capabilities of Through Glass Vias for Glass Core Integration, heralding a new era in advanced packaging technology

 

Bio:

Steven Tam is a seasoned professional with over 25 years of experience in the PCB and IC substrate industry, with extensive expertise in specialty chemical processes including surface treatment, metallization, and electrolytic plating. He currently serves as Product Director, IC Substrate line of business at ESI, where he leads regional strategy, product commercialization, and technology transfer across advanced ICS products platforms. Steven has held various key roles in technical marketing, product and technology management, and R&D coordination throughout his career at ESI, technology institute and various specialty chemical suppliers. He has successfully launched numerous innovative solutions for PCB and IC substrate market such as direct metallization, via fill, pulse plating, etc. A graduate in Chemical Engineering from HKUST with an MBA from the University of Hull, Steven combines strong technical insight with strategic leadership to drive growth and innovation in the electronic interconnect industry.

Abstract:

The industry transition from wafer-level packaging (WLP) to fan-out panel-level packaging (PLP) presents significant opportunities in scaling integration, cost reduction, and advanced package formats. However, this shift introduces critical plating challenges for line-and-space scaling, interconnect reliability, and uniform copper deposition across increasingly larger panels. MacDermid Alpha offers advanced solutions for overcoming challenges with innovations in plating chemistries. Synergetic relationships between materials, tools, and methodologies are essential to enable high-yield, high-performance PLP solutions that will support next-generation AI and high-performance computing applications.

 

Bio:

Ryo Tanaka, In 2014, I received my Ph.D. (Doctor of Engineering) from the University of Tokushima. The same year, I joined Okuno chemical Industries Co., Ltd. I am currently researching and developing additives for acid copper plating on semiconductor package substrates and interposer boards.

Abstract:

Advances in packaging technologies, such as chiplets, are leading to larger package substrates. As a result, production efficiency is declining. To compensate for this, panel-level packaging (PLP) technology is attracting attention.
In plating technology, dual damascene technology is essential for shortening process times. Furthermore, the development of dual damascene methods requires improved dimensional stability. To achieve this, films with minimal change in warpage due to heat are required.
We reviewed the design structure of nitrogen-based organic compounds and developed an additive that minimizes stress changes due to thermal history and can be filled with a thin film.

 

Bio:

Dr. Chin-Hock Toh is an Advanced Packaging Technologist at Lam Research, where he leads customer engagements, business strategy alignment, and the translation of technology roadmaps into advanced packaging solutions. He recently joined Lam after 10 years at Apple, where he drove packaging innovations for the iPhone, Apple Watch, and AirPods. With over 22 years of experience, including leadership roles at Applied Materials, Intel, and UTAC, he has pioneered advancements in WLP, fan-out, 2.5D IC, and 3D IC. Holder of 19 US patents, Dr. Toh is a long-time organizing committee member of SEMI SEA and IEEE EPTC, and earned his Ph.D. from UNSW, Australia.

Abstract:

Artificial Intelligence is driving a paradigm shift in semiconductor design, demanding ever-higher performance, bandwidth, and energy efficiency. Advanced Substrate, Interposer and Chiplet-based architectures have emerged as key enabler for meeting these demands, offering modularity, scalability, and accelerated development cycles. However, integrating these AI chips and memory into high-performance systems, especially for AI workloads introduces significant challenges in packaging and process integration.

This presentation explores the role of heterogeneous integration in AI-centric semiconductor design and the advanced equipment technologies required to support it. We will discuss key packaging schemes such as die-to-wafer hybrid bonding and interposer, which are essential for achieving the interconnect density and thermal performance needed in AI accelerators. Special attention will be given to Lam Research’s innovative equipment solutions that enable crack free interdie gapfill, finer interconnect and scalable manufacturing, critical for realizing the next generation of AI-enabled devices. Attendees will gain insights into how equipment innovation is accelerating heterogeneous integration and unlocking new possibilities in AI hardware design.