Sessions Index

Bio:

Dr. Li-Cheng Shen is currently the AVP of Miniaturization Competence Center of USI, focusing on developing and researching cutting-edge technologies of miniaturization. With more than 20 years of experience in the semiconductor industry, Dr. Shen owned more than 30 patents in the fields of Fault Diagnosis System, 3D Package, Wafer Level Package, Opto-electronic Package, Electro-optical Circuit Board, Embedded Component Substrates, RF Module Testing and RF SiP/System Assembly. He is also the technical committee member of ED&A (Electrical Design and Analysis) of ECTC.
In 1998, Dr. Shen received a PH.D. degree in Electrical and Control Engineering from Nation Chiao-Tung University, Taiwan.

Abstract:

• Energy Eagerness in AI/ML Applications


• Why modulelization and miniaturization


• Roadmap of power solutions for AI/ML
  

 

Bio:
Chaur-Hwan (John) Lin is a veteran hardware engineering leader with over 30 years of experience in high-speed digital design, specializing in PCB technology and system-level signal and power integrity. As Director at Lenovo Corporation Taiwan, he leads initiatives in server platform development, advanced interconnect design, and ultra-low-loss PCB material innovation. John has contributed to cross-industry research efforts, including iNEMI, and holds multiple patents related to PCB design and measurement techniques. He earned his Master’s and Bachelor’s degrees in Electrical and Computer Engineering from the University of Wyoming and remains deeply engaged in next-generation PCB advancements.

Abstract:
The warpage of printed circuit boards (PCBs) significantly impacts high-speed signal integrity (SI) due to mismatches in the coefficient of thermal expansion (CTE) among substrate materials, as well as environmental factors such as temperature and humidity variations, and thermo-mechanical stresses during manufacturing and assembly. Warpage distorts signal traces, vias, and critical regions such as ball grid array (BGA) fanouts and connector pads, potentially leading to impedance discontinuities, increased crosstalk, and signal degradation.

This study presents a systematic analysis of how PCB warpage impacts high-frequency signal transmission by constructing three-dimensional (3D) models of chip BGA fanout regions and Mini Cool Edge IO (MCIO) connector fanout regions under normal and warped conditions using full wave electromagnetic solver. Time-domain simulations are used to evaluate eye height and eye width variations for Non-Return-to-Zero (NRZ) signaling (e.g., PCIe 5.0 at 32 GT/s) and Pulse Amplitude Modulation 4-level (PAM4) signaling (e.g., PCIe 6.0 at 32 GT/s).

Warpage, defined by IPC-2221 as Bow (arc-like bending) or Twist, is quantified using the formula (R1−R2)/L×100%, with a focus on typical 0.74% warpage (1 mil height) in connector regions and 0.53% in BGA areas—parameters aligning with both industrial standards (0.75% max for SMT components) and tightened engineering norms (≤0.5%).

Three-dimensional (3D) modeling reveals that warpage distorts signal paths, increasing insertion loss (IL) and return loss (RL). For example, in BGA regions, IL shifts from -0.15 dB to 0.15 dB, and RL deteriorates from -32.72 dB to -29.91 dB under warpage, while connector fanout areas exhibit RL degradation from -19.75 dB to -19.22 dB, verifying via networks’ sensitivity to geometric deformation. Frequency-domain analysis confirms impedance discontinuities caused by warpage intensify above 16 GHz, severely affecting high-frequency signals.

Time-domain analysis reveals that PCB warpage reduces eye height significantly for both NRZ and PAM4 signaling, while eye width remains relatively stable. For PCIe 5.0 (NRZ), eye height decreases by 3.8% from 163 mV to 157 mV, and for PCIe 6.0 (PAM4), the top eye height drops by 10.2% from 43 mV to 39 mV. This degradation is primarily attributed to amplitude fluctuations induced by warpage, which predominantly affect the vertical signal margin. In contrast, timing characteristics, such as jitter and offset remaining largely unaffected and receiver equalization techniques help maintain eye width stability. Despite the reduction in eye height, the bit error rate (BER) requirements 1E-12 for PCIe 5.0 and, 1E-6 for PCIe 6.0 provide sufficient margin to tolerate limited signal degradation without compromising transmission reliability. The system’s ability to absorb moderate levels of noise and reflection ensures continued compliance with performance standards.

This study innovates by:
① Quantifying the correlation between 0.74% warpage and 1 mil physical deformation, enabling cross-scale analysis from geometric to electrical degradation.
② Comparing NRZ/PAM4 eye diagram parameters to reveal multi-level modulation’s higher warpage sensitivity—PAM4’s smaller eye margin (6 mV vs. NRZ 15 mV) exacerbates SI degradation.
③ Proposing a "warpage-loss-eye diagram" analytical framework for PCB design.

Engineering insights emphasize the importance of the collaborative optimization across multiple domains to mitigate the effects of PCB warpage. This includes low CTE substrate material selection, symmetric stack-up design, and tighter process control with reflow temperature gradients.

Looking ahead, future research may explore multi-dimensional warpage phenomena-(Bow-Twist composites) and their impact on high-frequency bands beyond 32 GHz. Additionally, the integration of machine learning offers the promising potential to predict warpage-induced SI degradation enabling smarter design strategies for advanced packaging and high-speed interconnects.

 

Bio:
Ashton Huang received the B.S. degree in applied mathematics from the National Chung Hsing University, Taichung, Taiwan, in 2006, the M.S. degree in statistics from the National Chiao Tung University, Hsinchu, Taiwan, in 2008, and the Ph.D. degree in statistics from the National Chiao Tung University, Hsinchu, Taiwan, in 2016. He is currently a Technical Manager with ASE Inc., Taiwan. His research interests include AI, machine learning, data modeling, and data analysis.

Abstract:
As industrial manufacturing processes become increasingly complex, a wide variety of product defects can arise and evolve rapidly—some may even be never seen. To ensure product quality, AI image-based defect detection technologies have been widely used in the manufacturing industry. For example, Object Detection (OD) techniques learn defect features through human-annotated data and are effective at classifying defect types. In contrast, Anomaly Detection (AD) models learn the features of normal samples and identify anomalies without requiring manually labeled defective data.
Despite these advancements, rapid deployment of image-based defect detection still faces critical challenges in practical applications: a large amount of manually labeled data, a model that can be trained quickly for inspecting new products, and a single model applicable across various product types. To address these issues, we apply the following methods to accelerate model deployment on the production line:
Synthetic Data (SD) We leverage the Domain Randomization method, a technique of Synthetic Data (SD), to automatically generate defect images. This approach not only enhances the model's classification capability but also reduces the need for defect data collection. In our experiments, we trained the model on approximately 5,000 human-annotated substrate defect images. The results show that with SD, the model's recall increased from 82.1% to 93.1%, and precision improved from 82.2% to 93.4%. Furthermore, SD enables the model to achieve the original accuracy using half the size of the original dataset.
Light Anomaly Detection Model (LADM) The goal of the LADM model is to enable rapid deployment for product inspection. We modified the PatchCore AD model to develop a faster, high-performance, low-resource version. The model can be trained in under three minutes using around 1,000 normal samples with 512x512 image resolution. It achieves a high AUROC, with an overall average of 97.27% on the MVTec AD dataset.
Cross-Product Anomaly Detection Model (CADM) The semiconductor manufacturing industry typically offers a wide variety of products to meet customization demands. Training a separate AI model for each product leads to a large number of models, creating challenges in maintenance. We modified existing AD models into a generalized version applicable across multiple products. In our experiment, we trained a substrate dataset of around 1,000 samples from different products. The escape rate is under 0.05%, the false positive rate below 1%, and about 10% of cases are judged as uncertain, requiring human inspection. This approach enhances model management efficiency while maintaining high detection accuracy.

We integrate three technologies—SD, LADM, and CADM—into a unified detection framework. When a new product requires inspection, LADM is trained for immediate deployment to monitor production. Meanwhile, normal images are used to train CADM, gradually improving its accuracy. Once CADM outperforms LADM, it replaces LADM in the detection workflow. Anomalous data is labeled by humans and combined with SD to train a comprehensive OD model. OD re-inspects images flagged as anomalies by AD for final quality assurance. This approach improves defect detection, accelerates model deployment, and reduces maintenance costs in manufacturing.

 

Bio:
Have three years of rich experience in the field of artificial intelligence, focusing on algorithm research and software development. Currently, He hold a pivotal role as a core member of the AI team within Universal Scientific Industrial Corpora-tion, specializing in algorithm engineering.

Abstract:
Image similarity comparison is vital for manufacturing tasks like defect detection and quality control, yet conventional text-based searches are slow and error-prone. We propose HOAM (Hybrid Orthogonal Attention Model), a dual-branch network that fuses orthogonal attention mechanisms—using Multi-Head Self-Attention for fine-grained feature extraction and Sub-Center ArcFace loss for robustness to noise. By indexing embeddings with Faiss and performing K-Nearest Neighbors retrieval at inference, HOAM returns the top-5 most relevant images, reducing search time by 80%. Trained on 1,569 classes, HOAM achieves 99.86% Precision\@1, demonstrating state-of-the-art performance in complex, noisy industrial environments. We detail HOAM’s architecture, training strategy, and inference workflow as a high-precision, high-efficiency solution for industrial visual search.

 

Bio:
I have over 20 years of experience in software development and digital transformation across several industries including retail, automotive & luxury cars, telco, manufacturing. Currently, I am leading the industrial digital & control software strategy to drive the industrial digital transformation in the PCB Market through the use of Machine Learning, IIoT, Digital Twin, AI and other technologies.

Abstract:
Background
The increasing demand for environmentally responsible and highly adaptive manufacturing processes has driven the electronics industry toward digitalization. While many existing IIoT and MES platforms offer data collection and visualization capabilities, they often lack enabling real-time optimization or active feedback to manufacturing equipment.
In the context of PCB manufacturing, achieving meaningful sustainability and productivity improvements requires not only data monitoring but also deep integration with control systems and domain-specific insight.
This study presents an industrial case of DFS, a purpose-built IIoT platform for PCB production environments, which uniquely combines real-time data acquisition, process domain knowledge (chemistry and equipment), and closed-loop control integration. It contributes to both Track B1 (Sustainable Materials and Technology) and Track B2 (Smart Manufacturing, Inspection and Testing) by demonstrating how integrated control and optimization can lead to measurable improvements in resource efficiency and production quality.
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Methods
DFS is deployed as a multi-layer digital platform interfacing with diverse data sources, including process equipment, utility infrastructure, and environmental controls. Unlike most industrial platforms which passively collect data for reporting, DFS enables bidirectional communication with programmable logic controllers (PLCs). This allows the system to not only observe but also dynamically and safely adjust process parameters in real time, creating a closed-loop feedback control system based on high-level optimization goals.
The system architecture supports:
• Modeling of energy consumption at the device level using virtual sensors derived from correlated process data
• Rule-based and AI-supported optimization logic, enabling fine-grained equipment control (e.g., pump schedules, idle states, heating routines)
• Historical traceability and contextual data aggregation, enhancing root-cause analysis and predictive diagnostics.
Domain-specific models, rooted in the team’s extensive experience with PCB manufacturing chemicals, process stability, and equipment behavior, are used to interpret raw data in terms of process efficiency, material usage, and potential failure mechanisms.
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Results
The platform was implemented across multiple PCB manufacturing lines, with quantitative and qualitative improvements in both sustainability and operational performance.
For Track B1, sustainable outcomes included:
• Up to 15% reduction in electrical energy consumption achieved via process-aware equipment control (e.g., oven idle-state management, compressor load balancing),
• CO₂ footprint analysis and optimization enabled by real-time modeling without the need for additional hardware sensors,
• Better alignment with environmental compliance frameworks through integrated reporting tools.
For Track B2, smart manufacturing benefits included:
• Up to 50% reduction in troubleshooting time due to multi-source data aggregation and PCB-level traceability,
• Increased reliability in inspection and testing feedback through centralized access to high-resolution process data,
• Implementation of predictive alerts and dynamic thresholds that improved first-pass yield and reduced operator intervention.
A key differentiator of DFS is the active, data-informed control loop between the platform and factory floor systems. This makes it possible to close the gap between optimization logic and physical execution — something that conventional MES or IIoT systems typically lack. The study underscores how the synergy between deep process expertise and integrated control systems can transform traditional PCB manufacturing into a more sustainable, intelligent, and responsive process.

 

Bio:
Mr. Wu is a Manager at Mirle Automation Co. He holds an M.S. in Computer Science from National Chung Hsing University. With over 20 years of experience in software development and system architecture, Mr. Wu has led numerous projects focused on factory system development.

Abstract:
With the rapid advancement of smart manufacturing and Industry 4.0, Automated Material Handling Systems (AMHS) have emerged as a critical element for enhancing production efficiency, reducing operational costs, and strengthening market competitiveness. Currently, PCB factories still heavily rely on manual scheduling and monitoring, which is inefficient and highly struggle to respond to rapidly changing production demands. However, in highly complex processes and high-value material scenarios presented in PCB substrates factories, the implementation of automated material handling equipment such as Automated Guided Vehicles (AGVs), Overhead Hoist Transports (OHTs), and Panel Stockers faces significant challenges in handling efficiency, task scheduling, system stability, and data utilization.

This study proposes a MCS Intelligent Assistant digital solution to overcome material handling bottlenecks and maintain a high throughput rate. The proposed system involves automatically gathering real-time operational data from both MES and MCS systems. Then cleans and formats the data to ensure data integrity and availability. After preprocessing, the system calculates KPIs, such as task completion time, equipment utilization, handling failure rate, and system response time. Analytical charts that visualize transportation routes, equipment status, task allocation, and abnormal events will be provided for visual representation. MCS Intelligent Assistant system can then empower engineers to identify latent problems such as task delays, equipment idleness or route conflicts. The system could analyze transportation tasks, equipment operations and route traffic to accurately locate bottlenecks or high-risk equipment and support more informed scheduling decisions.

This research method can overcome the limitations in manual improvement of bottlenecks and maximize AMHS performance. In usual practice, it can achieve more than 25% reduction in problem solving time and regain productivity. In future work, it is possible to integrate advanced technologies such as Large Language Models (LLMs), the Internet of Things (IoT), and Digital Twin to further enhance this MCS Intelligent Assistant for smart manufacturing and ultimately realizing the grand vision of Industry 4.0.

 

Bio:
Chi Chen is currently a master's student in the Department of Mechanical Engineering at National Cheng Kung University, Taiwan. His research focuses on using machine learning to predict electromigration behavior in low-temperature Sn-Bi solder alloys for reliable electronic packaging.

Abstract:
Driven by RoHS regulations and the continued miniaturization of semiconductor devices, the industry is adopting low-temperature lead-free solders, especially focusing on Sn-Bi alloys. However, reliability issues such as electromigration (EM) effect are still tremendous challenges. This study develops a machine learning model to predict the resistance change induced by electromigration of Sn-58Bi low-temperature solder alloys. The training data are extracted from published literature and focus on resistance changes under different processing conditions. A non-destructive planar joint structure was used in their study, enabling resistance measurement without sample sectioning—an advantage for narrow solder channels where traditional techniques may damage samples. The dataset includes five groups of Sn-58Bi solder data extracted from literature, categorized based on combinations of current density of 2.2, 4.4, 6.6 A/cm², and temperature of 60, 80, 100 °C. These features are used to predict the resistance behavior of solder joints. A Gaussian Kernel Ridge Regression (GKRR) model is employed. Results show excellent predictive performance on the Sn-58Bi dataset, with an R² of ~0.99, indicating an excellent fit between predicted and actual resistance values. The root mean square error (RMSE) is 0.020 ± 0.005, meaning that the average difference between the predicted and actual resistance values is only about 0.02 mΩ, demonstrating both high accuracy and consistency. The framework may provide a promising way for evaluating EM-related resistance behavior in low-temperature solders and can be extended in future work to include additional alloy compositions and experimental validation.

Keywords: Electromigration, low-temperature solder, Sn-Bi alloys, Machine learning

 

Bio:
I am currently a fourth-year Ph.D. student in the Department of Chemical and Materials Engineering at National Central University, Taiwan. My research focuses on electromigration-induced failure mechanisms in solder joints. I have a strong background in solid-state diffusion, phase transformations, and interfacial reactions in microelectronic packaging. I am also proficient in EBSD (Electron Backscatter Diffraction) principles and analysis, with applications in crystallographic characterization of solder microstructures.

Abstract:
Lead-free solder is widely applied in electronic packaging as a critical interconnection for electrical signal transmission between chips. As the industry advances toward solder bump miniaturization and fine-pitch designs to enhance electronic performance, concerns related to electromigration (EM) in solder joints have become increasingly significant. The high current density passing through these joints can lead to phase transformation, under-bump metallization (UBM) dissolution and void formation even open circuit at the cathode, resulting in a substantial increase in electrical resistance. The microstructure evolution at the cathodic interface plays a critical role for EM-induced failure. In this study, the flip-chip solder joints were conducted EM test through energizing with 4.0×104 A/cm2. We focus on the microstructure at the cathode side to discuss the effect of Ni barrier on interfacial reaction of the flip-chip solder joints. Based on the cross-sectional SEM images in the EM-failed Cu/solder/Cu bumps, the Sn phase forms in the consumed Cu-pillar region. In addition, some voids are observed above the as-reflowed the Cu pillar/solder interface, suggesting that Sn phase transformation occurs prior to void formation during Cu pillar consumption. From EBSD analysis, the dihedral angle between current-stressing direction and c-axis of β-Sn is calculated by {001} pole figure. Effect of grain orientation on the Sn back-filled area has been discussed in this study. The back-filled Sn phase exhibits the same crystallographic orientation with the as-reflowed Sn grain. Moreover, the Sn back-filled rate is controlled by grain orientation. It is indicated that Sn grains with a small α angle exhibit a larger back-filling area. When the Cu pillar is covered with a Ni barrier, voids form either at the solder/IMC interface or inside the IMC layer beneath the reflowed Cu/solder joint. Furthermore, in the absence of Sn back-filling, IMCs are formed in the region of the consuming Cu pillar instead. According to EPMA analysis on the cathode side, the IMCs are (Cu,Ni)6Sn5, which indicated that diffusion of Ni atoms would be driven to dissolve into Cu6Sn5 layer to retard the formation of new Sn phase. The suppression mechanism of Sn back-filling has been proposed in this study. As Cu concentration of the solder near the interface between IMC/solder interface at the cathode reduce to lower than Cu solubility under current stressing, Cu6Sn5 will occur dissolution from its surface to transform into a new Sn phase. On the other hand, When Ni atoms dissolve into Cu6Sn5 phase to form (Cu,Ni)6Sn5, Cu6Sn5 dissolution will be retarded leading to suppression of Sn phase transformation because the Ni solubility in Sn is much smaller than the Cu solubility in Sn. Once Ni or Cu atoms are driven by electron flow from (Cu,Ni)6Sn5 near the cathode side to anode side, vacancies continue to accumulate in (Cu,Ni)6Sn5 phase when Cu6Sn5 dissolution is retarded, voids may easier to form.