Sessions Index

Bio:

Chi-Chuan Wang is currently a chair professor in the Department of Mechanical Engineering, National Chiao Tung University, Hsinchu, Taiwan. He received his B.S., M.S., and Ph.D. from the Department of Mechanical Engineering of National Chiao Tung University, Hsinchu, Taiwan during 1978-1989. He then joined the Energy and Environment Research Lab., Industrial Technology Research Institute (ITRI), Hsinchu, Taiwan for about twenty years (1989.10-2010.1) conducting researches related to electronic cooling (liquid-cooling, air-cooling, heat pipe technology, immersion cooling, two-phase high-performance cold plate, data center cooling…) enhanced heat transfer, multiphase system, micro-scale heat transfer, membrane separation, and HVAC&R technology. He joined National Yang Ming Chiao Tung University in 2010 as a professor, working on all aspects of thermal energy systems and heat transfer processes. His editorial services include an associate editor Int. J. of heat and mass transfer (3-year term, term starts from Jan. 2025 to Dec. 2027), a regional editor of the Journal of Enhanced Heat Transfer since 1999, an associate editor of Heat Transfer Engineering since 2003, and an editor of Int. J. of Air-conditioning and Refrigeration since 2013. He has been authors or co-authors of more than 450 international journal articles. He is also a co-inventor of 40 Taiwan Invent Patents and 9 US Patents, and authored three books in association with heat exchanger design and heat transfer. He is also an elected Fellow of ASME (American society of mechanical engineers) and ASHRAE (American Society of Heating, Refrigerating and Air-Conditioning Engineers). He was a member of the Assembly of the World Conference (AWC) on Experimental Heat Transfer, Fluid Mechanics, and Thermodynamics (2009-2017) and a member of the scientific council of the International Centre for Heat and Mass Transfer (2017~2024). He is also receipt of the outstanding research award twice (2017, 2020) from Ministry of Science and Technology, Taiwan. Dr. Wang is actively involving the industrialization of novel concepts with more than 20 industrial sponsored projects currently. From miniature heat pipe, thermosiphon, vapor chamber, pulsating heat pipe, air-cooled heat sink, cold plate w/wo phase change, heat sink, smart energy system, chip/package level thermal management, airflow management in datacenter, PCM thermal system, immersion cooling w/wo phase change, heat transfer augmentation technique, HVAC&R, to huge industrial thermal systems. He is now supervising 40 MS/PhD graduate students along with another 8 Post-docs. His group is the most influential research team/think tank of thermal management to bridge the gap between industry and academics in Taiwan. With more than 455 SCI/EI international journal articles, the Google citation exceeds 25500 with h-index 80, and there are 59 papers are cited over a hundred times. He was listed as in the top 2% of scientists in the world rated by Stanford University in 2020~2024 through Scopus’s impact data. According to the World's Top 2% Scientists list, among the approximately ten-million research scholars in the world, according to the data published in October 2024 from Stanford university, he ranked 11,666 and the lifetime scientific impact ranking was ranked 18,219.

Abstract:

This study incorporates a step-gap structure (VCSG) to enhance two-phase heat transfer of vapor chamber (VC). The step-gap is on top of the boss area to facilitate effective pressurization and accelerating of the generated vapor from the heat source, therefore creating better heat spreading performance. Experiments were conducted using water as the working fluid, with heating load spanning from 80 to 560 W, filling ratios from 61% to 155%, and air flow rate between 33 and 110 CFM. Three step-gap configurations, namely VCSG-1, VCSG-2, and VCWSG-1, were evaluated in comparison with a baseline VC without step gap. For VCSG-1 at an air flowrate of 110 CFM, it is found that the thermal resistances are always lower than those of the conventional VC for all filling ratios (FR), and a pronounced drop of thermal resistance is encountered for VCSG-1 when the filling ratio is raised to 110%, and the maximum heating load can be extended to about 410 W.  The VCSG-2 structure incorporates a thicker step gap, and the thermal performance improves progressively as the filling ratio increases, with enhancements up to 50.9%, and the thermal resistance drop to about 0.072 °C/W for a heating load around 350 W. However, a reversed rise of thermal resistance is encountered when the heating load surpasses 400 W due to excessive evaporation of meniscus liquid in the wick and a possible local dry-out. By raising the filling ratio to 86%, the maximum heating load can reach 550 W at the maximum threshold temperature. The heat transfer mechanisms for the step-gap VCs include evaporation and boiling. 

 

Bio:
2011 Ph.D., University of Hamburg, Germany 2011-2017 Postdoctoral Fellow, RIKEN, Japan 2017-2021 Researcher, Nissan Arc, Japan 2021-now CEO and Founder, ANVOS Analytics Co. Ltd., Japan

Abstract:
Galium nitride high-electron-mobility transistors (GaN HEMTs) are critical for high-power and high-frequency applications, but self-heating effects limit their reliability and performance. Traditional thermal characterization techniques struggle to resolve small temperature gradients in-situ. Here, we present the first use of confocal thermoreflectance microscopy coupled with Rayleigh scattering intensity modulation to map self-heating in a GaN HEMT, offering a non-contact, sub-micron spatial resolution alternative to conventional methods.
A custom confocal microscope (adapted from Raman spectroscopy configuration) was employed to monitor thermoreflectance signals. The GaN HEMT was biased under varying source-drain currents (Ids), inducing Joule heating. The Rayleigh scattering intensity (elastic light scattering) was recorded as a proxy for reflectivity changes (ΔR/R), which correlate with temperature-dependent refractive index variations. The system’s spatial resolution (<1 µm) enabled localized thermal monitoring near the device’s active region.

A clear intensity modulation in Rayleigh scattering was observed with increasing Ids, confirming thermoreflectance sensitivity to self-heating. The scattering signal exhibited a reproducible, monotonic dependence on power dissipation, with localized intensity shifts near the gate edge (hotspot formation).
This work establishes confocal Rayleigh scattering as a viable thermoreflectance probe for GaN devices. Together with the calibrated thermoreflectance coefficient, quantitative temperature mapping can be enabled. The technique’s compatibility with standard optical setups simplifies adoption.
Our approach enables in situ, nanoscale thermal profiling of active GaN HEMTs, critical for addressing self-heating bottlenecks in RF and power electronics. Future work will integrate spectral filtering to enhance signal-to-noise and extend the method to other wide-bandgap semiconductors.

 

Bio:
Chun-Kai, Liu received his Ph.D. from the Department of Mechanical Engineering at National Taiwan University. He is currently working as a manager at the Electronics and Optoelectronics Systems Research Institute of the Industrial Technology Research Institute, specializing in electronic cooling, advanced IC packaging, power electronics packaging, and power conversion systems.

Abstract:
The exponential growth of the global data center market, driven by the rapid expansion of cloud computing, artificial intelligence, and high-performance computing, has resulted in significant increases in server thermal design power (TDP). This surge in power density has rendered traditional air-cooling methods insufficient for ensuring thermal reliability and energy efficiency. In response, liquid cooling technologies—particularly cold plate cooling and immersion cooling—have gained prominence. Cold plate cooling offers precise heat extraction at the component level, making it effective for high-TDP CPUs and GPUs, while immersion cooling enables full-system thermal management and significantly reduces cooling-related energy consumption.
In this paper, we investigate a hybrid cooling approach combining single-phase immersion with cold plate systems to optimize thermal performance and system-level efficiency by numerical simulation. Results demonstrate that this integrated solution achieves up to a 30% improvement in cooling efficiency compared to conventional cold plate setups alone, with a notable reduction in hotspot temperatures and thermal resistances. The findings underscore the potential of hybrid liquid cooling systems as a scalable and energy-efficient thermal management solution for next-generation data centers.

 

Bio:
Kenji Ono is currently the Director of Research Institute for Information Technology at Kyushu University, and he also holds an appointment at Kumamoto University. Before that, he worked at RIKEN Advanced Institute for Computational Science, the University of Tokyo and Nissan Motor Company. He received his degrees of Dr. Eng. in mechanical engineering from Kumamoto University, in 2000. His research fields are Computational Fluid Dynamics, parallel computation, visualization and machine learning for large-scale dataset.

Abstract:
This study presents a high-throughput thermal simulation framework to support early-stage IC design, particularly during floor planning when geometry and power profiles are uncertain. The method enables fast, reliable thermal evaluation to guide design decisions in upstream phases. A Julia-based simulator is developed with automated mesh generation and a pseudo-3D modeling strategy that leverages the near-linearity of temperature distribution in the stacking direction. As transistor integration reaches its planar limits, 3D integration is gaining traction. However, vertical stacking increases power density, raising thermal concerns like localized hotspots. Early 3D-IC design requires optimizing thermal TSVs, chiplet placement, and power delivery under incomplete information. While AI and surrogate modeling offer powerful design tools, they demand high-quality training data, which is hard to obtain across vast design spaces. Thus, rapid and accurate thermal simulation is essential for generating representative datasets. The proposed method automates mesh generation using primitive geometric shapes (Fig. 1). Material properties are assigned to voxel cells using predefined priority rules. The steady-state 3D heat conduction equation is discretized and solved via the BiCGstab method, suitable for asymmetric, ill-conditioned matrices from heterogeneous domains. Results on regular voxel grids confirm near-linear temperature profiles in the vertical direction (Fig. 2). It was also observed that automated meshing may alter heat source volume, affecting accuracy.
With a 60×60×30 mesh and a single Intel Core i5 3GHz CPU core, full simulation including meshing completes in 193 seconds. To reduce computation time further, a pseudo-3D approach minimizes vertical cells and relocates heat sources to silicon surface layers. This maintains accuracy while shortening runtime. Such rapid thermal simulations provide a foundation for training AI-based surrogate models and design optimization workflows. Future work includes modeling anisotropic thermal diffusion, TSV-aware cooling strategies, and layout co-optimization in 3D-IC design.

 

Bio:
Po-Hsun He is a Ph.D. student in the Department of Materials Science and Engineering at National Tsing Hua University. His research focuses on electrodeposition and thermal management, particularly in the modification of copper dendritic structures for wick enhancement in vapor chambers. His recent work investigates how electroplated copper wicks influence fluid transport and thermal resistance within vapor chambers.

Abstract:
With the rapid advancement of technology, high-performance computing (HPC), especially in AI training and CPU/GPU processors, has grown increasingly critical. One of the major challenges these components face is the escalating power consumption and heat density, making effective thermal management essential. Inadequate thermal management can lead to component failure, diminished performance, and long-term reliability issues. To address these thermal challenges, vapor chambers integrated into the lid structure offer an effective solution for chip heat dissipation and advanced packaging. These devices operate by circulating a working fluid between the evaporator and condenser: heat input at the evaporator vaporizes the fluid, which then condenses at the condenser to release heat, while capillary-driven wick structures passively return the condensed liquid to the evaporator.
While vapor chambers provide excellent horizontal (in-plane) thermal conductivity due to rapid vapor diffusion, their vertical (through-plane) heat transfer performance is limited by inefficient fluid transport and suboptimal phase-change efficiency. In vapor chambers, vertical thermal resistance is mainly influenced by evaporation and condensation behaviors. Sufficient fluid supply to the evaporator is crucial for efficient heat removal. If the fluid fails to absorb heat, the evaporator may dry out, leading to a loss of heat dissipation capability. Wick structures with high permeability facilitate fluid return to the evaporator, enhancing both fluid vaporization and overall heat dissipation efficiency.
This study investigates a novel hierarchical dendritic copper wick structure fabricated via a two-step electrodeposition process. The electrodeposited wick exhibits a spatial variation in morphology and thickness in radial direction. The gradient-designed structure achieves a high capillary performance (K/Reff) of 0.55 μm using deionized water as a working fluid. It promotes efficient fluid return by mitigating Marangoni resistance arising from temperature-induced surface tension gradients. The enhanced wick design enables superior vertical liquid transport and sustains evaporation at the hot spot, resulting in significantly improved thermal performance. The vapor chamber with the heterogeneous structure demonstrates a very low thermal resistance of 0.065 °C/W under a high heat power of 600 W, and can achieve a maximum heat dissipation capacity up to 750 W.
Our study centers on optimizing the surface morphology and microstructure of the dendritic coatings. By increasing maximum heat flux and minimizing thermal resistance, we position vapor chambers as the ideal thermal solution for next-generation high-power electronic devices. The novel structures and fabrication methods demonstrated in this research represent a significant leap in thermal management technology.

 

Bio:
Yusuf Rahmatullah is a Ph.D. candidate in Mechanical Engineering at the National Taiwan University of Science and Technology (NTUST), specializing in two-phase flow simulation for advanced thermal management systems. His research focuses on developing accurate and efficient numerical models to simulate phase-change heat and mass transfer in vapor chambers and heat pipes. Yusuf’s work emphasizes the implementation of the Lee model, interface tracking, and temperature-dependent Marangoni effects within ANSYS Fluent and custom solvers. He has investigated the impact of interfacial accommodation coefficients, evaporation layer thickness, and gravitational orientation on simulation stability and thermal accuracy. His recent efforts include full-scale modeling of Si-based vapor chambers, incorporating nucleate boiling, dryout behavior, and thin film evaporation to capture detailed thermal-hydraulic dynamics. He holds a diploma in mechanical engineering from Universitas Gadjah Mada and completed his B.S. and M.S. degrees at NTUST, graduating with distinction. His master’s research focused on the design optimization of pillar-reinforced vapor chambers using CFD and ANOVA methods. Yusuf continues to advance the simulation of two-phase systems with the aim of improving the predictive capability and design of next-generation passive cooling technologies.

Abstract:
Vapor chamber is a two-phase-based cooling solution that offers high equivalent thermal conductivity, ideal for high-power electronic devices. However, maximizing vapor chamber thermal-hydraulic performance requires a well-designed sintered powder pillar, including pillar diameter, pitch, and porosity. Because the present of the pillars may hinder the vapor flow, and neglecting these pillar design factors can adversely affect the performance. In design optimization, numerical analysis offers notable advantages over the experimental one in terms of cost and flow/temperature visualization. This paper uses the Lee model-based numerical scheme combined with the analysis of variance (ANOVA) to systematically examine how those pillar design factors affect thermal resistance, temperature uniformity, and total (liquid and vapor) pressure drops. The results revealed that the pillar porosity has the highest contribution to the thermal resistance, followed by the pillar pitch and the pillar diameter. However, the pillar diameter has the highest contribution to the temperature uniformity and total pressure drops. The optimization result suggests that desirability of 0.77 balances all responses for the best overall thermal-hydraulic performance.

 

Bio:
Chris Lin Wistron Corporation / Thermal Engineer 5 years of experience specializing in thermal design and optimization for server products

Abstract:
With the rapid advancement of AI technology, the heat flux and power density of chips continue to rise significantly. In addition to the development of advanced thermal solutions, thermal interface materials (TIMs) play a critical role in effective heat dissipation. Beside the thermal conductivity of TIMs, their ability to maintain stable cooling performance over the device's lifespan is equally crucial. Regardless of how advanced a thermal solution may be, its effectiveness can be greatly compromised without the use of an appropriate TIM. Various factors, including package design, package coplanarity, and warpage behavior, can significantly impact the performance of TIMs in chip cooling. This study aims to identify a TIM that can sustain efficient heat transferability under humidity and temperature cycling conditions while demonstrating strong pump-out resistance under warpage stresses.
This paper compares the performance of various types of TIMs in two different functional package designs: TIM1.5 for ring-type packages and TIM2 for lid-type packages. Time-zero and post-reliability test results are determined using standalone thermal test vehicle (TTV) testing. Junction temperatures of the TTV are measured with a four-wire thermistor, and junction-to-ambient thermal resistance (Rja) is calculated. Additionally, package coplanarity and cold plate flatness are assessed as key influencing factors. By analyzing the collected data, this study seeks to decouple the contributing factors affecting TIM performance and to identify the reasons behind the advantages and limitations of different TIM types.
This study evaluates the thermal performance of phase change materials (PCMs), thermal grease, thermal gel, and thermal pads under time-zero and reliability testing. At time-zero tests, PCMs, thermal grease, and thermal gel exhibit comparable thermal performance, while thermal pad shows approximately 10% lower performance. Under humidity and temperature cycling tests, thermal grease and thermal gel suffer significant degradation in performance, whereas PCMs demonstrate performance stability with variations within 10%, and thermal pads show even lower variation. Considering the current value of chip warpage, PCMs & thermal pads demonstrate strong competitiveness as a TIM due to their reliable performance and durability under stress. These findings provide valuable insights for optimizing thermal interface material selection for advanced chip packaging applications.
A testing platform and process have been established to validate the thermal performance of TIMs under conditions resembling real chip behavior. This platform is expected to serve as a development reference for the thermal design and selection of TIM1.5 and TIM2, providing a basis for evaluating and understanding TIM behavior across varied scenarios.

 

Bio:
Current working as a senior thermal engineer in ASE Group Chung-Li Branch. Responsible for thermal simulation, thermal measurement and package thermal issue solution.

Abstract:
With the continuous advancement of IC technology toward higher performance, slimmer form factors, and greater miniaturization, packaging technologies are facing increasing challenges in thermal management and reliability. Flip chip technology is a critical step in the package process and has a direct impact on bonding quality, reliability and lifetime of package product. The conventional flip chip bonding technique widely adopted in the industry is Mass Reflow (MR). However, due to its heating characteristics, MR can lead to excessive thermal stress and package warpage. Moreover, bonding defects are more likely to occur with fine-pitch and ultra-fine-pitch bumps under the MR process, thereby limiting its applicability for advanced packaging.

Laser Assisted Bonding (LAB) is an emerging flip chip bonding technology. By irradiating the package with a laser, the chip and substrate absorb laser energy and rapidly convert it into heat. The localized heating allows the solder to reach their melting point and bond to the substrate. Since the heat is concentrated in and around the chip region, LAB significantly reduces the overall temperature rise, shortens process time, and minimizes the heat-affected zone—enhancing both the flexibility and reliability of the packaging process. However, the rapid and localized heating may cause uneven temperature distribution. If key parameters such as laser beam size, power, and irradiation time are not properly controlled, issues like cold welding or incomplete bonding may arise. Thus, accurately predicting temperature rise and thermal distribution is essential for successful LAB implementation.

This study employs three-dimensional thermal modeling and transient thermal analysis to simulate the LAB process. The simulation predicts both the overall temperature rise across the package and the temperature rise for specified points. The results are validated against experimental data, confirming that the simulation approach effectively replicates the LAB process. This study not only offers valuable insights into thermal behavior during LAB, but also provides a practical simulation tool for thermal management and process optimization—particularly in high-end packaging applications.

 

Bio:
Professor Chi-Hua Yu is a scholar in artificial intelligence and advanced semiconductor packaging, with expertise in multiscale modeling and computational mechanics. He earned his Ph.D. from National Taiwan University in 2014 and conducted postdoctoral research at the Massachusetts Institute of Technology (MIT) from 2018 to 2020. Since 2020, he has been a faculty member at National Cheng Kung University, where his research focuses on applying AI techniques—such as deep learning, reinforcement learning, and generative modeling—to the design and optimization of electronic packaging systems. His work addresses key challenges in thermal management, mechanical reliability, and structural innovation for 2.5D/3D IC and fan-out packaging technologies. In parallel with his academic role, Prof. Yu is the founder and Chief Technology Officer of NeuroShine Ltd. Co., a university spin-off committed to developing AI-driven EDA tools for intelligent semiconductor design and advanced manufacturing. His combined academic and entrepreneurial efforts seek to bridge artificial intelligence with next-generation electronic system design.

Abstract:
Efficient thermal management remains a formidable challenge in high-power electronic systems, where escalating power densities and progressive miniaturization have rendered conventional cooling strategies inadequate. These limitations not only constrain system performance but also compromise long-term device reliability. While microfluidic cooling systems present a promising alternative, their optimization has traditionally depended on computationally intensive and time-consuming simulations, which often struggle to navigate the complex, multiphysics design landscape. To address these bottlenecks, this study introduces an integrated, AI-driven framework aimed at accelerating and automating the design of high-performance microfluidic cooling channels for electronic microchips. The primary objective is to establish an autonomous and intelligent design methodology that delivers thermally efficient and mechanically robust solutions.
The proposed framework leverages a hybrid computational strategy. Initially, the Representative Volume Element (RVE) approach, combined with the Finite Element Method (FEM), is employed to generate a diverse dataset comprising 2,160 unique microfluidic configurations. These designs systematically vary channel geometries and patterns, capturing twelve critical thermal and mechanical properties—including Young’s modulus, yield strength, and directional thermal conductivity. To circumvent the high computational costs of iterative FEM analyses, a dual-input convolutional neural network (CNN) is constructed to serve as a high-fidelity surrogate model. This network simultaneously ingests geometric images and numerical parameters of microchannel designs, providing real-time predictions of material properties with high accuracy.
Subsequently, a Deep Q-Network (DQN) reinforcement learning algorithm is integrated into the design loop to autonomously explore the vast design space. The DQN agent, informed by real-time feedback from the CNN surrogate, iteratively adjusts key design variables—such as channel width, spacing, and depth—toward optimizing vertical thermal conductivity (k₃₃). This dynamic exploration allows for rapid convergence to non-intuitive yet high-performing configurations.
The AI-driven framework exhibits exceptional predictive and optimization capabilities. The CNN surrogate consistently achieves R² values exceeding 0.99 across all twelve target properties when benchmarked against FEM simulations. The DQN algorithm effectively identifies innovative designs that demonstrate significant improvements in vertical thermal conductivity. Subsequent validation using computational fluid dynamics (CFD) and thermo-mechanical warpage simulations confirms the practical viability of these AI-generated solutions. Optimized configurations successfully maintain ASIC and HBM chip temperatures within safe operating limits while simultaneously reducing package-level warpage.