Sessions Index

Bio:

Andreas Ostmann, born 1966 in Berlin, studied Physics and received his Ph. D. in Micro System Technologies at the Technical University of Berlin. Since he joined Fraunhofer IZM in 1992, his research focus is on advanced packaging technologies. He is head of the department System Integration and Interconnect Technologies. His research group is involved in the developed of large-area processes for chip embedding, System-in-Package and advanced substrates. Andreas is author of a large number of publications and holds several patents on advanced packaging technologies.

Abstract:

In order to meet the bandwidth, form factor and power management requirements of computing systems for AI applications based on chiplet architectures, high-end packaging is required. Substrates for chiplet systems must overcome a number of challenges. Their connection density must allow the chiplet wiring to continue seamlessly. This necessitates structure widths of just a few µm and minimal electrical losses. Although substrates based on organic cores are a proven technology, they reach their limits with very high connection densities. Glass core substrates can address these geometric challenges and facilitate multiple sub-µm wiring layers in the future.
This presentation will outline some aspects of the process flow for glass core substrates. A study will demonstrate where a transition from organic to glass cores is necessary to achieve the geometric stability required for high densities. Reliability studies on copper-filled through glass vias (TGVs) will also be presented.

 

Bio:
Masaya Ukita was born in Kyoto, Japan, in 1990. He received the ph.D. degree in Engeneering from Nagoya University, Aichi, Japan in 2019. He is curently the Assistant Research Engineer of the Reliability Group, ROHM Company Ltd, Kyoto. His current research interest is the reliability of semiconductor packages.

Abstract:
Please refer to the attached PDF file. The PDF file totally follows IMPACT's guideline for submission.

 

Bio:
Hsueh-Chih Liu received his bachelor's degree in Mechanical Engineering from Yuan Ze University and went on to complete master's degree in Mechatronics and Mechanical Engineering at National Sun Yat-sen University. He has professional experience as a research and development engineer at TECO Electric & Machinery Co., Ltd. and China Motor Corporation. Currently, he is pursuing Ph.D. at the Advanced Institute of Manufacturing with High-tech innovation (AIM-HI) in National Chung Cheng University, with a research focus on probe testing in advanced electronic packaging.

Abstract:
Currently, the development of semiconductor chip packaging continuously shrinks to light weight and high integration density structure. Meanwhile, the structural dimensions of interconnect system in advanced electronic packaging also being smaller and smaller; therefore, the mechanical response induced by probing test and its influence on interconnect system must be studied. In this study, the numerical and experimental approach are performed to analyze the probing mark formation of aluminum (Al) pad on silicon (Si) wafer. The test vehicle of 6-inch Si wafer with PVD Al coating is shown in Fig. 1(a), the thicknesses of PVD Al coating and Si wafer are estimated as 1.4 μm and 675 μm, respectively. The 10 × 10 mm2 micro chips were diced from Si wafer for subsequent single probing test with Cobra-type needle.

To explore and understand the contact phenomenon and mechanical response of Cobra-type probe needle and Al pad, a finite element method (FEM) modeling was demonstrated with the Cobra probe needle and representative domain of Si wafer with PVD Al coating, the domain area and thickness of Al pad/Si wafer bi-layer system were defined as 0.04 × 0.04 mm2 and 10 μm, respectively. The Cobra probe needle and Si wafer are assumed as linear elastic material with Young’s modulus of 123 GPa and 130 GPa, respectively; and the Al pad is considered as elasto-plastic material to study the probing mark formation behavior, the Young’s modulus and yielding stress are separately considered as 69 GPa and 39 MPa.

The single probing test is accomplished by a customized fixture and MTS Acumen eletrodynamic test system, the test speed is set as 0.5 μm /sec to applied the external overdrive (OD) displacement similar to the actual wafer probing test approach. As shown in Fig. 3, a simulated probing mark with side pile-up along scratch direction is formed on Al pad under applied OD displacement, which is highly comparable to the experimental measured surface profile by AFM (Referred to Fig. 4). The relationship of contact force and external applied OD are illustrated in Fig. 5, which the contact force gradually increased from ~0.02 N to ~0.047 N and revealed the stable contact during single probing test. The demonstrated approach combined numerical and experimental methods are benefit to systemically investigate the probing mark formation phenomenon during wafer probing test with different probe needle geometries.

Fig. 1(a) 6-inch Si wafer with PVD Al coating; (b) Detailed dimensions of Si wafer and Al pad.

Fig. 2 FEM modeling of Cobra probe needle and Al pad/Si wafer structure.

Fig. 3 Simulated displacement contour on surface of Al pad.

Fig. 4 Topography of probing mark on Al pad.

Fig. 5 Contact force estimation during probing test with different OD consideration.

 

Bio:
Shang Yi Lim is currently pursuing an Engineering Doctorate (EngD) in Electrical Engineering at the National University of Singapore, where he works closely with both academic and industry partners to advance semiconductor failure analysis methodologies. His research focuses on the integration of artificial intelligence and machine learning in failure analysis, with an emphasis on physics-guided approaches for defect localization. With seven years of experience in silicon die failure analysis at AMD, Shang Yi has played a key role in developing advanced sample preparation workflows and interconnect defect detection strategies for cutting-edge packaging technologies and advanced technology nodes.

Abstract:
3D integrated circuits (3D ICs), realized through chip stacking (3D packaging) or device-layer stacking (3D monolithic integration), represent a significant leap beyond conventional planar architectures by enabling dense and heterogeneous integration. When combined with other heterogeneous system designs, these advanced packaging technologies offer substantial benefits in terms of modularity, signal integrity, mixed-signal co-integration, cost reduction, and footprint minimization. However, as integration density increases, the complexity of failure modes escalates, introducing critical challenges in yield, diagnostic turnaround time, and long-term reliability. While machine learning (ML) techniques, particularly neural networks (NNs), have been proposed to automate defect detection and prediction, their utility in high-reliability domains remains limited by their “black-box” nature, poor generalizability across evolving failure modes, and a lack of physical interpretability. To address these limitations, we propose a physics-informed modular stochastic framework based on Markov Chain Monte Carlo (MCMC) methods to learn and guide failure analysis with relevant physics progressively. Due to the inherent rarity of defective samples and the data requirement of machine learning models, we first construct a well-calibrated TCAD digital twin based on transistor and interconnect physics. The physics-guided digital twin model generates data on command and provides a holistic understanding of the 12 extracted data features from the electrical characterisation of defects across the interconnect and chip layers. Some key data features include the maximum and minimum node currents, as well as signal delay metrics, which are closely correlated with defect-induced parasitic resistance and capacitance. Finally, the MCMC models are trained to estimate the probabilistic distributions of physical features, enabling traceable and interpretable predictions that connect the most indicative feature sets to their underlying defect mechanisms. This not only facilitates informed physical diagnostics but also provides greater transparency into model decisions critical for failure analysis. The final trained model achieves 96.0% accuracy in predicting faulty signal paths and 75.7% accuracy in localizing specific faults within interconnect structures when applied to advanced CMOS inverter stack test structures. Furthermore, the modular architecture supports continual learning, allowing the seamless integration of new defect data without full model retraining. With the sequential introduction of defect class, defect localization accuracy and signal fault prediction increase steadily from 9% to 75.7% and 32% to 96% respectively. This adaptability suits the evolving nature of semiconductor manufacturing, where new failure signatures continually emerge. By combining physics-based modeling with probabilistic machine learning, our approach offers a scalable, explainable solution for next-generation failure diagnostics and reliability engineering in advanced heterogeneous packaging enhancing both the efficiency and confidence of fault localization for future system-in-package designs.

 

Bio:
Ming-Yi Tsai received the B.S. degree in civil engineering from the National Cheng Kung University, Taiwan, in 1982, and the M.S. and Ph. D. degrees in engineering science and mechanics from the Virginia Polytechnic Institute and State University (Virginia Tech), USA, in 1988 and 1990, respectively. Currently, he is a professor at the Department of Mechanical Engineering, Chang Gung University, Taiwan. He has published more than 150 technical papers in journals and conferences. He serves as an associate editor of J. Electronic Packaging, ASME, and J. of Mechanics for international journal paper publications. His research of interest is in electronic/optoelectronic packaging, photomechanics, adhesive bonding, and mechanics of composite materials. He was the president of IMAPS-Taiwan from 2018-2021 and is also a member of IEEE, ASME, and IMAPS

Abstract:
The three-dimensional integrated circuits (3DIC), stacked-die, or wearable electronics packages gain increasing popularity in subsystem or system packaging applications for satisfying the requirements of small size, low-profile features, high-pin count, high performance, low power consumption, or flexibility. In such applications, the silicon wafers of integrated circuits (IC) need to be thinned to their target thicknesses, typically in the range of 10 μm to 150 μm. The strengths of the silicon die cut from the wafers must be characterized after wafer thinning and sawing processes to fulfill the package design requirements in order to ensure short-term manufacturing yield and long-term reliability. The ring-on-ring test (RoR) is one of the standard tests for biaxial bending, suggested in ASTM C1499-19 and ISO 17167. This test has been widely applied to determine the biaxial bending strength of silicon dies to avoid the die edge effect of the four-point bending tests. However, from the literature, when the relatively thin silicon dies are tested, this test suffers from a geometric nonlinearity effect and thus results in overestimated maximum stress calculated simply by the theoretical solution. This study aims to investigate the mechanics issue in the RoR test experimentally, theoretically, and numerically by considering the geometric nonlinearity. A 2D-isotropy model of a nonlinear finite element method (NFEM) simulation is utilized and verified by experiments, and a 3D-anisotropy model in terms of deformation (or displacement) and stresses. Based on the 2D-isotropy NFEM solutions, the fitting equations of correction factors to modify the theoretical linear solution are proposed and implemented to determine the bending strength of 10 mm × 10 mm silicon dies with thicknesses ranging from 57 μm to 297μm. It has also been proved that the RoR test using the theory associated with the correction factor fitting equations can be easy to use to successfully determine the biaxial bending strength of the thin silicon dies that frequently failed in the nonlinear range.

 

Bio:
Masaaki Koganemaru was born in Fukuoka, Japan, in 1968. He received a Bachelor of Engineering degree in Nuclear Engineering and a Master of Engineering degree in Science and Engineering from Kyushu University in 1992 and 1994, respectively. He earned a Ph.D. in Mechanical Engineering from Kyoto University in 2008. From 1994, he worked as a researcher at Fukuoka Industrial Technology Center in Kitakyushu, Japan. In 2016, he became an Associate Professor at Kagoshima University. Since 2025, he has been serving as a Professor at Kagoshima University. His research interests include device simulation of strained-silicon MOSFETs and stress or strain measurement in electronic packages.

Abstract:
The demand for miniaturization in electronic packaging continues to grow, driving the development of flip-chip bonding technology capable of high-density implementation. In this flip-chip bonding, direct Cu-Cu bonding technology using Cu pillar bumps without solder has gained attention. This bonding method prevents short circuits caused by bridging between bumps during heating, as the bumps do not melt, making it suitable for fine-pitch applications. Additionally, the low electrical resistance of Cu is another advantage. However, the increased rigidity of the bonded parts raises concerns about increased stress on semiconductor chips and joints, potentially affecting mechanical reliability.
Currently, the behavior and reliability of microstructures such as Cu pillar bumps are mainly evaluated through simulations like the finite element method. It has been pointed out that the mechanical behavior of microstructures can differ significantly from bulk materials due to differences in crystal structure. Therefore, it is essential to ensure the validity of material properties and simulation results by comparing them with experimental results. In other words, to ensure the validity of simulations, it is necessary to measure and evaluate the behavior of Cu pillar bumps (deformation, strain, and stress under load).
In this study, a system and method were developed to measure the deformation and strain of Cu pillar bumps under compressive load, simulating the conditions during mounting (bonding). This test system consists of a CMOS camera for capturing specimen images, a micro-load testing machine with a piezo actuator for applying displacement (load) to the specimen, and a load cell for detecting the load. Digital Image Correlation Method (DICM) was applied to the images of Cu pillar bump specimens obtained by the CMOS camera to measure the displacement distribution (discrete point displacement) within the Cu pillar bumps. The Moving Least Squares Method was then applied to the discrete point displacement distribution to determine the displacement field, which was differentiated to obtain the strain distribution.
In this study, compression tests and strain measurements were conducted on Cu pillar bumps formed on Si chips at a scale of tens of micrometers. The Cu pillar bump specimens were prepared by ion milling to expose the height-direction cross-section of circular bumps as the DICM observation surface. As a result, DICM was applied to the images of Cu pillar bumps during compression tests, and the strain distribution within the Cu pillar bumps was successfully obtained. Finite element method simulations mimicking the compression tests were also conducted and compared with the strain measurement results. The order of strain values was approximately consistent between the two, but differences in strain distribution were observed. One possible reason for this is that the finite element method simulations did not consider the anisotropy of material constants in Cu pillar bumps. Specifically, it is suggested that there is anisotropy in the material constants in the width and height directions of Cu pillar bumps. In the future, experimental data will be increased to verify the validity and reproducibility of the test system and method.

 

Bio:
Chao-Ching (Burt) Ho received his B.S. and M.S. degrees from National Taiwan University, Taipei, Taiwan, R.O.C., in 1995 and 1997, respectively. He earned his Ph.D. in electrical engineering from the National Taiwan University of Science and Technology, Taipei, Taiwan, in 2008. He served as a naval engineer officer from 1997 to 1999. From 1999 to 2003, he worked as an R&D manager at 3DFamily Inc. From 2009 to 2016, Dr. Ho was an Associate Professor in the Department of Mechanical Engineering, National Yunlin University of Science and Technology. He joined National Taipei University of Technology in 2016 as a Professor at the Graduate Institute of Manufacturing Technology and Department of Mechanical Engineering, and he has held the title of Distinguished Professor since 2024. His research interests include industrial AI, in-situ monitoring and inspection, laser drilling and ablation, electrical chemical discharge machining, machine vision, as well as stereo vision. He has served as an academic editor for the Journal of Technology (JOT), Smart Science, British Journal of Applied Science & Technology, Journal Technologies, Journal of Science and Innovation , and as an Associate Editor for the International Journal of Innovative Technology and Education. Additionally, he has been a topic editor for Chemosensors and a board member of the World Journal of Textile Engineering and Technology. He is a member of SME (Society of Manufacturing Engineers, Taipei), SPIE and the International Measurement Confederation (IMEKO) TC10 (Measurement for Diagnostics, Optimization & Control).

Abstract:
With the rapid adoption of Industry 4.0 and smart manufacturing paradigms, production is shifting toward small-batch, highly customized runs, where new products cycle through the line at an ever-increasing pace. Traditional supervised defect inspection methods—which rely on thousands of labeled faulty samples and require retraining a dedicated model for every new board design—impose prohibitive annotation costs and lengthy redeployment timelines. Although unsupervised anomaly detection techniques alleviate the need for negative examples by learning exclusively from defect-free data, they still typically require separate models per product family and often suffer from unstable reconstructions and high false positive rates when confronted with the intricate textures and fine geometries of printed circuit boards (PCBs). In contrast, PCB fabrication workflows inherently provide precise CAD design files that encode the ideal board layout, and the universe of possible component arrangements—copper traces, solder pads, vias, silkscreen patterns, and substrate backgrounds—is finite and well defined. Leveraging this rich prior, we present a unified anomaly detection framework that trains only once, yet generalizes across multiple PCB product lines without full model retraining. At its core lies a bidirectional generative adversarial network: a “real-to-CAD” branch learns to map photographed PCB images—including those with latent defects—back to their idealized CAD representations, thereby internalizing canonical board structure; a complementary “CAD-to-real” branch synthesizes high-fidelity, defect-free PCB images from CAD inputs, enabling the network to capture the visual characteristics of normal textures under varying lighting and imaging conditions. During training, we augment the non-defect dataset with a synthetic anomaly generation pipeline that simulates broken traces and microscopic scratches. We further stabilize the dual-domain mappings by enforcing cycle consistency constraints and optimizing a structural similarity loss that emphasizes high-frequency detail retention. These design choices ensure that, in the absence of defects, the reconstructed images closely match real inputs—whereas even subtle deviations caused by manufacturing errors manifest as pronounced reconstruction-error residuals. At inference time, a query PCB image is processed through the real→CAD→real reconstruction cycle, and an anomaly heat map is generated by computing per-pixel reconstruction discrepancies and applying a threshold. Crucially, because the CAD prior comprehensively defines all valid component layouts, extending our framework to a novel PCB design requires only the provision of its CAD file—with no need to retrain the core network. This yields a highly efficient, flexible, and easily deployable solution for industrial anomaly detection. Our approach melds domain-specific prior knowledge with adversarial learning to deliver robust, low-cost quality inspection. It not only dramatically reduces data collection and retraining overhead, but also ensures consistent detection sensitivity across diverse PCB lines—making it ideally suited for any manufacturing setting equipped with CAD resources.

 

Bio:
I studied Chemical Engineering at Ming Chi University of Technology. After graduation, I worked as a Manufacturing Engineer at Unimicron Technology Corporation for about 1.5 years. Seeking to improve my professional knowledge, I left the job and am now studying at National Central University in the Department of Chemical and Materials Engineering. My research focuses on how different solder alloy compositions and solder ball sizes affect the reliability of Ball Grid Array packaging.

Abstract:
As AI chips evolve toward higher I/O density and advanced integration, smaller BGA solder balls are increasingly required to meet the electrical, thermal, and mechanical demands of high-end device applications. This study evaluates the reliability of lead-free solder joints by examining the effects of solder ball size and alloy composition. Each package was assembled with two types of solder pastes: the conventional SAC305 (Sn–3.0Ag–0.5Cu) and a new SABN alloy (Sn–4.0Ag–3.0Bi–0.05Ni). Two BGA package types were used: CTBGA228 with 0.30 mm SAC305 solder balls (SAC305(S)) and CABGA192 with 0.45 mm SAC305 solder balls (SAC305(L)). All solder joint combinations are summarized as SAC305/SAC305(S), SABN/SAC305(S), SAC305/SAC305(L) and SABN/SAC305(L).
All samples were subjected to two reliability tests: drop testing at 1500 G acceleration over a 0.5 ms duration using a half-sine waveform (JESD22-B111A), and thermal cycling from –40 °C to 125 °C with a ramp rate of 15 °C/min and a dwell time of 10 minutes (IPC-9701B). After testing, SEM and EDS were conducted to examine the microstructure and intermetallic compound (IMC) at fracture locations. EBSD investigated the relationship between recrystallization behavior and crack propagation after thermal cycling.
The reliability test results in the table I show that CTBGA228 exhibited earlier failure than CABGA192 during the drop test. In the CTBGA228 package, cracks in the smaller solder balls initiated and remained within the interfacial IMC layer (Fig. 1a). In the CABGA192 package, cracks propagated either along the IMC layer or into the solder bulk (Fig. 1b). The larger solder balls in CABGA192 absorbed more impact energy during the short loading period, which led to cracking at the interface or in the solder bulk.
During the thermal cycling test (TCT), the smaller solder joints in CTBGA228 exhibited a greater number of failure cycles than those in CABGA192. A comparison of crack types observed during TCT revealed different fracture characteristics between the two package types. Recrystallization in the solder balls is associated with stress distribution and relaxation within the joints. In CTBGA228, recrystallization occurred both at the neck region and near the center of the solder joints, whereas in CABGA192, it was observed only at the neck region. These differences in recrystallization behavior influence the lifetime of the solder joints under TCT.
Table I shows that the SABN/SAC305 solder joints exhibit better reliability performance than SAC305/SAC305 solder joints, especially in smaller BGA solder joints. The SABN/SAC305 solder joints tend to form a (Cu,Ni)₆Sn₅ IMC layer with the Cu pad, which enhances the mechanical stability of the interfacial IMC. The higher Ag content in the SABN alloy promoted the formation of larger Ag₃Sn particles in the SABN/SAC305 solder joints. These Ag₃Sn particles enhanced recrystallization, which led to intergranular crack propagation under thermal stress.
This study demonstrates that solder ball size significantly affects reliability. In smaller BGA solder joints, the mechanical properties of the IMC layer, thermal stress distribution, and recrystallization behavior play a more significant role in failure mechanisms. These findings provide valuable insights for optimizing BGA package design and solder alloy selection in high-reliability electronic applications.

 

Bio:
Pin-Jing Su is presently Deputy Manager of material technology department of R&D at Siliconware Precision Industries Co., Ltd. (SPIL) Over 12 years of job experience in semiconductor industry (focus on assembly field) and he is in charge of new advanced material development and management in SPIL currently. He has authored/co-authored 5 papers and 16 patents in the advanced packaging field.

Abstract:
In the booming era of Artificial Intelligence (AI), the high-performance computing (HPC) products focus on the pursuit of processing large amounts of data and fast calculations for efficient training and inference of AI models. Furthermore, the product will be required to enhance the heat dissipation ability to maintain computing efficiency, due to the high-density transistor in chips and the evolution of high-power input design. For the package application, flip chip ball grid array (FCBGA) is the well-known solution that has high IO and fine line width and line space design features. Therefore, the thermal interface material (TIM) selection plays an important role in the performance of high-end products. Currently, there are three major TIM material types including gel type, film type and metal type, which are used in different thermal dissipation requirements. Among them, film and metal types usually used for high heat dissipation products of HPC applications because of high thermal conductivity and low thermal resistance benefits. Thermal resistance is defined as the measurement of heat dissipation capacity of a package. It can involve the thermal characteristics of material bulk and contact interfaces. In the case of solid metal TIM, the lowest thermal resistance is exhibited due to the high isotropic thermal conductivity and high wettability of the contact surface after metal melting and bonding. However, it presents some challenges including high TIM stress and the necessity for additional back side metal (BSM) treatment for the contact surface with TIM material. In the case of liquid metal TIM, it can overcome the high stress and without the necessity for BSM. However, there are existing workability challenges including the design of sealed structures and the necessity for advanced liquid filling technologies. Conversely, the film type of Graphite TIM can be capable of addressing the aforementioned challenges, although its thermal resistance property is still higher than that of metal TIM. Therefore, we are studying a new film type material that is composed of liquid metal and carbon fiber. The melting point of this liquid metal alloy was measured to be approximately 31℃ by DSC. Thus, it is solid phase at room temperature. This composite film type material has the capacity to combine the workability of film type material and the thermal resistance reduction characteristics of metal type material.
The present article focuses on the discussion of material thermal properties and process workability. First, the thermal properties of this novel film material were measured such as thermal conductivity and thermal resistance. All thermal properties are superior to those of conventional Graphite TIM. Secondly, the solutions of high-risk processes were evaluated. These processes included TIM attachment, add the heating stage under the substrate and temperature setting greater than 31℃ that can prevent TIM shift risk in process because of the film material is non-polymer-based and non-adhesive. For HS process, when the TIM size is larger than die size, the liquid metal bleeding risk can be reduced. This is attributable to the extra TIMs around, which serve to enhance the resistance of liquid metal and thereby prevent bleeding out. To conduct a TIM coverage inspection by SAT, it is necessary to utilize a low-frequency probe that can enhance the penetration of ultrasound to get the readable TIM coverage image. In the meantime, the TIM material change of appearance was collected following the reliability conditions. The foaming of liquid metal alloy was found after uHAST condition, which directly influenced the TIM coverage. Therefore, the liquid metal alloy requires adjustment and enhancement in the subsequent stage. In conclusion, although this study did not achieve the expected results, it has provided new inspiration for research in related fields.