Sessions Index

Bio:

Dr. Sam Dharmarathna earned his Ph.D. from the University of Connecticut and is currently a Line of Business Partner for IC Substrate R&D at MacDermid Alpha Electronics Solutions. With a strong background in materials chemistry and electrochemistry, Dr. Dharmarathna specializes in developing innovative metallization solutions for IC substrates, driving advancements in advanced packaging, redistribution layers (RDL), and glass substrate technologies.
As a published author with over 30 technical publications.

Abstract:

Saminda Dharmarathna, Leslie Kim, Peter Chang, Steven Tam, Brian Gokey, Ernie long

The global IC substrate market is experiencing robust growth, projected to expand from USD 15.1 billion in 2024 to USD 37.1 billion by 2033, fueled by the rising demand for advanced semiconductor packaging solutions in artificial intelligence (AI), 5G, and high-performance computing (HPC) applications. As chip dimensions shrink and interconnect densities increase, IC substrates are evolving to incorporate wafer-level precision manufacturing techniques traditionally associated with front-end semiconductor processing. This evolution necessitates plating solutions capable of delivering ultra-fine line and space (L/S) structures, defect-free via filling, and highly planar surfaces — all critical for ensuring multilayer stack integrity and superior electrical performance.

In this study, we present an innovative copper electroplating process specifically tailored for advanced IC substrates, utilizing wafer-level technology principles adapted for substrate manufacturing. The process is optimized for embedded trench fill, simultaneous via fill, and through-hole plating with enhanced pattern plate capability. A bottom-up copper filling mechanism, driven by a finely tuned additive package—including suppressors, accelerators, and levelers—ensures uniform, defect-free filling of microvias and trenches. This approach eliminates common defects such as V-pitting, seam voids, and uneven copper deposits, while removing the need for costly and energy-intensive post-bake treatments.

To enable high-volume production with superior quality, the process is specifically designed for integration into High-Speed Plating (HSP) systems. HSP tools offer rapid throughput, precise current control, and uniform fluid dynamics, making them ideal platforms for advanced substrate electroplating. Leveraging HSP capabilities, the process ensures excellent via fill quality, superior co-planarity across the entire panel, and high mechanical and electrical reliability—critical attributes for AI and HPC applications.

Comparative studies show that the new plating process achieves significantly flatter pattern profiles and improved microvia filling compared to traditional dome-shaped plating outcomes. The resulting copper deposits demonstrate enhanced mechanical strength and elongation, meeting the rigorous demands of next-generation semiconductor packages.

By translating wafer-level precision into high-speed, panel-level manufacturing, this solution sets a new benchmark for IC substrate technology. It provides a scalable, efficient, and reliable pathway to meet the evolving performance and miniaturization requirements driven by the explosive growth of AI and HPC markets.

 

Key words

Artificial Intelligence (AI), Advanced packaging, Modified semi-additive processing (mSAP), IC Substrates, Electroplating, Uniformity.

 

 

Bio:
Michael Lo is PSC’s APAC Applications and Business Development Manager with rich professional experiences ranging from IR/Raman, AFM, material characterization to sample preparation, material synthesis, polymer-drug formulations and business development. Since 2018, he leads the technical market development of the novel submicron IR super-resolution microscope, also known as mIRage and mIRage-LS. In his past roles, he has led the discovery of new applications using tip-based sub-diffraction limited microscopes and resulted in numerous peer-reviewed publications. He has completed and received his doctoral degree in Chemical and Biomolecular Engineering from UCLA.

Abstract:
Improving yields in the manufacturing of microelectronic packages has become a progressively important task but also growing increasingly difficult due to smaller and finer feature sizes. Modern advanced packages consist of multiple functionalities toward system-on-chip (SOC) by incorporating multiple known-good dies, high bandwidth memories, and chiplets in an increasingly small complex 3D or even 3.5D packages. To accommodate small packages, feature sizes of interconnects are pushing toward sub-10 µm regime [1], leading to the smallest contamination could potentially jeopardize the operability of the entire device. Since multiple steps and processes are required to prepare each individual chip component, it becomes financially important to ensure integration through interposers and interconnects to be free of defects.

When defects do occur, these small foreign matters are challenging to identify for root cause analysis. After identifying the specific faults through physical failure analysis (PFA), Fourier-transfer infrared spectroscopy (FT-IR) is typically utilized to molecular fingerprint the unknown. This conventional FT-IR technique detects electromagnetic waves that are typically between 2.5 to 20 µm. The infrared wavelengths employed in the FT-IR microscopes are much too long to effectively resolve those sub-10 µm foreign contamination and particles [2,3]. Certainly, Raman microspectroscopy has been the go-to alternative that can offer spatial resolution for resolving those sub-10 µm organic defects, but the inherently strong fluorescence nature of many resins and chemicals used in the manufacturing of microelectronics shunts the benefits of Raman microspectroscopy.

To overcome the abovementioned challenges, a novel type of infrared-based microscope taking advantage of detecting localized infrared-absorption induced photothermal effects using a visible laser source, namely optical photothermal infrared or O-PTIR [4,5] has been developed to provide high spatial resolution and sensitivity to remedy aforementioned challenges in conventional analytical techniques. This instrumentation simultaneously illuminates a constant wave visible laser and a pulsed wide-tuning laser in the mid-IR. This visible laser is typically equipped at 532 nm, the theoretical spatial resolution of O-PTIR would also be in the submicron regime (<1 µm). The IR laser’s pulse width is a few hundred nanoseconds and repetition rate is about 100 kHz. When the material absorbs the IR wave, the material would heat up, leading to photothermal expansion and an instantaneous change in the refractive index. These phenomena are referred to collectively as photothermal effect, which would bend the constant wave visible laser, leading to the deflection of it relative to when the IR laser is in the off state [Fig. 1]. Since the photothermal effect is due to the IR absorption of the unknown, the resulting infrared spectra reflects its native IR absorption profile, such that we can directly searched and compared with commercially identified infrared databases.

Using this new method, identification of unknown of sub-5 µm contamination can be accomplished. In this contribution, we will briefly explain the fundamentals of submicron IR (O-PTIR) and conclude with an example illustrating the capabilities of O-PTIR toward analyzing contamination in between a sub-5 µm gap between metal leads (Fig. 2) with high signal to noise (Fig. 3), thus leading to confident identification of the unknown material.

 

Bio:
Mr. Ting-Wei Chen is an engineer who works in the NMC department at TSMC, specializing in advanced packaging within the semiconductor industry. Throughout his career, Mr. Chen has demonstrated a strong understanding of the carrier wafer process and has helped develop new processes and technologies that improve carrier wafer process stability and reliability.

Abstract:
ABSTRACT
The rapid progression of advanced packaging technologies is being driven by the growing demands of high-performance computing (HPC) applications. To meet the increasing complexity of HPC workloads, innovative packaging solutions such as 2.5D and 3D integration, chiplet architectures, and heterogeneous integration are being actively explored. However, these advancements introduce significant manufacturing challenges. In 2.5D and 3D packaging, carrier wafers play a critical role in supporting wafers throughout complicated processes including etching, thermal curing, lithography, and grinding. A key function of the carrier wafer is to minimize wafer warpage, ensuring precision in steps such as lithography and grinding.
The material selection of carrier wafer is crucial, requiring properties such as transparency, low surface roughness, and bulk defects-free (like voids or cracks) and chemical resistance. These carrier wafer qualities are essential for reliable performance at temporary bonding and subsequent processing stages. To ensure the quality of carrier wafer, this paper proposes an Advanced Optical Metrology (AOM) to monitor physical properties of carrier wafer, including transmittance, surface roughness, and bulk defects.
The AOM has been successfully validated on 12-inch transparent carrier wafer, providing comprehensive data on transparency, surface morphology, and bulk defects within one minute of measuring time. The validation was further confirmed by cross-checking results with other inspection instruments. The demonstration cases show that AOM offers a fast, reliable, and efficient solution for quality monitoring of carrier wafer, addressing the critical needs of advanced packaging processes in HPC applications.

 

Bio:
Education: 2011 Master of mechanical engineering department, National Chung Hsing University (NCHU), Taiwan. Experience: Over 14 years of job experience on semiconductor industry, especially focus on flip chip, Package on package (PoP), SiP (System in Package), CoWoS and Fan-out solutions of advanced assembly technology for mobile computing, IoT and networking market application. Mike is focus on new assembly package & new technology development. He has been exploring the product application strategy, package technology promotion, new project engagement.

Abstract:
Major semiconductor market applications require HPC, Cloud, Autonomous Car and Generative AI to get better daily life. When large scale expansion requirement from each application, we will receive a large amount of data which will be generated in the computing process by efficiently transmitted, calculated and stored. In recent years, the demand for data transmission in large data centers and cloud servers. Industrial networking countries have been driving into the optical communication field, by using "optical light" instead of "electrical" as the carrier during data transmission. The major benefits for optical communications can improve the transmission capacity, bandwidth, power efficiency to increase data bandwidth and reduce electricity energy consumption. However, the current networking server are using the traditional pluggable transceiver method, but power consumption is a major concern. Therefore, in order to overcome these challenges and achieve higher bandwidth and faster data processing needs, a "Co-packaged Optical" (CPO) packaging solution was developed to improve power and better bandwidth. The CPO product combined EIC (Electronic Integrated Circuit) and PIC (Photonic Integrated Circuit) with optical waveguides design into OE (Optical Engine) module and integrated switch chips and multiple OE modules into single package integration. In this paper, we see different OE structures (EIC/PIC) by horizontal and vertical integration methodologies, and use fan-out embedded with RDL, 3D TSV die stacking and hybrid bonding technologies to integrate EIC/PIC function into OE module. The FAU (fiber array unit) will use optical passive/active alignment method to put on waveguide area of PIC with grating coupling (GC) and edge coupling (EC) solutions. Both of electrical performance and thermal performance are major challenges for OE solutions. Compared with electrical performance by insertion loss and verify die thickness of thermal performance simulation. We also demonstrated the Fan-out CPO (FO-CPO) structure warpage challenge and assembly solutions during wafer level bonding and package level bonding to get better warpage control result. Finally, this paper will provide the advanced CPO and OE technology solutions for the next generation networking and HPC markets.

 

Bio:
Darko Grujicic, Ph.D. is a Principal Engineer at Intel's Advanced Packaging Technology Manufacturing organization. He received his bachelors degree from the University of Belgrade and his Ph.D. in Materials Science and Engineering from the University of Idaho. For the last twelve years at Intel, he has been working on development and manufacturing of advanced packaging solutions, including EMIB, EMIB-T and glass core and carrier packaging solutions, responsible for seed deposition and etch. He holds 10 awarded patents, and numerous peer-reviewed journal publications.

Abstract:
This paper presents the study of chemical copper seed etching in panel-level substrate packaging application for redistribution layers, utilizing equipment with the novel fluid reactor design. The main challenge in removing the copper seed for fine-line spacing redistribution layer interconnects is preserving the dimensions of the interconnects, while ensuring complete removal of the seed copper to prevent shorting between the interconnects. This prompted the need for a novel reactor design that can meet these requirements for fine-line interconnects with the width of 2um and below. Components of the reactor were designed by applying Computational Fluid Dynamics (CFD) modeling. These concepts comprise modelling of two-phase flow combined with the Discrete Phase Model (DPM) method and fluid film development on the panel surface to simulate solution flow on the panel surface. Additional control of the etch process is enabled by implementing the end-point detection system, so that the etch process can account for the incoming seed thickness variation and adjust the etch duration appropriately. The platform has flexibility to incorporate different chemical modules, incorporating titanium etch module for sputtered seed application. The platform, with some modifications, can be extended to other wet processes in the semiconductor packaging (e.g. photoresist develop and strip, bulk Cu etch, photoresist stripping using solvents, etc…) making it a universal platform with many potential uses.
The results in this paper demonstrate the capability of the reactor to remove copper seed between the copper electrical traces, without affecting the trace profile by over-etching the traces, using commercially available copper etch chemistry. The traces, defined by optical lithography in photoresist are biased to 2.4 um, and electrolytically plated on a 250 nm copper seed to a 3um thickness. Profilometry measurements and cross-sectional SEM images post etch indicate that the top and sides of the trace are etched at the same rate as the seed, resulting in a 2 um wide trace with a uniform rectangular profile.

 

Bio:
will be updated later

Abstract:
Heterogeneous integration enhances functional density by incorporating multiple chips or components into a single package. This integration increases the overall package size, posing challenges for dimensional stability. A promising solution is the use of new materials like glass, which offers exceptional flatness and dimensional stability. Achieving inclusion-free filling of high aspect ratio (HAR) through glass vias (TGVs) is crucial for improving the performance and reliability of advanced electronic packaging.
This study investigates the application of pulse reverse electroplating (PRE) to achieve defect-free copper electroplating in HAR TGVs. Defect-free filling of HAR TGVs is essential for the performance and longevity of advanced electronic devices. The PRE technique, which employs alternating current pulses combined with advanced DC electroplating processes, theoretically prevents the formation of inclusions and voids, ensuring excellent bridging and superconformal filling even in challenging structures.
Our findings suggest that the PRE method can provide inclusion-free filling for specific through-hole dimensions, as supported by theoretical ideas and plating examples. Additionally, our recent investigations support the theory of an influence of cuprous ions on the TGV filling mechanism, which could further optimize the electroplating process. Cuprous ions play a significant role in the electrochemical reactions occurring during the PRE process, impacting the deposition quality and uniformity. Understanding this influence allows for better control over the electroplating parameters, leading to improved filling results.
Another filling mechanism, previously published by our group [1], is also considered. This mechanism is based on the differential de- and re-adsorption of various additives at specific phases of the pulse scheme. These additives interact with the copper surface during the electroplating process, affecting the behavior and distribution within the TGVs. By carefully managing the adsorption and desorption cycles, it is possible to achieve more uniform and defect-free filling, enhancing the overall performance and reliability of the electronic packaging.
The theoretical data highlights PRE's potential to enhance structural integrity and improve thermal and electrical conductivity. The inclusion-free filling achieved through PRE not only improves the mechanical stability of the package but also enhances its thermal management capabilities, which are critical for high-performance electronic devices. The improved electrical conductivity ensures efficient signal transmission, reducing losses and enhancing the overall functionality of the device.
Future research will focus on refining these processes to accommodate diverse structure dimensions, further enhancing their reliability and versatility. By refining the techniques and exploring new combinations of electroplating methods, including testing new in-house synthesized molecules with tailored electrochemical performance, we aim to further enhance the versatility and reliability of HAR TGV filling processes to meet the evolving demands of advanced electronic packaging. These efforts will contribute to the development of more robust and efficient packaging solutions, capable of supporting the next generation of electronic devices.

 

Bio:
Ling-Hua Wang Worked at Advanced Semiconductor Engineering, Inc., Kaohsiung, Taiwan six years as Supervisor Participated PLCSP, FO/ FX, FOMCM, FOCoS-B device research and development Responsible Molding process including EQP and materials research and development Concurrently Recon team integrated

Abstract:
The packaging purpose of semiconductor is in order to protect chip and transfer electronic single. In packaging fan-out process, the size are 8 inch, 12 inch wafer and 600x600mm panel, more to achieve the 700x700mm panel which is as the large-Size. They are produced with the more hardly and challenge in the process. Large panel FO development is advance assembly technology. It’s a High-end Technical and also a Aggressive Cost Model in the OSAT (Outsourced Semiconductor Assembly and Test). Mold EMC filling methodology different between Wafer level and Panel level. The Incomplete molding filling improved is requirement on large panel molding. Molding filling is on large panel molding size. EMC background (1) : for hollow filler issue improved Filler size is changed. Filler size: 55um to 20um. EMC background (2) : for hollow filler issue improved. Spiral flow property difference. Spiral flow: 102cm to 88cm. Incomplete fill exist due to lower spiral flow

 

Bio:
Weiming Cheng is a Senior Manager of Business Development at MKS|ESI, leveraging over 23 years of expertise in the FPC, PCB/HDI,and IC Substrate markets to integrate New Product Introduction (NPI) with strategic market expansion. During his 15-year tenure at Unimicron, he demonstrated comprehensive R&D, strategic marketing, process and production capabilities, notably scaling facilities for volume readiness across advanced packaging substrate platforms (CSP, FCCSP, FCBGA). In PCB segment, he led new market penetration into high-growth applications like SiP, Automotive, and mSAP-HDI. Mr. Cheng holds 45 granted PCB/HDI and IC substrate patents and possesses dual Master's degrees in Engineering and Management.

Abstract:
Technological advancements in the integrated circuit (IC) package market, driven by the proliferation of mobile devices and artificial intelligence (AI) servers, have led to several key trends. These include increasing design complexities and package dimensions, heightened routing densities, miniaturized lines and spaces, and a corresponding reduction in the size of laser-drilled microvias. Consequently, the dry film solder resist (SR) materials employed in the outermost layer of these advanced IC package substrates must exhibit exceptional performance reliability. This is crucial for enduring the amplified mechanical stresses arising from coefficient of thermal expansion (CTE) mismatches between various IC package substrate constituents, such as capillary underfill materials, solder, copper (Cu), and interlayer insulation materials, as well as overall substrate warpage in upcoming larger and larger package formats. Furthermore, the continuous increase in routing densities necessitates superior insulation integrity in fine-line and -space configurations and an enhanced capability to stably produce smaller microvias with finer pitches, a demand that has grown significantly year over year.

 

Bio:
Hsin-Lin is a master’s student in the Department of Materials Science and Engineering at National Yang Ming Chiao Tung University. Her research focuses on Ni-doped nanocrystalline copper for low-temperature Cu-Cu bonding in advanced semiconductor packaging.

Abstract:
The semiconductor industry is rapidly advancing toward fine-pitch interconnects and integration of chips through 3D stacking technologies, such as through silicon vias (TSVs) and hybrid bonding. These approaches enable higher performance, reduced latency, and compact form factors critical for AI accelerators, high-bandwidth memory (HBM), and other high-growth applications. Achieving bonding at low temperature has become a critical requirement, particularly for copper-to-copper (Cu–Cu) bonding. Conventional Cu–Cu bonding processes typically demand high temperatures (≥300 °C) to enable sufficient atomic diffusion and grain growth across interfaces. However, such elevated temperatures can damage low-k dielectrics and induce warpage, and limit compatibility with backend-of-line (BEOL) processes. To overcome these limitations, this study explores the use of nanocrystalline copper doped with trace amount of nickel as a promising solution for achieving strong interfacial bonding at reduced temperatures.
Nanocrystalline copper, defined by its ultra-fine grain structure (grain size <100 nm), exhibits a high density of grain boundaries, which serve as fast diffusion paths. These features enhance atomic mobility and bonding efficacy even under reduced thermal conditions. To further improve bonding performance, trace element doping, specifically with Ni was employed. Ni doping was found to influence grain boundary energy, suppress abnormal grain growth, and enhance the thermal stability of the Cu films.
In this study, Ni-doped nanocrystalline copper films were fabricated by co-electroplating under controlled conditions to ensure favorable grain structures and uniform distribution of dopants. By varying the dopant concentration, we achieved tunable grain size and diffusivity, enabling tailored bonding behavior. Additionally, we annealed the films at 150°C for 2 hours and compared the microstructure before and after to evaluate the thermal stability, which is essential for integration into industrial manufacturing flows. Thermal compression bonding was performed at 200 °C for 1 hour in a vacuum environment. The microstructural characterization before and after bonding was carried out using electron backscattered diffraction (EBSD), focused ion beam (FIB), and EDAX OIM analysis to examine grain size, orientation and cross-section analysis. Electron probe microanalysis (EPMA) was used to assess Ni dopant distribution and concentration. In addition, shear tests were conducted to determine the mechanical strength and quality of the bonding interfaces.
The results show that Ni addition effectively refines grain size and enhances bonding performance. With increasing Ni content, grain size consistently decreased within the studied range, leading to improved interfacial contact and mechanical strength. Compared to conventional Cu bonding, Ni-doped nanocrystalline copper significantly improved bonding strength and interface integrity, even under low thermal budgets. These findings suggest that Ni-doped nanocrystalline copper is a promising material for next-generation fine-pitch and low-temperature bonding applications in advanced semiconductor packaging.