Sessions Index

Bio:

Hirokazu Ito received the M.S. degrees in applied chemistry from Hokkaido University, and joined JSR Corporation in 2008. He also worked in 3D Systems Packaging Research Center in Georgia Tech as a Visiting Researcher from 2017 for two years. He has engaged in development of photo imageable dielectrics and photoresist.

Abstract:

In this session, we mainly discuss photosensitive polyimide material required for re-distribution layers (RDLs) in next generation interposer. As increase the demand of high-density interconnect on interposer, stable process of fine pitch Cu traces less than 2µm-L/S is a key technology. However large topology which comes from large polyimide shrinkage through curing causes some technical issues on photoresist lithography for plating. In addition, CTE mismatch between polyimide and Cu is a potential reliability concern especially in larger packaging. Therefore, retaining low CTE at high temperature, namely high Tg, becomes important. From these prospective, JSR newly developed photosensitive polyimide enabling high resolution with an aspect ratio of 2.0 or more, low shrinkage around 10%, low CTE and high Tg simultaneously. We also demonstrated reliability performance including the biased-HAST by multi-layer stacking structure with 2 µm-L/S Cu traces. These unique properties and reliability data indicate that the newly developed photosensitive polyimide is a promising material for RDLs in next generation interposer. We also touch on the topics of fine pitch patterning photoresist for plating.

 

Bio:

Shaw Fong currently serves as the Principal Engineer at one of the Kulim Campuses of Intel Malaysia. With ~24 years of extensive experience in the semiconductor industry, he has held various positions that encompass a wide range of technical domains including packaging processes, assembly, testing, and material technology development. Throughout his career, Shaw Fong has played a pivotal role in advancing multiple packaging and product development initiatives, with a particular focus on warpage development and mechanical testing. His technical acumen and leadership have significantly contributed to innovative solutions and improved efficiencies within these critical areas.

In 2023, Shaw Fong was honored with the prestigious IEEE/EPS William Chen Distinguished Award, recognizing his significant contributions to the IEEE in driving advancement in semiconductor assembly and testing field. He has been nominated to the IEEE/EPS Board of Governance and serves as Region-10 Program Director. He is also engaging in IEEE Malaysia Section as the Executive Committee (Industrial Relations). Additionally, he is an active Committee Member of both the Electronic Engineering Technical Division (eETD) and the Material Engineering Technical Division (MaTD) of the Institution of Engineers Malaysia (IEM). His recent designation as a Professional Engineer by the Malaysia Board of Engineers (BEM), along with his advisory roles with various local universities, underscores his unwavering commitment to engineering excellence and education. Shaw Fong holds a total of 12 combined patents and trade secrets, and he is a key driver of technical innovation at Intel Malaysia, having achieved over 90 technical publications. Outside of his professional endeavors, Shaw Fong is a devoted family man with two sons and a passionate sports enthusiast, particularly in football, where he proudly supports Liverpool FC.

Abstract:

The IEEE Electronics Packaging Society (EPS) plays a pivotal role in advancing microelectronics and packaging technologies globally. This session aims to introduce the IMPACT community to the mission, structure, and strategic initiatives of IEEE EPS, with a focus on Region-10 (Asia-Pacific). As the semiconductor industry shifts toward heterogeneous integration and system-level innovation, EPS offers a robust platform for collaboration, knowledge dissemination, and professional development.
At the heart of EPS’s technical leadership is the Heterogeneous Integration Roadmap (HIR), a 15-year vision co-developed with global stakeholders to guide the integration of logic, memory, photonics, and sensors into high-performance systems [1]. This roadmap is not only a technical compass but also a catalyst for regional innovation and policy alignment. Region-10 chapters—including Taiwan, Japan, India, and others—are actively contributing to this vision through conferences, workshops, and chapter-led initiatives. The Malaysia EPS Chapter, for example, has expanded its membership base and hosted key events aligned with the EPS and national strategies [2]. EPS-sponsored conferences provide platforms for cross-border engagement and technical exchange [3].
This presentation will also highlight membership trends, 2025-2026 chapters’ activities, and opportunities for Region-10 collaboration. By leveraging EPS’s global resources and regional networks, we can accelerate innovation, strengthen talent pipelines, and shape the future of electronic packaging in Asia.

 

Bio:

Jenn-Ming Song is the Dean of the office of R&D, and a professor in the Department of Materials Science and Engineering, at National Chung Hsing University in Taiwan. He is also a visiting professor of Osaka University in Japan as well. His research interests encompass semiconductor packaging, advanced interconnect materials, synthesis and applications of nanomaterials, phase transformation and mechanical behavior of advanced materials at bulk and small length scales. He is an Editor for the journal Materials Chemistry and Physics, and serves as the member of editorial advisory board of Microelectronics Reliability. Prof. Song has received several excellence research awards, including the Ta-You Wu Memorial Award from National Science Council of Taiwan and the outstanding research professor award from the Lee Chang Yung (LCY) education foundation.

Abstract:

By minimizing interconnect resistance and improving signal transmission efficiency between stacked dies, metal to metal direct bonding addresses key challenges in next-generation semiconductor systems, such as power delivery, data bandwidth, and form factor reduction. In addition to thermal compression, ultrasonic technique has been suggested to achieve bonding between Au, Al, Cu and In, due to the advantages of short processing time, and the elimination of the need for vacuum and additional intermediate materials, such as solders or adhesives. An innovative and efficient surface modification pre-treatment that enhances direct metal bonding through electromagnetic irradiation, including pulsed Xenon flash, near infrared rays and short wavelength UV lights, has been proposed by our research group. Without vacuum, short period but critical electromagnetic radiation exposure on faying faces prior to bonding can significantly improve the joint strength up to 50% or even more. In addition to hydrophilic surface ligands, atom diffusion acceleration by increased compressive residual surface stresses resulting from sudden heating/ cooling accounts for the joint reinforcement. A close relationship between the increase in joint strength and the change in surface physics and chemical properties due to electromagnetic irradiations will be reported.

Keywords: Light irradiation, Direct metal bonding, Thermal compression, Ultrasonic bonding, Surface properties

 

Bio:

Chuan Seng Tan is a Professor of Electronic Engineering at the School of Electrical and Electronic Engineering at Nanyang Technological University, Singapore. He received his PhD from MIT in 2006. Currently, he is working on process technology of three-dimensional integrated circuits (3-D ICs), as well as engineered substrate (Si/Ge/Sn) for group-IV photonics. He has numerous publications (journal and conference) and IPs on 3-D technology and engineered substrates. Nine of his inventions have since been licensed to a spin-off company. He co-edited/co-authored five books on 3D packaging technology. He is a Fellow of IEEE (Class of 2022) and a recipient of the Exceptional Technical Achievement Award from the IEEE Electronics Packaging Society (EPS) in 2019. He was a Distinguished Lecturer with IEEE-EPS from 2019-2023. He is a Fellow of the International Microelectronics Assembly and Packaging Society (IMAPS) since 2019 and a recipient of the William D. Ashman - John A. Wagnon Technical Achievement Award in 2020.

Abstract:

Increasingly, enhancements in system-level performance are being complemented by functional diversification. In this talk, we present our recent work on engineered substrates (X-OI) and advanced packaging techniques—including through-silicon vias (TSVs) and wafer bonding—to advance this dual objective. We will highlight several key demonstrators, such as GaN-LED integration on silicon CMOS, ion-trap architectures on silicon interposers, and our latest proposal involving triple integration of optics, III-V optoelectronics, and silicon technologies.