Sessions Index

Bio:

Majored in mechanical engineering at Oklahoma State University. After graduation, joined Yaskawa Electric Corporation, where he was engaged in both technology development and business planning. In 2024, he joined Elephantech Inc. and was appointed Manager of the Business Development Division. He is currently focused on promoting next-generation PCB manufacturing technology, based on additive processes using inkjet technology and nanomaterials, with a particular emphasis on its potential for the semiconductor industry. His areas of expertise are the commercialization of new technologies and their application development within the semiconductor industry.

Abstract:

The electronics industry faces growing pressure to reduce its environmental footprint and improve resource efficiency. Conventional subtractive manufacturing processes, which are dominant in both PCB and semiconductor fabrication, lead to significant material waste and high energy consumption.

We introduce a revolutionary additive manufacturing process developed by Elephantech, which utilizes AI-powered inkjet technology and proprietary nanomaterials. Our technology has been successfully applied to PCB production, where it has demonstrated a remarkable reduction in material waste by over 95% and a decrease in CO2 emissions by more than 75% compared to traditional methods.

Based on these advancements, we believe our technology holds significant potential for addressing specific challenges and enabling new functionalities in the semiconductor industry.

We will share our experience and key insights gained from low-carbon PCB manufacturing. Our presentation will highlight how an additive, resource-efficient approach, already successful in the PCB field, could contribute to a more sustainable and innovative future for semiconductor manufacturing

 

Bio:
I pursue my bachelor's degree in Mechanical Engineering, University Malaya. I worked for 2 years in TF-AMD, a semiconductor packaging company in Penang, Malaysia as a process engineer in the underfill process. Now I am pursuing my master's degree in NCKU to specialize in the semiconductor industry.

Abstract:
The demand for high-power semiconductor devices continues to grow, driving the scaling of node sizes to accommodate a greater number of transistors within a single package. Cu is a commonly used material in semiconductor devices due to its excellent electrical conductivity and is employed in structures such as interconnects and Cu pillar bumps for solder joints. These structures experience mechanical loading during service. In Cu pillar structures, thermomechanical fatigue caused by the coefficient of thermal expansion (CTE) mismatch is a known reliability issue. However, the additional influence of electric current on Cu’s mechanical behaviour at the microscale remains insufficiently understood.

To address this, we employed micropillar compression, a technique capable of capturing uniaxial stress–strain behavior with crystallographic specificity at the microscale. Unlike nanoindentation, which provides modulus and hardness values, micropillar compression enables direct insight into elastic–plastic transition, strain bursts, and deformation mechanisms relevant to microbump reliability in 3D integrated circuits. Cu micropillars with diameter of 6µm and height of 15 µm were fabricated on a <111>-oriented single-crystal Cu substrate using focused ion beam (FIB) milling. Compression tests were conducted using a flat punch nanoindenter integrated with an electrical characterization module (ECM) inside a scanning electron microscope (SEM), allowing simultaneous application of mechanical stress and electric current. During compression, a displacement controlled programmed is used, with a strain rate of 3 × 10-3. The electric current density applied ranges from 0 to 4 × 103 A/cm2 .

The results show that the flow stress increases with current density, indicating electric current-induced strengthening in Cu. Post-compressed characterization using transmission electron microscopy (TEM) and transmission Kikuchi diffraction (TKD) revealed microstructural features linked to dislocation activity, offering insight into the underlying electromechanical deformation mechanisms.

 

Bio:
Currently a Ph.D. student in the Semiconductor and Green Technology Program at National Chung Hsing University, with research focusing on intermetallic compounds, nanoindentation, and nanoparticles.

Abstract:
In semiconductor packaging, the mechanical and structural characterization of interfacial intermetallic compounds (IMCs) is essential for assessing joint reliability. With ongoing technology scaling and structural miniaturization, nanoindentation has emerged as an effective technique for evaluating the mechanical properties of materials at the nanoscale. In this study, nanoindentation was employed to characterize the mechanical behavior of commonly observed IMCs in solder joints, and the correlation between the nanomechanical responses and solder joint performance was systematically investigated. The plastic deformability of IMCs is described by the ratio of elastic modulus to hardness (E/H), where a higher E/H indicates easier plastic deformation. Results show that E/H exhibits an inverse relationship with the work-hardening exponent (n) but positive correlation with strain rate sensitivity (m). Creep deformation plays a critical role under high-temperature operating conditions. Creep test results reveal that E/H is inversely related to the creep stress exponent (CSE), suggesting that IMCs with lower E/H exhibit better creep resistance. Furthermore, in high-speed ball shear testing the impact energy of solder joints was found to scale proportionally with the E/H value of the interfacial IMC. These findings demonstrate that mechanical behavior of IMCs dominates joint performance under various strain rate conditions. By controlling E/H values of IMCs, joint reliability can be further optimized from the aspect of material design.

 

Bio:
Master’s student in Professor Jenn-Ming Song’s Laboratory, Department of Materials Science and Engineering, National Chung Hsing University, focusing on direct bonding research for advanced semiconductor packaging.

Abstract:
By minimizing parasitic interconnect resistance and improving signal transmission efficiency between stacked dies, Cu-to-Cu bonding addresses key challenges in next-generation semiconductor systems, such as power delivery, data bandwidth, and form factor reduction. Its compatibility with low-profile, high-density integration makes it particularly suitable for AI accelerators and mobile devices. However, a key barrier to achieving high-reliability Cu-Cu bonding lies in the native oxide layer that inevitably forms on copper surfaces upon air exposure. Even at nanometer-scale thickness, this oxide can significantly hinder atomic diffusion across the bonding interface. This increases the required thermal budget and bonding pressure, and introduces risks such as void formation, warpage, or interfacial delamination—especially in thermally sensitive packaging environments. To address this challenge, we investigated the oxidation behavior of copper thin films under low-temperature thermal conditions (120°C). Constant-current coulometric reduction was employed to detect and quantify surface oxide layers. These results were cross-validated using X-ray photoelectron spectroscopy (XPS), Kelvin probe force microscopy (KPFM), water contact angle analysis, and atomic force microscopy (AFM). The integrated dataset enabled us to construct a detailed profile of oxide evolution and growth mechanisms under thermal oxidation. Shear tests of Cu t0 Cu direct bonded joints reveal that even relatively thin oxide layers (<10 nm) could cause a steep drop in bonding strength—from above 30 MPa to below 10 MPa—highlighting the extreme sensitivity of Cu-Cu interfaces to early-stage oxidation. Interestingly, the formation of a small amount of hydrophilic CuO was found to temporarily suppress strength degradation by improving wettability and interfacial contact.
Keywords: Cu-to-Cu bonding, Surface oxide, Thermal oxidation, Coulometric reduction, Bonding strength

 

Bio:
Academy of Circular Economy, National Chung Hsing University, Taichung 402, Taiwan

Abstract:
In 3D integrated circuits (3D ICs), vertical chip stacking relies on through-silicon vias (TSVs) filled with electroplated copper to achieve interconnection. As the bonding interface is composed of Cu–Cu, the bonding quality plays a decisive role in determining the overall reliability of the package. However, native oxide layers readily form on copper surfaces, which can hinder atomic diffusion and bonding integrity, making precise characterization of these oxides essential for process optimization. This study proposes a rapid and quantitative electrochemical method for analyzing both the thickness and phase composition of copper oxide layers. By applying constant current cathodic reduction and utilizing Faraday’s law, the oxide layer thickness can be accurately calculated. Moreover, by defining the redox potential ranges of CuO and Cu₂O, the thickness of each oxide phase can be separately estimated, thus improving the precision and efficiency of the evaluation. To validate the results, X-ray photoelectron spectroscopy (XPS) was systematically employed. The proportions of CuO and Cu₂O were determined by comparing the Cu 2p₃/₂ and Cu LMM signals, and the oxide thickness was estimated using the Beer–Lambert law. Depth profiling with XPS was also performed to observe variations in elemental signals along the thickness direction, confirming phase distribution across the oxide stack. Atomic force microscopy (AFM) and α-step profilometry were used to assess the changes in surface morphology and roughness before and after oxidation and electrochemical reduction, providing surface feature information related to the formation and removal processes of the oxide layers. This integrated analysis framework enables multidimensional and complementary validation of copper surface oxidation and reduction behaviors, contributing to the reliability of future microelectronic interconnect technologies.
Keywords: Cu–Cu bonding, copper oxide, oxide thickness, electrochemical reduction, XPS analysis

 

Bio:
SPIL substrate eng DEPT. technical manager

Abstract:
In recent years, with the popularization of cloud services, the application of generative AI and data analysis has become increasingly widespread. The trend of mobile offices or micro-desktop workstations has increased. The market demand of high-performance SoC is not limited to desktop computers. It Has gradually expanded to portable personal computers, such as a tablet or laptop. How to pursue high performance while consideration of thin and light design requirements is not just a subject in IC design, it also broke the previous technological development trend for IC carrier product platforms. While Flip-chip ball grid array (FCBGA) product design pursues large size and multiple layers, it also needs to consider how to reduce the overall thickness.
IC substrate is comprised of multi materials, of which the core layer accounts for 50~80% of the overall thickness (depending on the number of layers designed). If the core layer can be reduced or even removed it to create a coreless structure. Not only can the thickness of the base be significantly reduced, but also increase design flexibility, to remove the useless layers such as the bottom layer on a cored substrate, and achieve better electrical characteristics, due to reduce the loop inductance.
Although the thin core and coreless structures have been widely used in existing Flip-chip chip scale package (FCCSP) product technology; but FCCSP product designs are mostly small-sized and low-layer designs, and the dielectric material used is Prepreg which containing fiberglass cloth inside and able to provide rigidity. In contrast, FCBGA product designs are mostly large-sized and high layer count, thus the dielectric material used chose build-up film, hereinafter referred to as ABF, which does not contain fiberglass cloth. Whether it is reducing the thickness of the core or removing the core to create a coreless structure, the warpage performance of the FCBGA substrate is a big challenge.
Based on the above considerations, we expect to find a feasible substrate structure and suitable dielectric materials through this study. Considering the compatibility with FCBGA production line equipment, we selected two structures, 5/2/5L 0.15mm core and 12L coreless, for ultra-thin FCBGA structure verification. In addition, in the selection of dielectric materials, we also considered another ABF materials which containing glass fiber, also known as ABF-GCP (Glass Cloth with Primer), to enhance the rigidity of the dielectric materials. Due to the glass fiber will increase dielectric layer thickness, we only replaced two layers of ABF with ABF-GCP to keep the thin design requirements as posable and compare the warpage performance between pure ABF and hybrid dielectric (ABF/ABF-GCP).

 

Bio:
My name is Hao-Wei Kuo, a second-year master's student in the Department of Mechanical Engineering at National Cheng Kung University. My research focuses on low-temperature solders, particularly Sn-In alloys, which show great potential for use on flexible substrates. With a strong interest in this field, I am eager to further explore the development of these materials, which has motivated me to pursue a Ph.D. I sincerely hope to continue this journey successfully.

Abstract:
With the rapid development of flexible electronics, the demand for low-temperature solders has grown, especially for polymer substrates that are easily damaged above 150 °C. Traditional Sn–Bi alloys, despite their low melting point, suffer from brittleness, limiting their application. In contrast, Sn–In alloys offer better ductility but lack sufficient mechanical strength. For instance, the Vickers hardness of eutectic Sn–52wt.%In alloys is less than 10 HV, indicating their softness. To improve performance, previous studies introduced third elements such as Cu, Ag, and Zn. While some properties improvement was observed, the effects of multiple additions remain unclear due to system complexity. Therefore, this study adopts a machine learning model to efficiently explore and optimize multicomponent Sn–In–X alloys. Recently, machine learning methods have been proposed as a promising approach for new material design. A Vickers hardness database was established for alloys containing Cu, Ag, Zn, Bi, Sb, Al, and Ni. A Gaussian Kernel Ridge Regression (GKRR) model was trained using this dataset, and a genetic algorithm (GA) was integrated for inverse design. This framework enables efficient screening of alloy compositions targeting desired hardness levels. Candidate alloys were synthesized and experimentally confirmed, demonstrating the model’s predictive capability. The designed SIX5 (Sn–In–X) alloy exhibited approximately three times the hardness and more than double the tensile strength of conventional Sn–52wt.%In, confirming its significantly enhanced mechanical performance. This research demonstrates an effective framework combining machine learning and thermodynamic modeling to accelerate the development of advanced low-temperature solders for packaging and flexible electronics.
Keywords: low-temperature solder, Sn-In alloys, machine learning, hardness, tensile properties.