Sessions Index

Bio:

Ricky Lee received his PhD degree in Aeronautical & Astronautical Engineering from Purdue University in 1992. After one year of post-doctoral research at Purdue, he joined the Hong Kong University of Science & Technology (HKUST). During his career of tenure-track faculty at HKUST, Dr Lee once was on secondment to serve as Chief Technology Officer of Nano & Advanced Materials Institute for two and a half years. Currently Dr Lee is Chair Professor of Smart Manufacturing Thrust and Vice-President (Research) at the HKUST Guangzhou Campus (HKUST(GZ)). Dr Lee has been focusing his research on the technology development for electronics/optoelectronics packaging and additive manufacturing. The topics of his R&D interests include wafer level packaging and heterogeneous integration, 3D printing for microsystems packaging, LED packaging for solid-state lighting and applications beyond lighting, lead-free soldering and reliability analysis. The research outcomes of Dr Lee’s group have been documented in numerous technical papers in international journals and conference proceedings. He also co-authored 4 books and 10 book chapters. Due to his technical contributions, Dr Lee received many honors and awards over the years. In addition to being the recipient of 15 best/outstanding paper awards and 8 major professional society awards, Dr Lee is Fellow of IEEE, ASME, IMAPS, and Institute of Physics (UK).

Abstract:

Driven by booming generative and Agentic AI, global AI market scale is projected to surge tenfold by 2033, yet a critical structural bottleneck emerges: computing performance triples biennially while interconnect bandwidth only rises 1.4 times, rendering traditional copper electrical interconnection incompetent due to low bandwidth, severe signal attenuation and excessive power consumption. The industry thus enters a “fiber replaces copper” transition, evolving through four optical interconnection schemes: pluggable optics, LPO, transitional NPO, and ultimate CPO. By co-packaging switch ASIC and optical engines (PIC & EIC) on shared substrates, CPO shortens electrical traces to millimeter scale, slashing power consumption by over 30% and delivering unmatched bandwidth density and ultra-low latency. Its packaging technologies advance from 2D/2.5D heterogeneous integration to high-end 3D hybrid bonding targeting monolithic EPIC fusion. Covering upstream optical materials, midstream silicon photonics and advanced packaging, and downstream AI supercomputing, cloud data centers and HPC clusters, CPO will see accelerated mass production from late 2026. From an investment perspective, primary and secondary market institutions have fully deployed the whole industrial chain, as CPO fundamentally reconstructs AI network node hardware architecture and underpins upper-layer AI tracks such as world models, presenting long-term trillion-dollar industrial and investment value

 

Bio:
Masaaki Koganemaru was born in Fukuoka, Japan, in 1968. He received a Bachelor of Engineering degree in Nuclear Engineering and a Master of Engineering degree in Science and Engineering from Kyushu University in 1992 and 1994, respectively. He earned a Ph.D. in Mechanical Engineering from Kyoto University in 2008. From 1994, he worked as a researcher at Fukuoka Industrial Technology Center in Kitakyushu, Japan. In 2016, he became an Associate Professor at Kagoshima University. Since 2025, he has been serving as a Professor at Kagoshima University. His research interests include device simulation of strained-silicon MOSFETs and stress or strain measurement in electronic packages.

Abstract:
Evaluating the deformation behavior of semiconductor chips and molded resin packages during assembly processes and device operation is essential for optimizing packaging structures and improving overall reliability. Mechanical deformation induced by thermal or operational loading can lead to stress concentration, interconnect degradation, and long-term reliability issues. Therefore, obtaining experimental evidence of real deformation behavior is highly valuable not only for understanding packaging mechanics but also for advancing simulation models and verification methodologies. However, conventional measurement instruments—such as laser displacement sensors and general-purpose interferometers—are limited to point-wise or post-deformation measurements and cannot capture full-field deformation distributions in real time. This limitation has hindered the detailed understanding of transient deformation phenomena that occur during actual device operation.
To address this challenge, we developed a real-time full-field deformation measurement system based on laser speckle interferometry to observe the deformation behavior of chips and packages during assembly and device operation. Laser speckle interferometry offers high spatial and temporal resolution and enables non-contact measurement of displacement distributions on rough surfaces. When laser light illuminates a rough surface, the scattered light forms a speckle pattern consisting of bright and dark spots. By splitting a single laser beam using a half mirror, one beam is directed toward a reference surface while the other illuminates the measurement target. The reflected beams are then superimposed to generate a new speckle pattern. By comparing speckle patterns obtained before and after deformation, interference fringes are produced, from which displacement distributions can be extracted. The developed system consists of a He–Ne laser, a CMOS camera for capturing speckle patterns, a reference surface, and a piezo actuator that precisely controls the position of the reference surface.
Using this system, we conducted real-time measurements of the out-of-plane deformation of a molded resin package during the operation of a USB memory device. The deformation of both the memory package and the controller package was measured while several hundred megabytes of data were written to the device. During the writing process, the surface temperature of the package increased to approximately 50–60 °C, causing measurable out-of-plane deformation. These results demonstrate the applicability and effectiveness of the proposed measurement method for capturing dynamic deformation phenomena that cannot be observed using conventional instruments.
In addition, we introduce an application of the proposed system for measuring the out-of-plane deformation of chips under conditions that simulate the flip-chip assembly process. As chips continue to become thinner, deformation during flip-chip bonding has become a growing concern, as it may lead to mechanical and electrical reliability issues. Therefore, measuring and evaluating chip deformation during the flip-chip assembly process is of significant importance. Real-time deformation monitoring during assembly has the potential to contribute to process optimization, improved bonding quality, and enhanced reliability assessment. Overall, the proposed laser speckle interferometry–based system provides a powerful and versatile tool for real-time, full-field deformation measurement, offering significant potential for advancing semiconductor packaging research.

 

Bio:
Sun-Woo Lee is a Ph.D. student at KAIST, where he has been researching and studying as a member of Advanced Packaging and Thin Film Lab. His current research interests include experimental and computational mechanics of thin film and packaging materials for advanced semiconductors and displays. He received a BS degree in 2021 from Yonsei University, and MS degree in Mechanical Engineering in 2023 from KAIST.

Abstract:
As advanced packaging technologies continue to evolve, one of the most critical challenges lies in ensuring interfacial reliability. Cutting-edge architectures such as 2.5D integration, silicon bridge interposers, and 3D stacking inherently introduce numerous heterogeneous interfaces, which often act as mechanical weak points where delamination can initiate. Such delamination can lead to severe degradation or even catastrophic failure in package performance. Double Cantilever Beam (DCB) and Four-Point Bending (FPB) tests are widely employed to evaluate the adhesion energy of specific interfaces of interest. Various surface treatments and material engineering techniques have been developed to enhance interfacial fracture energy, and the effects of these approaches are typically verified through DCB and FPB testing. These tests are typically conducted under the assumption of a constant phase angle, valid only for homogeneous materials. For instance, the DCB configuration represents a pure Mode I (0°) condition, while the FPB configuration corresponds to approximately 43°. Accordingly, the measured adhesion energy reflects a fixed ratio of Mode I and Mode II fracture components. However, at nano-interfaces, even the extreme thinness of the film, along with elastic modulus and thickness mismatches in adjacent layers such as adhesion or epoxy layers, can significantly shift the actual phase angle during crack propagation. Moreover, variations in the phase angle can alter the most favorable crack kinking direction. When the interfacial adhesion energy is sufficiently high to suppress crack propagation along the interface, the crack may deflect or kink into one of the adjacent nanofilms. To accurately predict this behavior, the elastic properties and thicknesses of both the nanofilms and the surrounding adhesion layers must be considered. To address this issue, a two-step FEA simulation submodeling approach combined with a J-integral sweep method was employed. In conventional DCB and FPB configurations, the silicon beams typically have a thickness of approximately 775 µm, with specimen dimensions of 40 mm in length and 8 mm in width. However, the region of interest where crack propagation and phase angle variation occur exists at the nanometer scale. Therefore, a multiscale (mm–µm–nm) global model was constructed, incorporating locally refined meshes to accurately capture the nanofilm interfaces. In the first submodeling step, a local model around the crack tip was extracted from the global model to obtain the boundary displacements required for subsequent analysis. This was necessary to perform a J-integral sweep, in which a virtual crack was introduced at the interface and rotated over a range of directions from −75° to +75° in 15° increments. The J-integral was computed for each orientation to determine the direction that maximized the energy release rate, which was then identified as the predicted crack kinking direction. However, the nm-scale region directly imported from the global model was found to be too small to maintain stable meshing near the crack tip. To overcome this issue, a scaled-up submodel was constructed. The original submodel extracted from the global model had a characteristic length scale of 10^(-6) (in mm units), which led to severe mesh instability near the crack tip. In the refined submodel, the dimensional scale was adjusted to 10^0 by redefining the base unit from millimeters to nanometers, thereby achieving stable mesh quality while preserving geometric fidelity. The boundary conditions were then mapped from the original submodel by applying a scaling factor of 10^6. This scaling approach enabled virtual crack extension and J-integral sweep analyses to compute the maximum strain energy release rate, from which the crack kinking angle was determined. Using this framework, a comprehensive parametric study was conducted to identify the key factors influencing phase angle and crack kinking direction, particularly the effects of the elastic properties and thicknesses of the nanofilms and adhesion layers. Finally, a machine learning model was developed to establish a functional relationship that enables rapid prediction of phase angle variation and crack kinking direction. The trained model produces a master surface correlating these parameters with the elastic properties and thicknesses of the adhesion layer, allowing users to directly estimate interfacial fracture behavior from material design inputs. In conclusion, the proposed two-step submodeling framework offers a universal method for predicting interfacial crack kinking direction. Beyond DCB and FPB tests, this approach applies to systems with thin-film scale mismatches, providing engineers a practical tool to evaluate fracture mode mixity in interfacial reliability design.

 

Bio:
Hsueh-Chih Liu is now pursuing his Ph.D. degree in Advanced Institute of Manufacturing for High-tech Innovations, National Chung Cheng University. His research interest is focused on the numerical and experimental approach on chip probing mechanical response investigation with vertical probes features.

Abstract:
In recent years, with the rapid advancement of artificial intelligence (AI) technology, the semiconductor testing and inspection industry is experiencing new growth opportunities. It is anticipated that by 2025, the demand for AI servers, high-performance computing (HPC), and application-specific integrated circuits (AI ASICs) will increase significantly, further driving the upgrade of probe card and packaging testing technologies. By utilizing the contact between the probes of the probe card and specific solder pads on the wafer, electrical characteristics of the circuits can be measured, allowing for the assessment of chip yield and the immediate detection of defective chips. In this study, numerical and experimental approaches were employed to analyze the probing mark formation on the aluminum (Al) pad of a silicon (Si) wafer. The test vehicle, a 6-inch Si wafer with PVD Al coating, is shown in Fig. 1(a). The thicknesses of the PVD Al coating and Si wafer are 1.4 μm and 10 μm, respectively, as illustrated in Fig. 1(b). Microchips with dimensions of 0.04 × 0.04 mm² were prepared from the Si wafer for subsequent single probing tests using a Wire-Type needle.

Fig. 1(a) 6-inch Si wafer with PVD Al coating; (b) Detailed dimensions of Si wafer and Al pad.

A finite element (FE) model was developed to simulate the contact phenomenon and mechanical response of a wire-type probe needle with a round radius (RR) tip and an Al pad, as illustrated in Figure 2. The mechanical properties of the wire needle and the Si die were assumed to exhibit linear elastic behavior, with Young’s modulus values of 270 GPa and 170 GPa, respectively. The Al pad was modeled as an elasto-plastic material to investigate the probing mark formation behavior, with its Young’s modulus and yield stress set to 70 GPa and 160 MPa, respectively.

Fig. 2 FEM modeling of vertical wire probe needle and Al pad/Si wafer structure.

The single probing test was performed using a customized fixture and an MTS Acumen electrodynamic test system. The test speed was set to 0.5 μm/s to apply an external overdrive (OD) displacement, simulating actual wafer probing conditions. Following the experiment, the surface profile of the aluminum pad under various probe stroke settings was observed. The resulting probe mark was measured using a Keyence VK-X3000 3D laser confocal microscope, as shown in Fig. 3.
A three-dimensional finite element method (FEM) simulation was performed using the commercial software Abaqus. Figure 4(a) illustrates the established simulation setup, where a spherical probe tip is positioned to indent the aluminum (Al) pad, simulating the actual contact boundary conditions during the test. Upon applying the specified external overdrive (OD) displacement, the resulting displacement distribution on the Al pad was obtained. As shown in the displacement magnitude contour in Figure 4(b), the maximum displacement is concentrated at the center of the contact zone, aligning with the spherical profile of the probe tip. Figure 5 presents a comparison of the probe mark width and depth between the experimental data and the FEM simulation results. The comparison reveals that the FEM simulation successfully captures the overall trend of the deformation, particularly the increase in depth b as the overdrive displacement escalates. Furthermore, the close agreement in depth at the higher overdrive (OD 200) demonstrates that the proposed FEM model serves as a reliable tool for predicting the mechanical response and pad damage during the wafer probing process.

Fig. 3 Measurement of Probe mark by laser confocal microscope Keyence 3D VK-X3000.

Fig. 4 FEM simulation setup (a) and the resulting displacement contour of the probe mark on the Al pad (b) under overdrive (OD) conditions

Fig. 5 Comparison of probe mark width a and depth b between (b) experimental data and (c) FEM simulation results, based on the definition shown in (a).

 

Bio:
Shu-Huai Wang is currently a graduate student in the Department of Mechanical and Electro-Mechanical Engineering at National Sun Yat-sen University, Taiwan. His research interests include advanced electronic packaging, process analysis, and thermo-mechanical reliability.

Abstract:
High-warpage packaging products present significant challenges during the singulation process because the initial deformation, local support condition, and stress-release path continuously evolve as cutting proceeds. As the package strip is progressively separated, the constraint condition becomes nonuniform, and bending stress may be redistributed to the remaining uncut regions. In practical manufacturing, an improper cutting sequence may induce local stress concentration, package displacement, unstable vacuum suction, and potential die fly-off. Therefore, this study investigates the effects of cutting sequence design and vacuum suction behavior on the stress distribution of high-warpage packaging products.
A finite element model was established to analyze the deformation and cutting-induced stress of a warped strip substrate. The model included the strip substrate, compound region, glass component, and rubber support, with material properties assigned according to the package structure. Three initial warpage heights, 3 mm, 4 mm, and 5 mm, were considered to represent different process conditions. The vacuum suction mechanism was simplified using the pressure difference between atmospheric pressure and the vacuum chamber pressure. This pressure difference generates a downward suction force on the substrate and changes the contact condition, deformation behavior, and stress distribution during cutting. The simulation results were then used to compare the maximum stress variation among different cutting paths.
Four cutting sequence methods were evaluated. Method 1 cuts from the outside toward the inside and was used as the reference case. Method 2 considers the vacuum chamber arrangement and avoids early damage to the central vacuum region. Method 3 starts from the two side-center regions to maintain a larger effective suction area during cutting. Method 4 begins from the maximum-stress region to release bending stress at an earlier stage. The results show that the cutting sequence has a strong influence on the maximum cutting stress. Under larger warpage conditions, Method 1 tends to generate higher stress concentration because the early cutting steps do not effectively release the bending stress. For the 5 mm warpage case, Method 1 produced the highest stress among the compared paths, whereas Method 4 substantially reduced the peak stress by cutting the high-stress region first. However, Method 4 may require a more complex cutting path and could reduce production efficiency. In comparison, Method 3 shows better overall potential because it lowers the maximum stress while maintaining a practical cutting path and a larger effective suction area.
The results indicate that cutting sequence design is a critical factor in the singulation of high-warpage packages. A proper cutting strategy can reduce local stress concentration, improve vacuum suction stability, and lower the risk of package displacement or die fly-off. Future work will incorporate residual stress effects, double-sided warpage models, and practical cutting sequence design rules for manufacturing applications.

 

Bio:
Name : KONDREDDY SAI BHARATH KUMAR REDDY Degree : Master's in Semiconductor Technology Department : Innovation Frontier Institute of Research for Science and Technology University : NATIONAL TAIPEI UNIVERSITY OF TECHNOLOGY Nationality : INDIAN

Abstract:
This study explores how different glass interposer materials affect the reliability of solder joints in 2.5D semiconductor packaging, using finite element analysis (FEA) simulations carried out in Ansys. As the electronics industry pushes toward increasingly compact and high-performance designs, 2.5D packaging has emerged as a promising integration strategy, but the choice of interposer material plays an important role in how well solder joints hold up over time.
Four glass interposer materials were put to the test: borosilicate glass, fused silica glass, Gorilla glass, and ceramic glass. Each material expands and contracts at a different rate when heated or cooled a property known as the coefficient of thermal expansion (CTE) and this difference creates mechanical stress at the solder joint level. The simulations followed standard industry JEDEC thermal cycling conditions, sweeping between −40°C and +125°C, while tracking von Mises stress and equivalent plastic strain deformation in SAC305 (Sn-3.0Ag-0.5Cu) solder interconnects.
The results showed Borosilicate glass produced the highest plastic strain deformation at 0.067 µm, followed by fused silica glass at 0.041 µm, Gorilla glass at 0.025 µm, and ceramic glass at just 0.015 µm. At first glance, ceramic glass appears to be the winner, but appearances can be deceiving. Its low deformation is not a sign of good compatibility with the solder system; rather, it stems from the material's exceptional stiffness, which simply prevents it from bending. Underneath that rigidity lies a substantial CTE mismatch with both SAC305 solder and silicon, meaning that under real-world prolonged thermal cycling, ceramic glass is actually at greater risk of driving solder fatigue and cracking, a danger that the simulation alone cannot fully reveal without a dedicated fatigue life model.
Borosilicate glass, on the other hand, shows a CTE of 3.3 ppm/°C that sits very close to that of silicon at 2.8 ppm/°C making it a far more compatible and industrially practical choice for 2.5D interposer applications, despite its higher simulated strain values. This finding drives home a broader point: plastic strain magnitude alone is not a reliable indicator of real-world solder joint performance. Future work incorporating established fatigue life prediction approaches, such as the Darveaux energy-based model or the Coffin-Manson strain-based model, would give a much more complete picture of how each interposer material holds up across the full product lifetime.

 

Bio:
Juhee Baek is a researcher at the Reliability Research Center, Korea Electronics Technology Institute (KETI), Republic of Korea. Her research focuses on semiconductor package reliability, finite element analysis (FEA), and thermo-mechanical behavior, and advanced packaging technologies.

Abstract:
BACKGROUND
As advanced packaging technologies continue to evolve toward high-density heterogeneous integration, chiplet-based architectures, and vertical interconnection, hybrid bonding has emerged as a key enabling technology for energy-efficient AI hardware and high-performance computing (HPC) systems. In these multi-layer structures, interfacial adhesion reliability is a critical concern; local delamination at sub-micron bonded interfaces can directly affect mechanical integrity, electrical continuity, and long-term package reliability. The double cantilever beam (DCB) test is the standard experimental method widely utilized to evaluate Mode-I interfacial fracture behavior. However, the high accuracy and reproducibility of the measured adhesion energy are strongly sensitive to the configuration of the loading tabs design and its associated experimental uncertainties.
OBJECTIVE
This study proposes a tolerance-aware, robust design methodology for DCB loading tabs to guarantee high-fidelity, Mode-I dominant fracture evaluation of hybrid-bonded interfaces. Conventional loading tab designs are typically established under idealized alignment and symmetric loading conditions. In practical laboratory testing, however, imperfections such as tab-positioning offsets, dimensional tolerances during tab fabrication, angular misalignments of the loading axis, and nonuniform bonding layers between the tab and specimen are inevitable. These physical variations can introduce unintended Mode-II (shear) and Mode-III (tearing) components into the interface. This mode contamination results in mixed-mode fracture conditions, including significant errors in the extracted apparent Mode-I fracture energy release rate (GI). Therefore, a robust design guideline is required to minimize mode mixity under realistic experiment variations.
METHODS
A systematic parametric finite element analysis (FEA) framework is established to evaluate the sensitivity of fracture-mode partitioning to key tab design parameters. The investigated geometric variables include tab thickness, tab length, bonding area, loading-hole position, and upper-lower tab structural symmetry. To capture realistic testing environments, quantified fabrication tolerances and assembly misalignments are intentionally introduced into the simulation models as structural perturbations. Mode-decomposed energy release rates (GI, GII, and GIII) are meticulously evaluated along the three-dimensional crack front using fracture mechanics node-splitting techniques. Through this extensive case study, design factors that are most vulnerable to mode contamination are isolated, and their allowable manufacturing tolerance thresholds are rigorously quantified.
RESULTS AND SIGNIFICANCE
The parametric simulation framework successfully yields a comprehensive, simulation-based design window for robust DCB loading tabs tailored for advanced packaging interfaces. The numerical results elucidate the exact mechanisms by which experimentally feasible variations in tab assembly alter the fracture-mode composition along the crack front. The analysis highlights critical design criteria that are missing from conventional standard recommendations, particularly when addressing thin hybrid-bonded layers characterized by sharp material property mismatches. By establishing a direct correlation between geometric optimization and experimental uncertainty, this work provides a practical foundation to suppress mode contamination and improve the repeatability of DCB-based interfacial characterization. The established guidelines offer an essential pre-experimental verification framework, contributing to the development of highly reliable fracture characterization standards for next-generation electronic packages.
ACKNOWLEDGEMENTS
This research was supported by the Ministry of Trade, Industry and Energy (MOTIE), Republic of Korea (RS-2024-00418263), and the Korea Institute for Advancement of Technology (KIAT) (RS-2023-KI002797)

 

Bio:
N/A

Abstract:
As electronic packages continue to move toward higher integration density, finer interconnect pitch, and more compact structures, solder joint reliability has become a critical concern in advanced packaging design. In WLCSP and flip-chip packages, solder balls function not only as electrical interconnects but also as mechanical load-bearing components between the chip and substrate. During thermal cycling, the mismatch in the coefficient of thermal expansion among the silicon chip, solder joints, and package substrate induces repeated thermo-mechanical deformation. This deformation promotes plastic strain accumulation in the solder balls, which may lead to fatigue damage, crack initiation, and eventual package failure.
Underfill is commonly applied to improve solder joint reliability by providing mechanical support and redistributing thermal stress. However, conventional full underfill may increase process time, material consumption, and rework difficulty. In addition, flow control during dispensing can become challenging, especially for compact package structures. Therefore, selective reinforcement has become an attractive alternative for improving reliability while maintaining process flexibility. In this study, epoxy flux is investigated as a localized reinforcement material for WLCSP applications, as shown in Fig. 1 and Table 1. Instead of filling the entire gap between the chip and substrate, epoxy flux reinforces the regions near the solder balls where plastic deformation is more likely to accumulate. This approach has the potential to reduce material usage while still providing effective mechanical support.
A three-dimensional finite element model was established to evaluate the effect of epoxy flux design on solder ball reliability. The package model was subjected to a temperature cycling condition from -40°C to 85°C, and SAC305 solder was used as the interconnect material. The equivalent plastic strain increment in the solder balls was selected as the main reliability indicator. Different epoxy flux heights, including 60%, 80%, and 100% of the solder ball height, were compared with the no-flux condition, as shown in Fig. 2. In addition, different area coverage ratios were considered to examine the influence of reinforcement range, as shown in Fig. 3.
The simulation results show that epoxy flux can effectively reduce the equivalent plastic strain increment compared with the no-flux model, as shown in Fig. 4. Among the investigated conditions, the 60% flux height showed the best reliability improvement. When combined with 100% area coverage, the strain increment decreased from 1.479% in the no-flux model to 1.106%, indicating a significant reduction in solder ball plastic deformation. In contrast, although 80% and 100% flux heights also improved the reliability compared with the no-flux case, their effects were less significant than that of the 60% flux height. This suggests that a higher flux height does not necessarily lead to better reinforcement performance. Meanwhile, increasing the area coverage under the same flux height slightly reduced the strain increment, but its influence was relatively limited compared with the effect of flux height.
In conclusion, this study demonstrates that localized epoxy flux reinforcement can enhance solder joint reliability under thermal cycling without requiring full underfill. The results indicate that flux height is the dominant design factor, while area coverage provides a secondary improvement. An appropriate epoxy flux design should balance mechanical support and deformation flexibility, making it a promising reinforcement approach for compact, high-reliability, and cost-sensitive WLCSP applications.