Sessions Index

Bio:

Dr. Li-Cheng Shen is currently the AVP of Miniaturization Competence Center of USI, focusing on developing and researching cutting-edge technologies of miniaturization. With more than 20 years of experience in the semiconductor industry, Dr. Shen owned more than 30 patents in the fields of Fault Diagnosis System, 3D Package, Wafer Level Package, Opto-electronic Package, Electro-optical Circuit Board, Embedded Component Substrates, RF Module Testing and RF SiP/System Assembly. He is also the technical committee member of ED&A (Electrical Design and Analysis) of ECTC.
In 1998, Dr. Shen received a PH.D. degree in Electrical and Control Engineering from Nation Chiao-Tung University, Taiwan.

Abstract:

- why considering glass
- the system on module on glass (SoMoG)
- how the electrical property of the SoMoG behaves
- how the mechanical warpage of the SoMoG performs
- how the thermal dissipation of the SoMoG achieves
- key process challenges to be identified and solved

 

Bio:

Alex Liu has over 25 years of experience in the semiconductor packaging industry, specializing in equipment engineering, process integration, and advanced packaging technologies. He began his career as an Equipment Engineer and later advanced to process development leadership, pioneering multi-chip stacking and high-density package integration. In 2012, he led 3DIC and TSV technology development with leading IDMs, building a strong foundation for future high-end applications. Since 2016, he has driven the development and mass production of panel-level fan-out packaging, enabling heterogeneous device integration, and has devoted his career to continuously learning and advancing new technology development.

Abstract:

In this talk, we share how the Hi-CHIP Alliance, together with our industry partners, embarked on an accelerated effort to explore glass interposer process integration within a three-month timeframe. By coordinating across multiple companies, we combined expertise and resources to investigate some of the most demanding challenges in advanced packaging.
The presentation will guide the audience through critical process modules—such as precision TGV drilling and wet etching, deposition of Ti/Cu seed layers using advanced PVD, and copper filling strategies with electroplating chemistry. Along the way, we will highlight key technical observations, integration sensitivities, and lessons learned that are highly relevant to manufacturability and reliability.
Rather than focusing on final hardware, this session emphasizes insights gained from tackling real-world hurdles and aligning multi-company collaboration toward common goals. These experiences not only deepen understanding of glass interposer technology but also provide guidance for future development paths in advanced packaging.

 

Bio:

Dr. Jack, Wen-Liang Yeh has a bachelor’s degree and master’s degree in chemical engineering from the National Cheng Kong University, Taiwan and a Ph.D degree in chemical engineering from the National Tsing Hua University, Taiwan in 2008. He started his career job as R&D researcher in the chemical industry and joined Unimicron in 2013 for the development of glass core substrate till now.

Abstract:

Substrate warpage and metal junction are key factors in assembling advanced heterogeneously integrated products. Glass cores can provide dimensional stability, and Cu-Cu direct bonding has the potential to improve power/signal integrity. In this talk, we share our exploration of the Glass Interposer M2M-bonded Core, focusing on design considerations, process flow, and key technical insights gained from integration efforts.

 

Bio:

Dr. Jeng-Ting Li is a Deputy Project Manager in the New Business Department at Unimicron, where he has been engaged since 2018 in the development of advanced glass core substrate processes and Fan-Out Panel Level Packaging (FOPLP) redistribution layer (RDL) technologies. His work focuses on process evaluation, integration, and reliability improvement for next-generation substrate solutions. He holds a Ph.D. from the Department of Materials Science and Engineering at National Cheng Kung University in Taiwan.

Abstract:

Glass core substrate (GCS) technology is emerging as a promising solution for high-density interconnection in advanced packaging. Its inherent advantages such as low dielectric loss, high dimensional stability, and mechanical robustness make it suitable for next-generation electronic systems. A key challenge in GCS fabrication is the reliable formation and filling of Through Glass Vias (TGVs), which require precise control over via drilling, metallization, and dielectric filling. This study demonstrates a panel-level process for building a GCS test vehicle (TV) with dual-side redistribution layers (RDLs). The structure includes six RDL layers and six dielectric layers on a 200 mm × 200 mm glass panel with 400 µm thickness. The TGVs were metallized using conformal copper plating, and the via centers were filled with a vacuum-laminated photo-imageable dielectric. Fine-line patterning was achieved using a dry semi-additive process with a minimum line/space of 10/10 µm. The results confirm the feasibility of integrating materials and processes for scalable glass-based packaging.