Sessions Index

Bio:

Shinya Shimizu is the Founder and CEO of Elephantech, a company pioneering low carbon, resource-efficient manufacturing approach for printed circuit boards. He founded the company in 2014 and has led the company to become the first to achieve mass production of PCB manufacturing using copper nanomaterial-based inkjet printing technology.

Abstract:

This presentation introduces innovative vertical interconnect technologies utilizing copper nanomaterials. As advanced packaging becomes increasingly important, vertical interconnect technologies—rather than only lateral interconnect scaling—are becoming critical. We will introduce two technologies enabled by copper nanomaterials: DeepVia™, which enables high-aspect-ratio vias, and SAphire™, a copper sintering paste for advanced bonding applications.

 

Bio:
Roger gained his degree in Materials and Microstructural Engineering from Sheffield Hallam University before continuing with post graduate work at The University of Northumbria at Newcastle. He has only ever worked within the electronics industry, initially developing thick film and power hybrids for medical and military applications before joining the global automotive group of Motorola as a process specialist for wire bonding and soldering applications. In 2000 he joined Via Systems, UK where he remained for 6 years as a Senior Process Engineer responsible for all aspects of inner and outer layer production. Since joining Atotech in 2006 Roger has held global technical and managerial positions in China and Germany and is currently Technical Marketing Manager focusing on products for surface treatment and primary metallisation

Abstract:
Since their advent in the 1990s, laser formed blind microvias (BMV) have become a common design feature in modern PCBs as they offer unrivalled opportunities for device miniaturization. However, as their use has expanded into ever more challenging applications, there has been a growing concern regarding their long-term reliability performance, especially when replacing a traditional “staggered” or “offset” design with the more enabling “BMV stack”
Initially, such concern was addressed through investigations that reported on the physical testing of stacked BMVs, but more recently, there have been a number of publications regarding the metallurgical characteristics of plated and filled BMVs. In such investigations there have been two predominant microstructures identified, one being considered as “ideal” and the other being less favored as it has been shown to be mechanically weaker. In view of these findings there has been ongoing desire to not only understand how such structures are formed, but to ensure that the ideal situation becomes the norm for high volume manufacturing.
In this paper, we summarize our current findings regarding the two dominant plated structures and identify some factors which impact their formation. We follow this by introducing the concept of “Normalized Crack Length” (NCL) as a means for evaluating crystallographic epitaxy in a BMV. Using examples taken from production made PCBs, the derived NCL is then shown to be a positive indicator for relative reliability performance, and can be used as a viable means to compare and evaluate the performance of plated BMVs.

 

Bio:
Dr. Kesheng Feng is a R&D Director at the Metallization Technology business at MacDermidAlpha Electronics Solutions in Waterbury, CT, USA, responsible for the research and development of metallization technologies in the field of printed circuit boards and IC substrate. Starting in MacDermid’s Central R&D group 28 years ago, Kesheng has experience in a variety of applications in the field of printed circuit boards and IC substrate over 30 years. He holds fifteen patents and has over thirty publications in magazines, journals, and industry technical conferences.

Abstract:
The rapid expansion of servers and electric vehicles has driven significant demand for high-layer-count (12+ layers) and high-density interconnect (HDI) PCBs. These complex architectures require large stacked vias and high-aspect-ratio through-holes paired with fine-pitch Ball Grid Array (BGA) patterns to support high-speed signal transmission, thermal management, and power efficiency. However, conventional direct current (DC) plating processes have limitation to plate through holes on a thick board, which can lead to non-uniform copper distribution, such as the "dog-bone" effect and severe surface thickness variations that disrupt impedance matching and compromise solder joint reliability. This paper reviews process optimizations to address these challenges, specifically focusing on high-aspect-ratio through hole configurations and high-hole-density regions where localized potential drops reduce throwing power and increase the thickness variation on surface. The deployment of periodic pulse reverse (PPR) plating technologies combining with PPR products such as brand names of PC 600 and PC 610 mitigate the issues and ensure robust hole plating to achieve a planarized surface and high throw power inside holes.

 

Bio:
will follow later

Abstract:
Continued scaling of IC substrate interconnects toward finer line/space dimensions and increasing package complexity places growing demands on patterned blind microvia (BMV) filling in build-up layers. In addition to void-free via filling and low surface copper thickness, advanced IC substrate manufacturing requires excellent within-unit and within-panel copper thickness uniformity across a wide range of layouts and operating conditions, while maintaining high productivity in volume production environments.
Organic IC substrates are a key enabler for next-generation AI accelerators and high‑performance computing (HPC) modules, driving strong growth in advanced substrate technologies. Market forecasts expect the advanced substrate market to reach approximately USD 31 billion by 2030, driven by AI, HPC, and increasing package complexity [1]. To meet these requirements, leading substrate manufacturers are transitioning toward line/space dimensions of 10/10 µm and below, where the semi-additive process (SAP) is the dominant build-up layer approach. Within this process flow, patterned BMV filling represents a major yield and performance risk, as local copper thickness variation within the unit can directly impact impedance control, pad-to-trace height uniformity, and downstream assembly margins. Consequently, stable copper thickness distribution at practical current densities is a key performance metric for advanced IC substrate processes [2].
This paper presents a new electrolytic copper process for patterned DC BMV filling in vertical plating systems using insoluble anodes. The process is designed to deliver robust via filling and uniform copper deposition for advanced IC substrate and redistribution layer (RDL) applications. Experimental evaluation focuses on BMV filling performance, within-unit distribution and uniformity, current-density capability, and benchmark comparisons across four different board designs. Performance metrics include plated copper thickness range, relative thickness range, dimple depth, and line-profile control for fine-line features.
The results demonstrate reliable BMV filling with dimple depths below 2 µm and improved thickness uniformity compared with benchmark processes across all evaluated board designs. The process shows reduced layout sensitivity, maintaining consistent copper thickness distribution for dense and isolated features. Stable filling and uniformity are achieved over a current density range from 1 to 3 A/dm², supporting both productivity and process flexibility. Overall, the new electrolytic copper process provides a layout-robust and benchmark-competitive solution for patterned BMV filling, enabling advanced IC substrate designs with increasing density, complexity, and manufacturing demands.

 

Bio:
John Carlo is a Product Specialist for Primary Metallization at MacDermid Alpha specializing in direct metallization technologies for printed circuit board manufacturing. Before his current role, he worked in R&D on process development, reliability testing, and customer evaluations for direct metallization. His work has included collaboration with PCB fabricators in North America and Asia.

Abstract:
Electroless copper metallization is historically the most popular primary metallization process used for making holes conductive in printed circuit board (PCB) manufacturing. Electroless copper represents ~83% of the $670M “making holes conductive” market. This technology is well understood and highly reliable, making it the method of choice for mission-critical applications.
This chemical process prepares a circuit board for electrolytic plating by covering a hole wall with a seed layer of copper ranging from 0.3 to 1.0 μm in thickness. Electroless copper plating consists of various process steps including - cleaning, micro-etching, conditioning, activating, and electroless copper deposition.
Additionally, electroless copper lines vary in processing configuration, with some utilizing horizontal conveyorized equipment and others employing vertical hoist-based systems consisting of sequential chemical baths. The consensus is that horizontal processing leads to increased reliability due to the improved uniformity of solution exchange and consistency of the process.
The objective of this study is to compare the impact of catalyst type and processing method on reliability performance. A comprehensive test vehicle has been developed and evaluated using a range of reliability tests across multiple substrate types, including high-Tg, ultra-low-loss materials commonly used in server applications. Reliability performance was assessed by constructing a comparative dataset across catalyst chemistries and processing configurations on substrates with increasing Tg.

 

Bio:
Dr. Frank Xu is the Director for Final Finish Line of Business at MacDermid Alpha Electronics Solutions. He brings about 20 years of experience to the company, joining after earning his doctorate in Materials Science and Engineering from the University of Pittsburgh. His responsibilities include setting strategy for final finish product lines, overseeing new product research and development, and facilitating direct technical and strategic roadmap discussions with both direct and OEM customers. Dr. Xu's expertise is further demonstrated by his numerous presentations at technical conferences and his multiple patents.

Abstract:
The rapid growth of electric vehicles (EVs) is driving increased demand for highly reliable electronic assemblies used in battery management systems, power conversion modules, onboard charging systems, vehicle control units, and advanced driver-assistance systems. As manufacturers seek cost-effective, lead-free solutions that can meet stringent automotive reliability requirements, immersion tin has emerged as an attractive final finish due to its excellent solderability, flat surface profile, and compatibility with fine-pitch assembly processes.
This presentation reviews recent advances in immersion tin final finish technology that have enhanced its suitability for demanding EV applications. Key developments in process chemistry, bath stability, deposit quality, corrosion resistance, and whisker mitigation will be discussed. In addition, the presentation will highlight emerging applications of immersion tin in EV electronics, including battery management systems, power electronics, and vehicle control modules. Current industry trends, technical challenges, and future opportunities will be explored, with an emphasis on how ongoing innovations in immersion tin technology are supporting the evolving requirements of next-generation automotive electronics.
The results demonstrate that continued improvements in immersion tin chemistry and process control are expanding its capability as a reliable, sustainable, and cost-effective final finish solution for the rapidly growing EV market.
Keywords: Immersion Tin, Final Finish, Electric Vehicles, Automotive Electronics, Battery Management Systems, Power Electronics, Solder Joint Reliability, Whisker Mitigation.

 

Bio:
Academy of Circular Economy, Taichung 402, Taiwan

Abstract:
With the rise of advanced packaging and 3D ICs, low-temperature (<250°C) Cu-Cu direct bonding is crucial for high-density interconnects. However, ambient or low-temperature oxidation forms native Cu2O and CuO layers that inhibit atomic diffusion and degrade bond quality, making accurate oxide quantification crucial. While previous research focuses on high-temperature oxidation kinetics, phase-resolved thickness quantification of thin CuO/Cu2O layers formed below 200°C remains limited. This study utilizes galvanostatic coulometric reduction (GCR) paired with Faraday’s law to quantify CuO and Cu2O thicknesses in low-temperature oxidized copper films. Electrochemical data confirmed a stepwise reduction sequence CuO→Cu2O→Cu, supported by interrupted-reduction Raman and XPS analyses. Notably, the SAE outperformed NaOH by providing clearer reduction plateau separation and minimizing signal overlap. Furthermore, TEM and Alpha-step analyses validated the accuracy of the electrochemically estimated thicknesses. Ultimately, this study establishes a reliable electrochemical method for phase-resolved copper oxide quantification, serving as a valuable process-control tool prior to Cu-Cu bonding.
Keywords: Cu-Cu bonding, copper oxide, galvanostatic coulometric reduction