Sessions Index

Abstract:

As package body sizes continue to increase, the industry must explore all options to manage both cost and yield. Panel-level packaging was originally adopted for some smaller, simpler applications. Now, in this second wave of panel-level packaging, advancements have been made that may support larger, complex packages built on panels. However, there are a multitude of panel sizes currently being pursued across the industry, with no clear answer on which panel size may be optimal. This analysis focuses on two panel sizes: 310x310mm and 510x515mm, with a 300mm wafer baseline included for comparison. Activity-based cost modeling is used to compare processing costs for 50x50mm, 100x100mm, and 150x150mm molded RDL interposers across all three formats. Key cost drivers and design trade-offs are identified, and the impact of yield is included.

Abstract:
In recent years, the advancement of generative AI and large language models (LLMs) has been enabled not only by increased chip computational performance, but also by high-speed interconnects between chips. To address future demands for higher I/O density, redistribution layer (RDL) manufacturing faces challenges in achieving finer patterning, improved signal transmission efficiency, and enhanced scalability. To overcome these challenges, numerous studies have reported a transition from silicon interposers to organic interposers.
RDLs in organic interposers are generally patterned using lithographic processes with photosensitive dielectric materials. However, photosensitive materials present a challenge in achieving fine patterning (line/space ≤ 2/2 μm) while maintaining material properties. By adopting non-photosensitive dielectric materials, it becomes possible to preserve and improve material characteristics. However, this introduces a new challenge in achieving fine patterning without the use of conventional lithography.
Furthermore, RDLs are typically formed using a semi-additive process (SAP), which has been widely implemented in the formation of build-up layers in semiconductor package substrates. However, in applications requiring finer patterning, SAP presents several issues, including pattern collapse caused by undercut during seed layer etching and critical dimension (CD) errors due to surface waviness generated during multilayer stacking.
To address these challenges, fine patterning of non-photosensitive dielectric materials using KrF excimer laser ablation is considered an effective solution. Since the material does not need to be photosensitive, it allows for greater focus on improving material properties such as dielectric constant. Additionally, the short wavelength of the KrF excimer laser makes it well-suited for high-resolution microfabrication. The equipment system employs a mask pattern reduction projection method, enabling batch processing over a large area. It can fabricate not only vias but also a wide variety of pattern geometries.
Compared to conventional galvanometer mirror–based laser processing systems that machine holes sequentially, this system can maintain high productivity even as pattern density increases. Furthermore, because it utilizes mask transfer, it is well suited for improving various accuracy parameters, including alignment precision.
Moreover, precise control of processing depth can be achieved by adjusting the number of laser pulses.
This capability enables compatibility with the dual damascene process, in which vias and trenches are simultaneously filled with copper plating. This process has a proven track record in front-end semiconductor manufacturing and offers advantages such as eliminating the seed layer etching step and suppressing surface waviness through planarization by chemical mechanical polishing (CMP). As a result, this approach provides a solution to conventional process challenges while achieving both miniaturization and improved transmission performance.
In this study, fine patterning was performed on non-photosensitive dielectric materials using a mask projection system equipped with a high-power KrF excimer laser for ablation. As a result, via diameters of 3 μm and line/space of 2/2 μm were successfully fabricated, with taper angles of approximately 85° achieved in both cases. These results demonstrate that KrF excimer laser ablation enables fine RDL formation even with non-photosensitive dielectric materials and is compatible with the dual damascene process.

Abstract:
This study employs empirical equivalent material property models to investigate the influence of copper routing pattern geometry on the equivalent Young's modulus of a redistribution line-like (RDL-like) structure in advanced packaging and to develop pattern-correction models that more accurately predict the effective material properties of complex routing structures.
Classical analytical approaches, including the rule of mixtures (ROM) and inverse rule of mixtures (IROM), are adequate for unidirectional patterns but fail to account for the effects of trace geometry, directionality, and connectivity in complex routing configurations, resulting in relatively large prediction errors. In this study, a set of standard routing patterns representative of advanced packaging layouts is adopted as the basis for FEM homogenization modeling using ANSYS APDL. Equivalent material properties are evaluated across a range of copper volume fractions, pattern arrangements, and geometric parameters, and the applicability of classical analytical models (ROM, IROM, and the Halpin-Tsai model) is assessed.
The results show that the equivalent Young's modulus of diagonal-type and sinusoidal-waveform trace patterns is governed not only by the copper volume fraction, but is also coupled with the wire inclination angle and waveform amplitude. To capture this pattern effect, an angular correction function and geometric correction terms are introduced to calibrate the semi-empirical Halpin-Tsai model, which accounts for the influence of trace directionality on stiffness and reduces the prediction error of conventional analytical models.
The corrected equivalent model is further applied to the mechanical analysis of practical redistribution layer (RDL) structures, where finite-element simulations are conducted to compare mechanical responses between the equivalent and full-geometry models. Results show that the equivalent model can substitute for complex copper trace patterns while maintaining satisfactory prediction accuracy, thereby reducing both degrees of freedom and computational cost. Across various RDL trace configurations and copper distribution conditions, the proposed model provides consistent predictions of equivalent stiffness, making it suitable for stress assessment and rapid design verification in advanced packaging.
In addition, the pattern-property database built in this study can be combined with image recognition and artificial intelligence techniques in future work to predict equivalent material properties directly from routing geometry.
Keywords – Advanced packaging; Finite element method (FEM); RDL-like, ROM, IROM

Abstract:
As Moore’s Law gradually approaches its physical limits and the demand for high performance in artificial intelligence (AI) chips continues to increase, advanced packaging has become an important approach for improving overall system performance. Fan-out packaging redistributes chip I/O terminals through redistribution layer (RDL), thereby increasing the number of I/O connections and enhancing layout flexibility. Depending on the carrier format, fan-out packaging can be classified into fan-out wafer-level packaging (FOWLP) and fan-out panel-level packaging (FOPLP). Compared with wafer-level packaging, panel-level packaging provides higher material utilization and lower manufacturing costs. However, its larger structural dimensions also result in more significant warpage.

During packaging processes, multiple thermal cycles cause stress accumulation and warpage due to mismatches in the coefficients of thermal expansion (CTE) among different materials. Warpage may affect alignment accuracy, product reliability, and manufacturing yield. Therefore, the rapid and accurate prediction of warpage has become an important issue in advanced packaging.

This study first investigates mesh modeling strategies for FOPLP structures and validates the models using multiple sets of experimental measurements. The prediction accuracy of a uniform mesh model is compared with that of a hybrid mesh model incorporating local mesh refinement at the four corners. The results show that the uniform mesh model yields an average error of 9.64%, whereas the hybrid mesh model reduces the average error to 3.44%. This demonstrates that local mesh refinement effectively captures the stress and deformation behavior in the corner regions, thereby improving the accuracy of FOPLP warpage prediction.

For multilayer RDL structures, equivalent structures and material properties are employed to avoid the excessive computational cost associated with directly modeling fine copper traces. The average reference temperature method is then introduced into the hybrid mesh model. The results indicate that the conventional reference temperature method produces an average error of 72.33%, whereas the average reference temperature method reduces the error to 3.44%, demonstrating its suitability for thermal stress analysis of multilayer RDL structures.

Based on the validated finite element model, a large simulation database is established, and a quarter-symmetry model is employed to reduce modeling and computational costs. Machine learning methods are subsequently integrated to predict not only the maximum warpage value but also the global warpage profile of the entire FOPLP structure.

Furthermore, a recursive prediction model is developed to progressively predict the global warpage of subsequent layers based on the prediction result of the preceding layer. This approach reduces the required amount of data and model development costs while achieving an average error of only 3.70% compared with experimental measurements. The developed model can rapidly and accurately predict global warpage and can be further applied to parameter analysis and optimization to identify appropriate process conditions for warpage reduction.

In summary, this study integrates finite element analysis and machine learning to establish a comprehensive framework for global warpage prediction and parameter optimization. The hybrid mesh and average reference temperature methods improve simulation accuracy, while the recursive machine learning model enables highly accurate warpage prediction and packaging design optimization with reduced computational costs.

Abstract:
ABSTRACT
As the demands of artificial intelligence, high-performance computing, and high-speed communication increase, advanced packaging has become a key approach for improving chip performance and system integration. Fan-out panel-level packaging (FOPLP) has attracted attention because of its high input/output density, material utilization, and large-area manufacturing potential. In FOPLP, redistribution layers (RDLs) rearrange chip I/O terminals to improve layout flexibility. However, as RDL layers increase and circuit patterns become more complex, local surface topography variations become more significant, affecting subsequent stacking, process stability, and surface planarity.
In multi-layer RDL fabrication, polyimide (PI) is commonly used as a dielectric material. During post-curing, PI shrinkage, copper trace constraint, and local pattern-density variation can induce dishing deformation. PI dishing is affected by linewidth, spacing, copper coverage, and circuit geometry, and may accumulate during multi-layer stacking. Although finite element analysis (FEA) can evaluate PI dishing and surface topography, modeling numerous RDL regions over a full panel requires considerable preprocessing and computational time. Therefore, a fast prediction method is required for multi-layer RDL process design.
This study integrates FEA and deep learning to establish a prediction framework for PI dishing and surface topography in multi-layer RDL processes. Regions of interest (ROIs) with different circuit features are extracted from a single-unit circuit layout, and corresponding RDL finite element models are constructed using Moldex3D. The simulated Z-direction displacement after PI post-curing is used as training and validation data. RDL layouts are converted into binary images, while simulated displacement results are transformed into image-format datasets, allowing the models to learn the relationship between circuit geometry, PI dishing, and surface topography.
For single-layer RDL prediction, convolutional neural network (CNN) and U-Net models are developed, and their prediction results are compared. The CNN model extracts geometric features from RDL patterns through convolution operations, whereas the U-Net model, with its encoder–decoder structure and skip connections, preserves local image details and is suitable for pixel-wise surface topography prediction. This comparison evaluates different architectures in predicting edges, corners, and high-gradient deformation areas.
After completing the single-layer prediction model, this study extends the framework to multi-layer RDL processes. To describe layer-by-layer surface topography evolution, a recursive U-Net model is developed. The current RDL layout and previous-layer height map are used as inputs, and the Z-direction displacement after the current process is predicted as the output. The predicted result of one layer is then used as the input for the next layer, enabling sequential prediction of surface topography in multi-layer RDL structures.
The results show that both CNN and U-Net models can capture the relationship between RDL geometry and PI dishing distribution, while U-Net provides better performance in local detail preservation and surface reconstruction. Therefore, U-Net is adopted as the main architecture for multi-layer and recursive prediction. Finally, a user interface (UI) integrating full-panel RDL layouts and the trained model is developed to rapidly predict surface topography after multi-layer RDL stacking. The proposed platform can support RDL process development, layout evaluation, and surface planarity improvement for FOPLP applications.
Keywords: Fan-Out Panel-Level Packaging (FOPLP), Redistribution layer (RDL) process, Polyimide (PI), Convolutional neural network (CNN), Surface topography.

Abstract:
Glass substrates have emerged as a promising material for next-generation semiconductor packaging due to their ultra-smooth surfaces, excellent thermal and mechanical stability, low coefficient of thermal expansion, and superior dimensional control. Compared with conventional organic substrates, glass also exhibits significantly lower dielectric loss at high frequencies, making it highly attractive for advanced computing, artificial intelligence (AI), and high-speed communication applications. In addition, glass substrates are cost-effective, available in large panel sizes, and free from material scarcity concerns. These advantages position glass as a key enabling material for future semiconductor packaging and an important technology for extending Moore’s Law.
　　Despite these benefits, several technological barriers remain before glass substrates can be widely adopted in advanced packaging. One of the challenges is the development of reliable metallization processes with strong interfacial adhesion, as poor adhesion can significantly compromise both circuit performance and long-term package reliability. To address this challenge, our group has developed a wet metallization process based on electroless deposition (ELP) Cu using a self-adsorbing palladium nanoparticle catalyst capped with 3-aminopropyltriethoxysilane (APTES) in combination with a titanium dioxide (TiO2) adhesion-promoting layer (APL). The TiO2 APL provides a nanoporous structure that facilitates mechanical interlocking between the deposited copper and the underlying glass substrate. As a result, electroless copper layers with peel strengths exceeding 1300 gf/cm have been achieved on alkali-containing glass substrates.
　　In this work, the effects of TiO2 APL processing parameters on ELP Cu adhesion and reliability are systematically investigated. The influence of TiO2 thickness, pore morphology, and post-deposition thermal treatment conditions is examined to establish the structure–property relationships governing interfacial bonding. In addition, TiO2 APLs fabricated by spin coating are compared with those prepared by atomic layer deposition (ALD) to elucidate the role of film density, porosity, and microstructure in adhesion enhancement. Peel-strength measurements, microstructural characterization, and reliability evaluations are conducted to identify the optimal APL architecture for robust metallization.
　　The results provide important insights into the adhesion mechanisms of electroless copper on glass and demonstrate the critical role of nanoporous TiO2 interlayers in achieving high-reliability metallization. This study contributes to the development of scalable, cost-effective wet metallization technologies for advanced glass-based semiconductor packaging applications.

Abstract:
The exponential growth of data-intensive applications, particularly within the demanding domains of high-performance computing (HPC) and artificial intelligence, is generating an insatiable demand for data throughput that has pushed traditional architectures to their limits. This has created an unprecedented and critical I/O bottleneck on the communication pathways connecting logic and memory. To surmount this fundamental performance barrier, the semiconductor industry is strategically pivoting towards heterogeneous integration schemes, with a primary focus on advanced packaging that combines System-on-Chip (SoC) logic with High Bandwidth Memory (HBM) modules. The ultimate success of these complex, multi-chip architectures is critically dependent on the ability to fabricate ultra-high-density redistribution layers (RDLs), the intricate nervous system of the package, which must deliver both immense bandwidth and superior energy efficiency.
Conventional mask-based lithography, a cornerstone of semiconductor fabrication, struggles to compensate for the non-linear substrate distortions inherent to large-format wafers used in advanced packaging. This forces the use of conservative design rules, such as oversized landing pads and wider traces, which directly limits routing density and becomes a primary source of yield loss from registration errors. This paper introduces a production-ready digital lithography technology that operates without a physical mask. At its core, the technology performs real-time topological mapping of the substrate, adjusting the projected pattern on a die-by-die basis to dynamically compensate for wafer warpage and distortion (Fig. 1). The process performance enabled by this adaptive approach is exceptional. We demonstrate robust fabrication of 1 µm line/space patterns, 2 µm vias, and 3 µm landing pads on 300mm wafers. Critically, this is achieved with an overlay accuracy better than 0.25 µm, a metric essential for multi-layer RDL builds. This tight registration control allows for the aggressive scaling of via landing pads, directly enabling denser vertical interconnects while mitigating a primary source of yield-killing electrical opens. Furthermore, the process exhibits a within-wafer critical dimension uniformity of <3%. This level of control ensures consistent electrical characteristics (e.g., resistance, capacitance) across all interconnects on the wafer, broadening the process window and guaranteeing predictable, high-speed signal integrity for every die. The combination of these tightly controlled process capabilities facilitates a transformative, greater-than-four-fold improvement in interconnect density over conventional 2/2 µm RDL nodes, without compromising manufacturing yield or long-term system reliability (Fig. 2). This advancement provides a critical and economically viable manufacturing pathway for the future of advanced packaging. By providing manufacturing certainty for finely pitched interconnects and minimized via structures, it fundamentally empowers system architects to pursue designs previously considered unmanufacturable, unlocking a new generation of heterogeneous systems with superior bandwidth efficiency, reduced power consumption, and greater functional density.