Sessions Index

Bio:

Professor Nogita graduated as an Engineer in Japan in 1990 and worked in the nuclear power industry with Hitachi Ltd. He was awarded a PhD from Kyushu University in 1997. He migrated to Australia in 1999 after accepting a position at the University of Queensland, where he became the founding director of the Nihon Superior Centre for the Manufacture of Electronic Materials (NS CMEM) in 2012 as well as project manager of the University of Queensland – Kyushu University Oceania project (UQ-KU project) at the School of Mechanical and Mining Engineering. He is also an invited Professor at Kyushu University and a Research Adviser at the University of Malaysia Perlis. His research is in three major areas, namely lead-free solders and interconnect materials, energy materials such as hydrogen-storage alloys, and structural and coating alloy development. He holds 20 international patents and has authored over 250 refereed scientific papers. He is a deputy chair for the Electronic Packaging and Interconnection Materials (EPIM) Committee (since 2022), and Leading organiser (2019 and 2023) and Co-organiser of the “Emerging interconnect and Pb-free materials for advanced packaging technology” symposium at TMS in the USA, from 2015 to the current date. He is the recipient of the TMS Research to Industrial Practice Award in 2021.

Abstract:

If electronics manufacturers and users are to have confidence in the reliability of the solder joints on which electronic devices and systems rely, it is essential to have an understanding of the solder joint failure mechanisms and the role of dynamic recrystallisation in failure. However, due to difficulties in real-time atomistic scale analysis during deformation, we still do not fully understand these mechanisms. Here, we report the development of an innovative in-situ method using high voltage transmission electron microscopy (HV-TEM) for observation of the microstructural response of a solder joint to room temperature tensile loading.  This technique was used to observe events including dislocation formation, dynamic recrystallisation, grain boundary separation, and crack formation and propagation in a Sn-3wt.%Ag-0.5wt.%Cu (SAC305) alloy joint formed between copper substrates.

This invited talk provides recent progress introduced at ICEP2025 in Nagano, Japan, detailing how advanced characterisation approaches such as HV-TEM can be used to optimise and develop Pb-free solder alloys and associated intermetallics that form between the solder alloys and substrates of electronic interconnects.

 

Bio:

Yukako Ikegami received her BS and MS degrees from Tokyo Institute of Technology. She worked as a process engineer at Toshiba Corporation. At Toshiba, she was primarily involved in process development, including the development of 3D-NAND.Since 2022, she has been in charge of being a lead process engineer for WoW hybrid bonding for Image Sensors at Sony Semiconductor Solutions Corporation.

Abstract:

Three-dimensional (3D) stacking is a significant trend in advanced semiconductor technology. In structures with three layers, Cu-Cu hybrid bonding is introduced on face-to-face and face-to-back surfaces, electrically connecting through silicon vias that penetrate the middle substrate. During Cu-Cu hybrid bonding shrinkage at the face-to-back interface, the presence of two bonding interfaces makes alignment control critical.
This study investigates the development of face-to-back Cu-Cu hybrid bonding in a three-layer structure and evaluates the impact of wafer warpage on its bonding properties. We examined fine and large-scale Cu-Cu connections with a pitch of 1.4 μm and two million connections, establishing two warpage levels: Process A and Process B. The results showed that Process A had poorer alignment accuracy, leading to open defects at a 1.4 μm pitch, which significantly affected the reliability of the connections. Additionally, we evaluated the connectivity of long daisy chains with 0.7 μm pads, achieving over 90% yield, demonstrating the effectiveness of the bonding process under controlled conditions.
This research emphasizes the critical role of managing wafer warpage to enhance bonding precision and electrical performance. By systematically analyzing the effects of warpage, we provided insights into how variations can impact the overall performance of the bonding process.

 

Bio:

Takumi Yumoto is an engineer of the Products Development Department at Shinko electric industries CO.LTD.
He has been working on Packaging technology development.
Recently, he has also been working on the development of packaging technologies for power semiconductors known as POL (Power Overlay).

Abstract:

In pursuit of developing a low-inductance power module, we engineered a module featuring a POL double-layer facing structure. This design demonstrated a mutual inductance cancellation effect of 14.9 nH, reducing the module’s parasitic inductance to 8.7 nH. Furthermore, by decreasing the inter-module distance to 1.0mm in the simulation, the mutual inductance cancellation effect was enhanced, resulting in a reduction of the module‘s parasitic inductance to 5.5 nH.

 

Bio:

Toshiyuki Takasaki is the manager of the Process Equipment Development Department at Panasonic Connect Co., Ltd, and is responsible for the development of plasma process equipment and respective processes, as well as the total process integration of Plasma Dicing.
In 2017, he joined Panasonic Connect Co., Ltd, as a process engineer. Scince then. he has been in charge of R&D activity and product development of plasma dicing processes.
He received Master's degree of Electrical Engineering from Kyushu University, Japan, and MBA from Graduate school of management, GLOBIS university, Japan.

Abstract:

Hybrid bonding is an essential technology for 3D stacking, and particularly in Die-to-Wafer (D2W) bonding, the die requires an extremely high level of cleanliness equivalent to that of the Front End of Line (FEOL). Plasma dicing has features such as being particle-free and chip-free compared to existing blade dicing methods, making it an indispensable dicing technology for next-generation 3D stacking technology. This presentation will introduce plasma dicing technology that achieves particle-free process and its total solution.

 

Bio:

Kai Takeuchi received his Ph.D. degree from the University of Tokyo in 2020 and currently is assistant professor in Tohoku University, Japan. He has been working on low temperature bonding technologies for electronics packaging inclusing surface activated bonding, plasma activation bonding, ans polysilazane-mediated bonding.

Abstract:

Room temperature wafer bonding using polysilazane as a bonding layer offers significant advantages for advanced semiconductor and MEMS packaging. This study demonstrates strong and reliable bonding of silicon wafers at ambient temperature by converting the polysilazane layer to silicon dioxide through plasma-assisted hydrolysis. The process enables void-free interfaces, reduces thermal budget, and avoids substrate warping typical of high-temperature bonding. Infrared imaging and mechanical tests confirm high adhesion and interface quality. The method is compatible with standard wafer substrates and promises improved yield and process flexibility. These results highlight its potential for next-generation electronic device integration.