Sessions Index

Bio:
I am a graduate student in the Department of Electronic Engineering at National Pingtung University of Science and Technology, Taiwan. My research focuses on low-temperature co-fired ceramics (LTCC) for high-frequency applications. I am dedicated to advancing the development of LTCC technologies in the field of electronic integration.

Abstract:
With the rapid development of 5G wireless communication and Internet of Things (IoT) technologies, there is a growing demand for communication modules featuring high frequency, low latency, miniaturization, and massive connectivity. Low-temperature co-fired ceramics (LTCC) have emerged as key materials in 5G and millimeter-wave systems due to their excellent high-frequency characteristics, high integration capability, and co-firing compatibility with internal electrodes. Compared to commercial substrates such as Rogers 4003C (organic composite) and DuPont LTCC (which require high sintering temperatures and costly gold electrodes), the oxide-based LTCC developed in this study demonstrates both low-temperature sintering and stable microwave dielectric properties, making it suitable for high-frequency PCB and multilayer module applications with improved cost and environmental benefits.
In the first stage, ZnMoO4-based ceramics were synthesized via solid-state reaction, and partial substitution of Zn2+ with Mg2+ formed the Zn1-xMgxMoO4 system. Dielectric properties and sintering behavior were systematically evaluated. The x = 0.06 sample sintered at 770 °C for 2 hours showed εᵣ = 8.65, Qf = 59,000 GHz, and τf = −62.18 ppm/°C, indicating high-Q performance with low-temperature sinterability. To further improve thermal stability and achieve temperature compensation, TiO2 known for its high permittivity and positive τf was incorporated to form the (1−y) Zn0.94Mg0.06MoO4–yTiO2 composite system. At y = 0.13 and sintered at 780 °C, the optimized composition exhibited εᵣ = 9.8, Qf = 42,800 GHz, and τf = −3.41 ppm/°C, achieving both near-zero temperature coefficient and low dielectric loss.
For application verification, a filter was designed based on a 2020 IEEE reference circuit featuring one low-pass and two band-pass responses. The second band-pass center frequency was modified to 3.5 GHz (Sub-6 band), and a band-pass filter was fabricated using the developed LTCC substrate. Its performance was benchmarked against three commercial substrates: Rogers 4003C, FR4, and Al2O3. Results demonstrated that the (1−y)Zn0.94Mg0.06MoO4–yTiO2 substrate enables circuit miniaturization, reduced insertion loss, and improved frequency stability with near-zero τf behavior.
Moreover, this material can be co-fired with low-cost Ag electrodes at low temperatures without the need for expensive gold electrodes or nitrogen atmosphere, significantly reducing process costs and carbon emissions. It shows excellent compatibility with green manufacturing and is well-suited for large-scale PCB production. Finally, a Sub-6 GHz band-pass filter was successfully fabricated using the developed LTCC material, and the experimental results matched well with simulations, confirming its effectiveness in high-frequency applications and demonstrating its potential as a next-generation LTCC substrate for high-frequency modules.
Keywords: Low Temperature Co-Fired Ceramics; Dielectric Ceramics; 5G Filter; Low-Carbon Processing; Cofiring Compatibility; High-Frequency PCB Applications

 

Bio:
I'm Po-hsiang Juan from Tainan, Taiwan. I'm the master student from NCKU MSE. Our lab, NEXT-G, focus on electronic packaging, battery and so on. And my research is about thermal interface materials.

Abstract:
As electronic products continue to evolve toward lighter and more compact designs, chip dimensions have also been continuously shrinking. This results in a significant increase in the number of transistors per unit area. This trend aligns with Moore’s Law, which states that the number of transistors on a chip doubles approximately every two years. To meet the demands of such high-density components, traditional two-dimensional (2D) packaging based primarily on wire bonding has gradually become inadequate in terms of performance and spatial requirements. As a result, packaging technology has been steadily advancing toward three-dimensional integrated circuits (3D ICs). At the same time, as chip functionalities grow more powerful, power consumption has also continued to increase. The power consumption of Central Processing Unit (CPU) has risen with each new generation. This means higher power density in the same or even smaller volume, which not only leads to increased temperatures inside the package but also causes chips to operate under high thermal stress, potentially resulting in reduced performance or even lower reliability.
Efficient dissipation of the heat generated within a chip has become a critical challenge in the field of electronic packaging. Among various thermal management strategies, thermal interface materials (TIMs) play an essential role in the thermal conduction path. Their performance directly influences the overall thermal management efficiency and long-term reliability of electronic systems. When two solid surfaces come into contact, the actual physical contact area is limited due to microscopic surface roughness even if the surfaces appear smooth on a macroscopic scale. The gaps formed by this roughness are typically filled with air, which has extremely low thermal conductivity. This creates a significant thermal barrier at the interface, reducing heat transfer efficiency. TIMs are designed to fill these micro-gaps, replacing the air and increasing the real contact area. This facilitates smoother heat flow from the heat source (e.g., the chip) to the heat-dissipating component (e.g., the lid or heatsink), effectively reducing interfacial thermal resistance and improving overall heat dissipation performance.
In this study, we use Indium as TIM. First, a die/In/die sandwich structure was fabricated using thermal compression bonding (TCB) method. Use SAT to scan the interface to make sure indium and substrate are well-bonded. Subsequently, cross-sectional analysis will be performed to examine the interface. Scanning Electron Microscope (SEM), Energy-Dispersive X-ray Spectroscopy (EDS), and Electron Probe Microanalyzer (EPMA) were used to analyze the microstructure and identify the phases. The thermal resistance was measured by ASTM D5470 method. We investigate the interfacial reaction of die/In/die sandwich structure and examine how different bonding parameters affect the interfacial reactions. By comparing the relationship between interfacial reaction and thermal resistance, we can determine which bonding condition yields the best overall performance.

 

Bio:
Huan-Ping Chao is a professor in Department of Environmental Engineering, Chung Yuan Christian University, in Taiwan. He received his Ph.D. degree from Graduate Institute of Environmental Engineering, National Taiwan University, in 2003. His research interests include adsorption, volatilization, environmental contaminant analysis, and remediation of soil and groundwater, and solid waste management. At present, his research focuses on (1) developing new adsorbents for removal of various contaminants, (2) establishing a theory of volatilization and discussing the volatilization mechanisms of organic compounds from water, (3) developing new techniques for the remediation of soil and groundwater. Up to now Prof. Chao has published more than 60 papers in reputable-journal and two book chapters. Also, he is a regular reviewer for many prestigious environment-focused journals in different publishers.

Abstract:
The contaminants eliminated in wastewater could reduce the impacts of contaminants on the environment. If these contaminants can be recycled, the enterprise can provide sustainable development for the environment. The wastewater from printed circuit board industries often contains contaminants such as copper ions and color. Thus, a new adsorbent removing both copper ions and dyes was developed in this study. The calcium aluminum layered double hydroxides (Ca-Al LDHs) was applied in the adsorption of copper ions and organic dyes. Ca-Al LDHs has attracted widespread attention in recent years due to its unique layered structure, high adsorption amounts of contaminants, and relatively low synthesis cost. In addition, the Ca-Al LDHs can adsorb cationic and anionic contaminants through different adsorption mechanisms to simplify wastewater treatment process.
In this study, Ca-Al LDHs was synthesized using coprecipitation process. Tow kind ratios of calcium to aluminum (3:1 and 4:1) were selected to produce the Ca-Al LDHs. The Ca-Al LDHs before and after adsorption were characterized by were characterized by Scanning electron microscopy (SEM), BET surface area, Fourier transform infrared spectroscopy (FTIR), XRD, and X-ray photoelectron spectroscopy (XPS). Then, the Ca-Al LDHs were used to adsorb copper ion, cationic dyes (methylene blue and methyl green) and anionic dye (methyl orange) in the various pH (3, 4, 5, 7 and 9) solutions. The adsorption amounts of test contaminants on the Ca-Al LDHs were estimated by Langmuir equation. In addition, in-situ synthesis processes for the LDHs were also applied to remove the test contaminants. 1000 mg/L of contaminants were used to test the removal rates in the process for the LDHs synthesis. Three concentrations of chemicals for the in-situ synthesis were added the solutions to measure the removal rates in the given periods.
The results showed the two Ca- Al LDHs before adsorption have the similar SEM images, XRD spectra and FTIR spectra. The result demonstrated the Ca- Al LDHs have been synthesized successfully. The difference in XPS and BET surface area represented the diversity of adsorption efficiencies on the selected contaminants.
The equilibrium adsorption experiments presented the data can fit Langmuir model well. Moreover, the maximum adsorption capacities of selected contaminants on the LDHs can be estimated by the Langmuir equation. The adsorption amounts of methyl orange and copper ion increase with the decreasing pH values. The adsorption amounts of methyl blue and methyl green are less-important with the pH values of solutions. The maximum adsorption capacities of copper ions, methylene blue, methyl green and methyl orange in various pH solutions are 480, 1293, 1408 and 2451 mg/g. The primary adsorption mechanism of copper ion is surface precipitation. The primary adsorption mechanisms of methylene blue and methyl green are hydrogen bonding, van der Waals force and surface precipitation. The primary adsorption mechanism of methyl orange is electrostatic force or ion exchange. The result in the in-situ synthesis demonstrated the Ca-Al LDHs can be used in the realistic wastewater. The removal rates of test contaminants can reach 80% within 4hr.

 

Bio:
Bryant Tsai is a Senior System Power Design Engineer at Intel Corporation, based in Taiwan. His work focuses on supporting customers in designing stable, reliable, and optimized power delivery systems for Intel’s data center platforms. With a strong background in power integrity, system-level design, and cross-functional collaboration, he plays a key role in enabling scalable and efficient power architectures for next generation server solutions. Bryant has extensive experience in system validation, power delivery network (PDN) optimization, and customer enablement across global markets. He is passionate about bridging the gap between silicon design and real-world deployment, ensuring robust performance under diverse workloads and operating conditions.

Abstract:
As Artificial Intelligence (AI) workloads drive unprecedented power demands in modern data centers, efficient power delivery has become a critical design priority. Traditional approaches such as increasing PCB copper thickness or adding layers are reaching physical and economic limits. This paper introduces an advanced copper foil (ADCF) solution that significantly reduces DC resistance compared to conventional Reverse Treated Foil (RTF) foils, thereby enhancing power efficiency. Through theoretical modeling, test vehicle validation, and system-level simulations, the study demonstrates up to 7.4% power loss reduction using ADCF. This translates into substantial electricity cost savings and carbon emission reductions in large-scale AI server deployments. By improving conductivity and minimizing energy loss, this innovation supports the broader goal of sustainable power efficiency in next generation data center infrastructure.

 

Bio:
24 years of work experience at USI QMD/QA Engineer → QA Section Manager (2000~2006)-> Staff Administrator(2009)→Prof. Manager (2015)->Associate Director (2019)→ Director (2021~) Main Job function: 1. Own Global IE&PC for WW Capacity Plan and Drive WW Mfg. Utilization and Efficiency, and Cross-Site Capacity Allocation 2. Survey New sites, New Building Facility Layout. Join M&A, Due Diligence, Synergy post M&A 3. Review Capex, Save Capex by Cross-Site Alloca-tion; Cross-Site Product/Equipment Transfer

Abstract:
In previous studies, SFIS and SAP data have been used to present SMT OEE, achieving global standardization of factory data standards. Excel data is pushed monthly through automated reporting systems, but only the previous month's data can be sent at a fixed time each month, which is not conducive to on-site management and timely improvement. This upgrade utilizes Azure Analysis Services (AAS) for big data modeling and preprocessing and uses Power BI to connect AAS models to generate interactive OEE dashboards. Users can set their own conditions to view reports at any time, as well as analyze the root cause of OEE anomalies independently. They can quickly seek improvement and provide accurate historical data for quotation.

 

Bio:
Education： 1995.9-2000.10 Ph.D in Electronic Engineering, National Chiao Tung University 1992.9-1994.6 Master of Applied Chemistry, National Chiao Tung University Experience： A. 2017/8~Now National Ying Ming Chiao Tung University Post Doc. Research B. 2010/11~2016/02 UMC New Business Company, Manager I. Compound Semiconductor manufacture Foundry (III-V MMIC RF device manufacture) II. 3D IC package C. 2000/11~2006/10 & 2007/03~2010/08 (UMC), Technical Manager

Abstract:
In this study, the feasibility and the QRcode ecosystem are demonstrated with semiconductor processing and advanced packaging supply-chains. The QRcode Mcells are auto-generated via decent CAD flow automation, as this illustration. We can create different QRcode per wafer, per photo-shot and split-patterns, especially for good potential in maskless, sub-millimeter, sip-process usage (in wafer or panel form), it is “traceability” in SiP supply-chain management. We included design splits: same QRcode/pitch with 3 square sizes for 2 µm x 2 µm ; 3 µm x 3 µm and 4 µm x 4 µm, to emulate various process variations. The design for the QR-code combined with two layer. The process DOEs include single exposure (1P, separate layers) and double exposure (2P, single layer), and verified by both SEM and OM (optical microscope), on different film stack/substrates: One was the oxide-on-PR-on-silicon; Others were Ta-on-glass substrates.
The core idea is to use a single controller on the photomask machine to directly generate the QR code onto a programmable mask-reticle, enabling an in-process, closed-loop automation flow. While we can't fully replicate this process in a small SBIR project without the equipment vendor's endorsement, this proof-of-concept (POC) project is an excellent starting point for promoting "SiP traceability" in future SiP and related industry practices. Our CAD flow can auto-generate the QR code Mcell variance, but it can't link with the tool itself.
The QRcode read-out is “JBeGeLlqZTF” correctly, via some software improvements (e.g. machine learning for noise refinement, fuzzy matching, transparent algorithm, etc)

 

Bio:
I am currently a master’s student in the Department of Materials Science and Engineering at National Cheng Kung University. My research focuses on electromigration phenomena and microstructural evolution in Au thin films used in electronic devices. My work involves investigating lattice instability, grain growth, and dislocation density changes, aiming to develop methods for early detection of electromigration-induced damage. In this conference, I will present my work titled “Early Detection of Electromigration-Related Lattice Instability in Au Strip.”

Abstract:
Understanding current-induced degradation in metallic interconnects is essential for improving the reliability of advanced PCBs. In this work, we investigated irreversible lattice deformation in FCC Au strips under electric current stress (ECS) using in-situ synchrotron X-ray diffraction (SR-XRD). A clear threshold was observed at ~1.04 × 10^6 A/cm^2, beyond which the (111) reflection showed irreversible d-spacing expansion, absent under thermal-only conditions. This confirms a non-thermal origin, attributed to electron wind force. The expansion was crystallographically anisotropic and unrecoverable after post-heating, indicating field-induced lattice distortion rather than elastic strain. No phase transformation or hillocking was observed, highlighting Au’s distinct response compared to Cu and Al. This study establishes SR-XRD as a powerful diagnostic tool to detect early-stage lattice instability prior to failure.

 

Bio:
Jeff Chen, graduated from Mechanical Engineering Dep., NYUST in 2002 and started to work in USI as a manufacturing engineer from 2004. He has the experience on board and system assembly. Currently, he focuses on SiP new process and technology in COD

Abstract:
Jumper is a kind of compact metal or plastic cap connector, which is mainly used for short circuit or jumper operation on the circuit board of electronic devices to achieve specific circuit configuration or function selection. The automatic jumper machine arranges the irregular incoming materials orderly through the vibrating plate.The pressure self feedback sensing technology is applied to accurately control the distance and pressure with the electric cylinder, so as to realize the full-automatic jumper insertion instead of manual operation, and improve the production efficiency and quality. Currently, it has been widely used in mass production.

 

Bio:
I'm master student from NCKU

Abstract:
Silver is excellent electrical conductivity; this property makes it to be an ideal material for various electronic and optoelectronic applications. However, its high-cost limits large-scale usage, especially in applications requiring extensive coverage. To solve this challenge, fabricating silver in the form of thin films offers a cost-effective strategy that retains its superior conductivity while significantly reducing material consumption. In this study, a galvanic reaction-based method is employed to efficiently deposit silver thin films, providing a simple, low-cost approach for scalable silver utilization. Galvanic reaction is a type of electroless redox reaction that occurs at the interface between a solid substrate and a solution containing metal ions. This process is driven by the difference in standard reduction potentials, where the substrate undergoes spontaneous oxidation while metal ions in the solution are reduced and deposited onto the surface. To further control the morphology of the deposited layer, polyvinylpyrrolidone (PVP) is introduced as a structure-directing additive. The addition of PVP significantly influences the nucleation and growth behavior of the metal crystals, effectively suppressing dendritic structures and promoting the formation of dense, uniform films composed of near-nanoplate morphologies. Given that the Ag⁺/Ag redox pair has a higher standard electrode potential (+ 0.799 V) than the Cu²⁺/Cu pair (+ 0.337 V), galvanic replacement readily occurs when copper substrate is immersed in AgNO3 solution. A series of experiments were conducted using Ag⁺ solutions of varying concentrations, and the results are presented in Fig. 1. In the absence of polyvinylpyrrolidone (PVP), the deposited silver exhibits poor surface coverage and predominantly cluster-like morphologies rather than plate-like structures. In contrast, when PVP is introduced into the galvanic reaction system, the crystallization of silver dendrites is effectively suppressed. This morphological control is attributed to the steric hindrance imparted by PVP and the reduced mobility of Ag⁺ ions in the more viscous medium, which together promote the formation of discrete Ag nanoplates and polyhedral particles. As the Ag⁺ concentration increases from 1 mM to 50 mM, a notable improvement in surface coverage by silver is observed. However, extended reaction times at higher concentrations lead to the co-growth of Ag dendrites alongside nanoplates, with dendrites often emerging from the preformed Ag plates. This indicates that at 50 mM, the amount of PVP present is insufficient to fully suppress dendritic growth. Increasing the PVP concentration in such high-Ag⁺ systems may further inhibit the formation of undesired dendritic structures. The experimental parameters—including reaction time, silver nitrite concentration, and the content of PVP—play critical roles in determining the thermodynamic and kinetic pathways of the reaction, as well as the resulting morphology and microstructure of the deposited silver.

 

Bio:
My name is An-Yu Huang. I am a graduate student in the Department of Materials Science and Engineering at National Cheng Kung University (NCKU), Taiwan. My research focuses on electronic packaging technologies, particularly the electroplating of liquid metals and low-temperature bonding techniques. I am currently leading a collaborative industry-academic project between NCKU and ASE Group, aiming to advance next-generation 3D IC packaging solutions.

Abstract:
During the high-temperature bonding process in heterogeneous integration, undesirable warpage often occurs due to the mismatch in the coefficient of thermal expansion (CTE) between different materials. Therefore, reducing the bonding temperature is an attractive strategy to mitigate thermal stress and improve structural reliability. Transient Liquid Phase Bonding (TLPB) is a key technology that utilizes low-melting-point metals (such as indium (In) and gallium (Ga)) as bonding fillers to interconnect high-melting-point materials (such as copper (Cu) and nickel (Ni)). In the TLP bonding process, the low-melting-point interlayer melts and reacts with the substrates, forming high-melting-point intermetallic compounds (IMCs). These IMCs offer excellent thermal and mechanical stability, ensuring strong metallurgical bonding. TLPB combines the low-temperature wetting characteristics of liquid metals with the long-term reliability of solid-state joints, effectively addressing the CTE mismatch issue in 3D IC packaging. It also overcomes critical challenges under extreme operating conditions, such as high current density, thermal cycling, and power dissipation, making it a promising solution for next-generation heterogeneous integration.
Electroplating is a well-established thin film deposition method, and gallium (Ga) is a highly promising material for TLPB. However, Ga electroplating has not been widely adopted in the industry due to its inherently low current efficiency. This inefficiency is mainly attributed to the lower reduction potential of Ga³⁺ compared to H⁺, which leads to competitive hydrogen evolution reactions (HER). These reactions significantly suppress the reduction of gallium ions and result in a low gallium metal deposition rate. In this study, we demonstrate how to suppress HER by adjusting the parameters of the electroplating solution. By modifying the ratio of Ga to complexing agents and adding pH buffer additives, we achieved a nearly 40% improvement in current efficiency. The morphology and composition of the Ga layer were characterized using SEM, EDS, and EPMA; functional groups were analyzed by FTIR; and the mechanical properties of the Ga layer were evaluated using nanoindentation. Additionally, we investigated the violent bubble formation observed during the electroplating process, aiming to fully suppress the hydrogen evolution reaction (HER). As a result, this study achieved a current efficiency of 82% for Ga electroplating, successfully suppressing the bubble formation during electrodeposition and overcoming the long-standing challenge of low current efficiency in Ga electroplating. We propose a high-current-efficiency Ga electroplating method and confirm that Ga electroplating is a promising TLPB technology capable of effectively addressing the CTE mismatch issue in advanced electronic packaging.

 

Bio:
I work at the Industrial Technology Research Institute in Hsinchu, and my department is the High Frequency - Wide Band Substrate Materials Laboratory. I have a master's degree and graduated from National Chung Cheng University.

Abstract:
With the accelerating development of application technologies such as artificial intelligence servers (AI Server), high-performance computing (HPC), network communication equipment, and the Internet of Things (IoT), the IC substrate materials market is poised for rapid expansion. In response to the growing demand for next-generation computational power, advanced substrates must offer high-speed data transmission, low signal latency, and low power consumption to meet future performance and system requirements. To meet the demands of high-performance computing, advanced wafer fabrication processes are integrating chips of varying nodes and functionalities into a single device, offering IC designers greater flexibility in system architecture. In addition to continuous node scaling down, advanced packaging technologies such as 2.5D, 3D integration, and chiplets are being employed to heterogeneously integrate these smaller dies. This approach allows for more compact circuit layouts and increased interconnect layer counts to support higher I/O density requirements.
In the realm of high-frequency, high-speed signal transmission, performance degradation arises not only from dielectric losses but also from the pronounced skin effect in copper conductor layers. Moreover, as the number of stacked layers in substrate designs increases, the build-up dielectric materials also require high glass transition temperatures (Tg) and low coefficients of thermal expansion (CTE) to mitigate interlayer warpage, signal instability, and performance loss under high-frequency, high-speed operation. Thus, build-up materials for advanced applications must exhibit a low dielectric constant, low dissipation factor, and high thermal stability to ensure the signal integrity and reliability of the final IC substrate.
In this study, a novel build-up material was investigated using a hybrid resin system composed of a rigid thermosetting resin and a low-polarity resin. By systematically designing the resin components and fine-tuning the formulation, a series of film materials was obtained. These materials exhibit a low dielectric constant (Dk 2.98–3.08 @10 GHz), low dissipation factor (Df 0.0018–0.0029 @10 GHz), low coefficient of thermal expansion (CTE = 16–29 ppm/°C), and high glass transition temperature (Tg = 170–180°C). Furthermore, using a semi-additive process (SAP)—including electroless copper plating, photolithography, and electrolytic copper plating—the material was fabricated into a multilayer substrate. The insertion loss of the complete build-up substrate was then measured under various frequency conditions to evaluate the signal transmission performance of the multilayer configuration.

 

Bio:
Chiew Yee is working in Intel Platform System Engineering team as Systems and Hardware Enabling Engineer responsible for HSIO electrical and functional validation and customer issue debug

Abstract:
As the datacenter industry grows rapidly and high-speed signal data rate increases to support the demands from Artificial Intelligent (AI) server, the channel design of multiple connectors topologies of high-speed interconnect (HSIO) is utilizing the cable assemblies with riser or high-speed backplanes to provide the flexibility to connect and manage multiple PCIe switches end devices such as storage, network and graphic components. The optimization of cables used in the high-speed channel design in high dense AI server design is crucial to ensure the quality of the high-speed signals with low bit error rate (BER).

Flat cable consists strands of high-speed differential wires bundled in parallel ribbon to form a flat surface while the conventional round cable has strands of wires twisted around each other to create a round cylindrical shape. Two types of HSIO cables with round shape with length 360mm and 720mm and flat shape with length 380mm were used in a HSIO channel 3 connectors topology on a datacenter platform for Signal Integrity (SI), Electrical Validation (EV) and Functional Validation (FV) characterization.

The cable is a Y-type cable with one end consist of a Mini Cool Edge (MCIO) connector with x8 lane width connected to the main board (MB) and splitting into two ends of MCIO x4 lane width connected to the high-speed backplane (HSBP) with the PCIe Gen5 x4 Enterprise and Datacenter Standard Form Factor (EDSFF) Solid State Drive (SSD) connected for EV and FV testing. In the SI measurements, the EDSFF SSD and CPU are not included in the impedance and loss analysis with the assumption that delta of CPU and end device loss across various lanes are negligible.

In the EV characterization, the timing and voltage margin of the CPU Receiver (Rx) were collected using flat and round cables, whereby the voltage margin result shown on Figure2 that the round cable with longer length has better voltage margin than the flat cable. The performance throughput of the HSIO channel is measured using Flexible IO (FIO) Tester application. Per Table1, all types of cables are showing similar IOPS test result.

In the SI characterization, flat cable is showing higher insertion loss compared with the round cable with the similar length. Flat cable is showing lower via impedance and greater impedance mismatch with MB (~8ohm) while round cable has better impedance mismatch (~3ohm).

In summary, flat cables provide better flexibility of the cable management in a dense datacenter AI server fleet with the expenses of higher loss, greater impedance mismatch with MB and lower electrical margin. As the channel design are within the specification guideline and receiver is well equalized, the performance throughput of the flat and round cables is comparable.

 

Bio:
Currently a first-year graduate student in the Department of Electrical Engineering at National Formosa University, focusing on the fault diagnosis of Interior Permanent Magnet Synchronous Motors (IPMSM), with an emphasis on spectral analysis methods. The research aims to explore the relationship between electromagnetic signal characteristics and motor fault patterns, in order to improve diagnostic accuracy and system reliability. Current work involves frequency-domain feature extraction, anomaly detection techniques, and validation through hardware implementation. Future research will focus on integrating these diagnostic approaches into intelligent drive systems to enable real-time monitoring and fault prevention.

Abstract:
This study addresses the challenges of performance monitoring and fault prediction in Interior Permanent Magnet Synchronous Motors (IPMSMs) for smart industrial and precision drive control applications. A highly integrated control system with driving, monitoring, and diagnostic capabilities is developed, featuring both hardware and software components. The hardware comprises a custom-designed control core PCB, power stage board, and multifunctional interface board. At the heart of the system is the TMS320F28335 digital signal processor, which, in combination with analog and digital signal conversion components, enables motor drive signal generation, sensor data acquisition, data transmission, and real-time processing. On the software side, a human-machine interface (HMI) is integrated to provide real-time visualization of d-axis and q-axis current waveforms, allowing operators to monitor current fluctuations and identify potential anomalies during motor operation.
To further enhance the system’s capability in evaluating operational conditions, a Fast Fourier Transform (FFT) algorithm is implemented within the TI Code Composer Studio development environment. The algorithm performs frequency-domain transformation and feature extraction on the d-axis and q-axis currents generated during motor operation, establishing spectral indicators for fault detection. Signal spectral characteristics are then compared and analyzed for anomaly trends. This method is effective in early identification of abnormal conditions caused by bearing wear, magnetic circuit asymmetry, or load variations, thus improving the feasibility and accuracy of predictive maintenance strategies.
Moreover, the system incorporates a spectrum analyzer and near-field probes to perform field measurements of electromagnetic signals under actual operating conditions. By observing the near-field radiation and electromagnetic response of critical regions on the PCB, the system's stability and electromagnetic compatibility (EMC) characteristics can be further assessed. Comparing the measured spectra with simulated frequency responses facilitates the identification of potential sources of interference and high-frequency noise, providing guidance for optimizing PCB layout and filtering design.
Experimental results confirm that the developed system can reliably execute motor control and real-time current monitoring. The integrated frequency-domain diagnostic algorithm effectively captures critical abnormal signals during operation and demonstrates strong diagnostic robustness and system responsiveness across various load and speed conditions. The overall system offers a high degree of integration, modular architecture, and good scalability, making it suitable not only for IPMSM motor control but also for broader applications in high-performance electric motor monitoring systems.
This research provides a valuable reference for the development of motor health monitoring and intelligent control systems in Industry 4.0 environments. Future enhancements may involve integrating machine learning and artificial intelligence techniques to strengthen automated fault diagnosis and decision-making capabilities, paving the way for advanced smart predictive maintenance platforms.

 

Bio:
Yu Ching Tseng received the bachelor’s degree from National Taiwan Normal University, Taipei, Taiwan, in 2016. She is currently pursuing the master’s degree in electronics engineering at National United University, Miaoli, Taiwan. Her research interests include microwave measurement techniques and the extraction of electromagnetic parameters of materials.

Abstract:
Please refer to the attached file of abstract.

 

Bio:
Tz-Cheng Chiu received the Ph.D. degree in mechanical engineering from Lehigh University in 2000. He is currently a Professor of the Department of Mechanical Engineering at National Cheng Kung University in Taiwan. His research interests are on material characterization and reliability simulation for advanced packages, in particularly in the areas of fracture mechanics, nonlinear mechanical behaviors, and finite element simulation.

Abstract:
2.5-D integration of logic and high-bandwidth memory (HBM) using fan-out (FO) redistribution layer (RDL) is one of primary choices for high-performance computing applications. The multilayered RDL typically consists fine-pitch Cu lines and polyimide (PI) dielectrics, which allows higher number of electrical input/output and faster signal transmission and. However, the risks of cracking or debonding failure in the RDL are higher under thermal stresses experienced during packaging processes or in-use conditions due to the increased overall package size and the higher density of dissimilar materials arrangements. For the purpose of evaluating the risk of debonding failure under temperature cycling reliability test, it is important to evaluate the debond driving force and the interactions of the defact and RDL Cu pattern.
In this study, a fracture mechanics based 3-D global-local finite element model is developed to investigate the debonding growth driving force of the RDL Cu-trace and PI-dielectric layers in a 2.5-D package. In this model, the growth of cracking defect occurs both at Cu-PI interface and through PI. The driving forces for crack growth under temperature cycling thermal stresses are estimated. Results of the global analysis of the 2.5D package showed that the stress concentration region in the RDL are at the corners of the logic and HBM chiplets. From the perspective of the overall package configuration, the high-risk area of cracking failure is mainly around the periphery of each individual chiplet, as opposed to simply being judged only by the distance to neutral point at package center. From the subsequent crack growth driving force evaluation, it was shown that the RDL stress around the corner defect is mainly in shear, and the crack growth driving force is Mode-II and -III dominant. The shear stress induced rotations of the RDL Cu lines lead to variation in the crack driving force across each Cu line. Comparing the debond driving forces of each RDL layer interfaces, it was shown that the thermal stress induced defect growth in RDL is more likely to occur in layers close to the Si die than in layers close to the laminate substrate. This trend can be attributed to the high deformation mismatch between the Si die and the RDL. For RDL defect underneath the logic die, as the location of the defect moves closer to the corner of the die, the strain energy release rate increases, the Mode-I stress intensity factor decreases, and the Mode-II and -III stress intensity factors increase. The simulation procedure and results described in this paper can be applied to in the package design phase to the enhance the thermomechanical integrity and reliability of RDL.

 

Bio:
ZongYuan Wu has been with USI since 2019. He has experience working in China, Indonesia, and specializes in project management and Industrial Engineering. Since 2024, he joined the Digital Transformation Center to enhance internal processes with modern applications. Digital Transformation Center. Universal Global Scientific Industrial.

Abstract:
Develop a Mendix-based platform to manage and collaborate on changing customer requirements. The main data source is the Excel file updated regularly by the customers. There is no CRM system in the current system to integrate customer demand management, and this needs to be achieved through the internal development of auxiliary systems.
The data on the platform is highly sensitive and has a wide range of influences, so complete permission management is required for information dissemination: including price- related permissions, factory management permissions, work process review permission settings, etc., which are ultimately allocated and reviewed by platform administrators and factory administrators.
This platform will maximize the retention of basic fields as basic data and will also provide users with the option to choose file formats that meet the needs of different customers on the interface. And use the LSTM model to infer the profit-maximizing configuration.

 

Bio:
Jong-hyoung Kim is an Assistant Professor working in the Department of Materials Science and Engineering at Pukyong National University (PKNU), Republic of Korea, since 2024. Kim obtained his BS and PhD degrees in materials science and engineering from Seoul National University in 2012 and 2019, respectively. He was a postdoctoral researcher at Harvard University from 2019 to 2024. Kim can be reached by email at jhkim@pknu.ac.kr.

Abstract:
As semiconductor devices continue to scale down in size, advanced architectures such as 3D ICs and High Bandwidth Memory (HBM) increasingly incorporate complex geometries and multiple heterogeneous interfaces. These structures inevitably develop residual stresses due to factors such as thermal expansion mismatch, and lattice mismatch. Such stresses can lead to mechanical failures including cracks and delamination, ultimately compromising device reliability. In particular, the interplay between the thermal expansion mismatch of insulating and conducting layers and the heat generated during device operation can exacerbate residual stress levels. Therefore, a precise understanding and evaluation of stress distribution within advanced semiconductor devices is essential for ensuring their structural integrity and operational stability.

Conventional residual stress measurement techniques—such as wafer curvature, X-ray diffraction (XRD), and Raman spectroscopy—face significant limitations when applied to patterned 3D structures composed of ultra-thin films. These methods are often material-specific and lack the spatial resolution required for localized stress assessment. To address this challenge, a novel technique capable of measuring local residual stress in patterned thin-film structures is needed.

In this study, we propose an advanced version of slitting method that combines high-resolution Digital Image Correlation (DIC) with Focused Ion Beam (FIB) milling to precisely measure local stresses in thin films. Custom-designed DIC patterns are printed on the specimen surface using lithographic techniques. To protect these patterns during the FIB milling process, a sacrificial polymer layer is temporarily deposited. The deformation induced by stress relaxation around the FIB-milled slit is then captured via DIC analysis. Based on the measured deformation, specimen geometry, and material properties, a neural network-based model is developed to predict the residual stress fields. This approach enables accurate and efficient stress evaluation at the microscale.

In addition, finite element analysis (FEA) simulations were conducted to examine whether the deformation induced by stress relaxation follows a plane-strain condition when the aspect ratio of the slit exceeds a certain threshold. The simulation results were used to optimize the slit geometry for effective stress measurement. Furthermore, the influence of non-equibiaxial stress states was analyzed by investigating how stresses applied parallel to the slit axis affecting the resulting deformation. These insights provide a foundation for accurately interpreting complex residual stress states in semiconductor devices.

This presentation will introduce the theoretical background and experimental & computational results of the proposed method and discuss its potential to improve the mechanical reliability of advanced semiconductor devices.

 

Bio:
Currently serving as a project lead at NXP Semiconductors, with primary responsibilities in package-related evaluation, qualification, and design. Accumulated 6 years and 7 months of experience at NXP, complemented by 10 years of prior experience in assembly process engineering at ASE Group.

Abstract:
Handling small Ball Grid Array (BGA) packages during reliability testing presents significant challenges. To mitigate the risk of device loss and facilitate handling, the packages are mounted on a translation board. This approach is widely adopted, especially during temperature cycling qualification, a critical step in the product qualification process. To further secure the device and prevent mechanical damage, a cap-ring is incorporated into the translation board design. However, this modification significantly influences the test results, producing outcomes contrary to those observed in conventional board-level temperature cycling tests. Specifically, failures are concentrated in the central balls rather than the corners—a shift attributed to the mechanical stress introduced by the cap-ring. To investigate the root cause of this stress redistribution, a simulation is conducted. The results confirm that the altered stress distribution leads to increased stress concentration in the central solder joints, ultimately causing failure in those areas instead of the corners. This study also includes a comparative analysis of SAC105 and SAC405 solder balls under these test conditions, observed the SAC405 is extended the lifetime of temperature cycling test

 

Bio:
Tina Yang is currently a Platform Application Engineer in Data Center Group at Intel, responsible for high-speed interfaces design for server and workstation products. She received the M.S. in National Taiwan University of Science and Technology in 2012. She worked for Jabil from 2017 to 2019 and for Himax from 2019 to 2021. And she joined Intel Corporation as a signal integrity engineer for SI/PI customer enablement and support and technology development from 2021.

Abstract:
As high-speed Input/Output (HSIO) devices, such as servers and AI systems, designing channels on printed circuit board (PCB) has become increasingly complex and challenging. Ensuring data rate requirements is essential to meet the high bandwidth demands of Large Language Model (LLM) training Therefore, the Peripheral Component Interconnect Special Interest Group (PCI-SIG) defined the PCI Express Gen6 specification with a data rate of 64 GT/s in 2022, and the PCI Express Gen7 specification, with a data rate of 128 GT/s, is currently under development. From a board designers’ perspective, designing a system to fulfill the data rate requirements while reducing potential risks is becoming increasingly critical.

A methodology for testing the RX eye diagram, proposed in 2024, is based on PCB routing length and material. This approach enables board designers to efficiently evaluate design quality prior to finalizing the PCB. However, this methodology necessitates preparing various riser cards, potentially leading to extra cost. Alternatively, employing simulation over real measurements can more readily produce results and lower cost. In this paper, we aim to illustrate the simulation process and demonstrate its alignment with real measurements.

The purpose is to identify the differences in various PCB lengths and materials by simulation. The simulation needs to obtain real data from other areas within the end-to-end channel. For example, if the end-to-end channel includes cables, sockets, etc., we need to acquire loss data either from vendors or through measurement. In this study, we used measurements to obtain the loss data, aiming to closely approximate real system results.

After measuring the loss data from PCB, we can obtain different parameters and import them into simulation. By adjusting the EQ settings to generate diverse eye diagrams. In this study, we measured the end-to-end loss and applied 11 dB and 12 dB (matching the riser card loss in previous studies) to the PCB loss to observe changes in the eye diagram. The simulation results show that when an additional 11 dB is applied, the eye height/eye width is 18.5 mV/13.5 ps, which is within the PCI-SIG specification (18 mV/9.37 ps). However, after increasing the additional loss to 12 dB, the eye height decreases to 12.5 mV, which is below the guideline. These simulation results also corroborate the previous study. In real measurements, the results similarly show that using a 12 dB riser card causes the eye diagram to fall below the specification (16.43 mV, with the specification criterion being 17.5 mV). Utilizing this methodology provides a more cost-effective solution for designers, especially when compared to relying on conventional industry baseline criteria.

According to the above simulation and real measurement results, designers can comprehensively understand how to leverage simulation to optimize PCB design for high-speed I/O in AI systems. This simulation methodology offers PCB designers a clear approach to obtaining results across various PCB parameters, thereby enhancing confidence in meeting specification guidelines.

 

Bio:
Chiew Yee is working in Intel Platform System Engineering team as Systems and Hardware Enabling Engineer responsible for HSIO electrical and functional validation and customer issue debug

Abstract:
As the datacenter industry grows rapidly and high-speed interconnect signal data rate increases to PCIe Gen7 with Pulse Amplitude Modulation (PAM4) encoding, the board design is crucial to ensure the quality of the high-speed signal data transmission. Conventionally, in platform design and qualification stage, board design verification (DV), Signal Integrity (SI) and Electrical Validation (EV) tests are conducted to ensure the quality of the high-speed signal data transmission on the specific platform design. However, due to the cost and time constraints, board manufacturers may decide to omit some of the testing which may result in late found issues after platform post-production launch, such as PCIe link stability or data integrity issues that could potentially cause an outage in the datacenter fleet services. In this paper, a closed loop design and validation methodology for datacenter platform design which includes feedback loop and correlation of test results and issues found in DV, SI and EV tests is proposed and detailed case studies with including design, SI and EV analysis and correlation will be provided.
First, the layout of the board design revision1 will be checked against the predefined manufacturing and design constraints by automation tool to avoid the common PCB layout mistakes. Simulation of the board design should be performed to understand the electrical characteristics of the high-speed channel design before the platform in production. Any issues found from the checkers and simulation should be root caused and fixed in the design board before production.
Next, SI measurements should be performed on the productized board design revision1 by conducting end-to-end (E2E) loss and impedance characterization or through the Intel® Automatic In-board Characterization (AIBC) and Automatic Channel Characterization (ACC) testing to identify any outlier in the impedance. The SI measurements could be used to correlate to the board design layout and the previous simulation result conducted.
Lastly, EV tests should be performed across all high-speed channels with various end devices by obtaining the voltage margin and timing margin of receiver. Margin that is below the design guideline is considered low margin. Margin data analysis is required to understand the factors such as settings of component receiver equalization, high speed channel topologies and board designs that could contribute to lower margin performance and correlation with the previous board design verification and signal integrity testing could be done to understand cause poor signal integrity and provide fix proposal for future board design revision2.
With this closed loop design and validation framework applied on the datacenter board design, the components that could cause deterioration in the quality high-speed signal transmission are identified with risk assessment performed and enhancement to the high-speed channel design are developed and deployed to the board design revision2 as needed or fixes in the others component such CPU and end PCIe devices to ensure the health of the high-speed signal and datacenter fleet.

 

Bio:
Ben-Je Lwo is currently a Professor at Department of Mechanical and Aerospace Engineering, National Defense Univ., Taiwan

Abstract:
A newly developed glass-embedded fan-out, antenna-in-packaging (FO_AiP) structure, as shown in Figure 1, was previously proposed. Through ANSYS-HFSS simulation, the electromagnetic (EM) performance of the antenna designs has been demonstrated to be suitable for 5th generation (5G) millimeter-wave (mmWave) applications at 60 GHz [1]. In this study, a backpropagation (BP) artificial neural network algorithm, implemented in MATLAB, is used to improved electromagnetic behaviors of the antenna design. To this end, seven geometric dimensions of the antenna were first selected as design parameters, and a dataset of 300 records of electromagnetic performance from random combinations of these parameters was generated through HFSS simulations. Accordingly, the inputs to the BP algorithm are the seven geometric parameters, and the outputs are the antenna’s gain, bandwidth, and central frequency. As shown in figure 2, the BP model with five hidden layers was next selected as the neural network model of this study, and Adam optimizer was chosen as the optimizing algorithm. The PB model was then trained and validated using 280 records from the dataset, and accuracy of the BP model was subsequently verified using the remaining 20 records from test. After model verification, 78125 designs (i.e., 57, since there are five design levels for each of the seven parameters) were generated through combinations of geometric parameters. The 78125 designs were then input into the established BP model to predict the EM performance of each design. We next scanned and filtered the output of the 78125 records and selected the five best combinations of design parameters from BP model’s output. Finally, the antennas’ geometric dimensions from the best five records in the dataset were re-simulated using HFSS to verify the optimal FO_AiP designs.

 

Bio:
Thermal engineer

Abstract:
Nowadays, technology is growing rapidly in the semiconductor industry, driven by next-generation applications such as cloud computing networking servers, telecommunication devices, communication satellites, and automotive systems. Consequently, these applications demand high power performance in packages. As power levels continue to increase, heat dissipation techniques become increasingly critical. Thermal interface material (TIM) is a thermal pathway between the metal lid and die. To reduce thermal resistance of junction-to-case, bond line thickness (BLT) and thermal conductivity are key factors. In addition to maintaining high thermal performance, good reliability is an important characteristic of TIMs. In this study, we evaluated different types of TIM through reliability test, including Temperature Humidity Test(THT), Temperature Cycle(TC) and High-Temperature Storage (HTS). To compare these TIMs, a thermal test vehicle (TTV) was developed, providing detailed thermal characteristic of Heat Spread Flip Chip Ball Grid Array (HSFCBGA). TTV heaters were integrated into the die, and corresponding thermal sensors were distributed across the die to monitor changes in thermal resistance, which reflect temperature variations throughout the cycling process. The thermal measurement results from TTV were captured by Standard JEDEC thermal resistance equipment for junction-to-case thermal resistance. This study presents the thermal performance evaluation of TIM, summarized in Table1. TIMB showed significant advantages, including high thermal conductivity and good gap-fill capability. Compared with TIMA and TIMC, TIMC has twice the thermal conductivity of TIMA; however, the results show that their thermal performances are still similar. TIMD showed the best thermal performance among grease TIMs. The results also show that after Temperature Humidity Test(THT), Temperature Cycle(TC) and High-Temperature Storage (HTS) evaluation, the sample can maintain the original thermal characteristics. Also, TIM coverage has been verified via scanning acoustic tomography (SAT) after reliability testing. A series of thermal simulations was conducted based on a package thermal model constructed for the thermal test vehicle, which includes multiple heat sources. Verifying with thermal measurement, it’s shown that the thermal model can achieve highly accuracy. Comparing simulation and measurement results, thermal conductivity is not directly proportional to thermal resistance. Once thermal conductivity reaches a particular value, thermal resistance of trend is slowdown. In conclusion, verification and fundamental characteristic of thermal test vehicle was completed. It would be beneficial to achieve methodology in design part to reduce high thermal risk in high-power semiconductor system applications.

 

Bio:
Soo Hin is a Senior Thermal Mechanical Engineer for AMD Server Engineering Team and has 25 years of experiences in mechanical design in semiconductor industry. He started to involve in system thermal for server platform since he joined AMD in 2021. He has passionate and love to work with AMD server engineering team and collaboration across functional team to solve critical issue. Soo Hin has been married to Jenny for over 17 years and has one kid. As family they like to travel and enjoy food.

Abstract:
In recent years, rapid technological advances and the emergence of various solid-state drives (SSD) connectors in backplanes, such as EDSFF E1.S and E3.S, have necessitated unique designs for each SSD tray. This has contributed to increased non-recurring engineering (NRE) costs and longer lead times. The added challenge of validating different SSD types for SP7 Venice CPU performance compliance further complicates the process. This technical paper seeks to address these issues by introducing a versatile, small-scale common backplane chassis through design standardization and modularization, which ultimately reduces costs and development time while increasing flexibility.
This innovative design employs a shared SSD tray that accommodates 6 different thickness and types of EDSFF SSD, making it compatible with various backplane types. The backplane chassis consists of 8 SSD trays as modular and offering small scale to match 8 connectors on each backplane. Offering versatility, this design caters to both rackmount and benchtop platform systems, ensuring it can meet a range of application requirements. The SSD tray can be positioned vertically in backplane chassis for direct cooling from axial fan. Thermal simulation results indicate that the cooling solution provided in this design is sufficient to meet SNIA SSD Tcase specifications. Moreover, the consistent pitch of SSD connectors across different backplane types allows for the accommodation of up to 8 SSDs in a backplane chassis.
In summary, this paper presents a comprehensive solution for designing and validating a wide range of SSD types through the implementation of a common backplane chassis and common EDSFF SSD tray. This groundbreaking approach not only curtails NRE costs and lead times but also enhances adaptability and applicability across an array of system requirements.

 

Bio:
Seongkyu Choi is currently a master's student in the Department of Intelligent Robotics at Sungkyunkwan University, Suwon, South Korea. He received his B.S. degree in Mechanical Engineering from the Tech University of Korea, Siheung, South Korea. He is pursuing his M.S. degree through an academic–research collaboration between the Advanced Packaging and Reliability Innovation Laboratory at the Korea Institute of Industrial Technology (KITECH) and the Multiphysics System & Computation Laboratory at Sungkyunkwan University. His current research interests include the thermo-mechanical reliability of semiconductor packaging, particularly using Digital Image Correlation (DIC) and Finite Element Method (FEM) to analyze strain and warpage in advanced package structures.

Abstract:
With the rapid advancement of semiconductor packaging technologies, there is a growing shift toward heterogeneous integration, chiplet-based architectures, and large-area system-in-package (SiP) designs. These emerging trends, while enabling higher performance and functionality, also introduce significant thermomechanical challenges. In particular, the mismatch in the coefficient of thermal expansion (CTE) between dissimilar materials leads to warpage during thermal processing, which can generate localized strain at solder ball interconnections. This strain accumulation is increasingly recognized as a critical factor influencing the long-term reliability and service life of advanced electronic products.
Traditional methods for evaluating solder joint reliability often rely on destructive cross-sectional imaging or time-consuming thermal cycling tests. To address these limitations, this study proposes a non-destructive framework that quantitatively assesses the thermomechanical behavior of ball grid array (BGA) packages using digital image correlation (DIC) and finite element analysis (FEA).
Our research will focus on BGA packages with 400 µm solder ball pitch, which remain widely used in industry and serve as a suitable platform for analyzing package-level deformation mechanisms. Full-field 3D DIC will be employed to capture the global out-of-plane warpage of the package under controlled thermal loading, while 2D DIC will be used to extract in-plane strain distribution near critical solder joints. These experimental measurements will be compared against FEA simulations constructed with measured material properties, including Young’s modulus (via nanoindentation) and CTE (via DIC-based thermal expansion tracking). In this configuration, the warpage of the package acts as a displacement boundary condition on the solder ball interconnections, inducing significant strain particularly at the outermost joints, where the deformation is most concentrated.
A key objective of this study is to establish a clear correlation between experimentally measured warpage and strain fields and the corresponding simulation results. Through iterative tuning, we aim to validate the FEA model against DIC data to ensure consistency in both global warpage patterns and local strain behavior, thereby confirming the model's predictive capability.
Once validated, the FEA model will be utilized to investigate the relationship between warpage and strain across different geometric configurations and material settings. This is expected to reveal a robust and reproducible correlation between package-level warpage and solder joint strain, suggesting that warpage can serve as an effective proxy for interconnection reliability evaluation. This approach will potentially enable engineers to predict strain-induced reliability risks based solely on non-destructive warpage measurements
Furthermore, the FEA model to be validated in this study is expected to lay the groundwork for its practical application in optimizing package structures to reduce thermally induced warpage in next-generation electronic systems. By providing a reliable and accurate simulation framework, this methodology will allow engineers to virtually explore various design parameters and material combinations before physical fabrication. Such a predictive approach is anticipated to support more informed decision-making in the early design phase, ultimately contributing to improved reliability, reduced development costs, and a lower risk of solder interconnect failures during actual operation.

 

Bio:
Member of Technical Staff as Customer Solutions Engineer at AMD, where Fabian plays a key role in enabling and validating cutting-edge silicon solutions for global customers. With hands-on experience collaborating across cross-functional teams, he ensures the successful delivery of high-quality silicon and critical platform ingredients, tailored to customer requirements. Fabian has worked closely with numerous industry partners to bring complex products from early engagement through validation and deployment till product launch. His work bridges the gap between engineering and customer success, helping partners accelerate time-to-market and achieve robust platform readiness.

Abstract:
In the realm of the Server product development program, Server platform developers have expressed concerns on memory interface electrical healthiness. Server system design has grown more complex, leading to the need for stricter board design rules, more advanced circuit knobs tuning and increasing rigorous validation coverage. Consequently, post-silicon electrical validation of DDR5 is crucial in product release qualification for aggressive launch with an upright board design that supports sufficient list of approved DIMM vendor modules. In this work, we designed a data-driven automation system to collect and postprocess DDR margin metadata. By integrating design-on-simulation technologies and utilizing advanced testing and measurement techniques, we have enhanced the data management framework for HSIO margin data, facilitating efficient and actionable insights.

This paper presents a comprehensive analysis of memory configuration and design influencers. The study focuses on the impact of various design parameters on memory performances, specifically examining Vref and Delay margin influencers. Key influencers identified in the study include DRAM configuration, DIMM Channel, DIMM pitch, Via-In-Pad routing on SMT connector, PCB material, PCB layer routing and routing lengths which are crucial in understanding the variations in memory performance. These elements are analyzed to determine their influence on the VREF values for top margin and bottom margin, as well as Delay values for left margin and right margin, providing insights into how design choices can optimize memory configurations.

The metadata framework involves a detailed examination of memory routing layers, topology, and subchannel configurations, offering a granular view of how these components interact to affect overall system performance. The findings suggest that specific design parameters, such as PCB material and SMT VSS via count, play significant roles in influencing VREF values, thereby impacting the efficiency and reliability of memory systems.

The findings suggest that specific design parameters, such as channel routed on bottom microstrip on 14-layer PCB has reported poorer margin at the lower side which is close to the margin limit line. Besides, in order to get better margin, the key influencers suggested the use of 1Rx8 DIMM modules instead of 2Rx4 DIMM modules to gain ~10mv VREF bottom margin uplift.

Our comprehensive study serves as a pivotal study in the realm of memory configuration, offering a detailed exploration of design influencers and their impact on VREF values. The findings underscore the importance of strategic design choices in achieving optimal memory performance, paving the way for future innovations in memory technology

 

Bio:
Honglin Li is a junior student at the School of Eilte Engineer College, Dongguan University of Technology. His research interests focus on machine vision and pattern recognition.

Abstract:
For applications in autonomous driving, robotic navigation, and other intelligent system scenarios, traditional SLAM (Simultaneous Localization and Mapping) algorithms face critical challenges in dynamically separating camera motion from object motion within complex scenes, thereby leading to significant degradation in 3D model construction accuracy. This paper introduces an innovative 4D Gaussian splashing approach enhanced by time-scene flow technology, realizing precise dynamic scene modeling through multi-faceted technical innovations. It integrates advanced scene flow algorithm optimization with epipolar geometric constraint mechanisms to establish a robust spatiotemporal correlation model, enabling efficient estimation of complex camera motion parameters. Through novel optical flow field decomposition strategies, the method achieves effective decoupling of object dynamics from the scene flow framework. Furthermore, a four-dimensional Gaussian splashing model fusing 3D spatial dimensions with temporal dynamics is employed to dynamically characterize scene structures, complemented by a multi-layer motion compensation algorithm system to mitigate the interference of moving objects on 3D modeling.
This proposed methodology breaks through the modeling bottlenecks of conventional SLAM in dynamic environments, demonstrating remarkable improvements in real-time environmental perception and adaptive motion handling capabilities. It provides a more robust technical solution for intelligent systems to achieve precise environmental understanding in dynamic scenarios, showcasing significant application potential in fields such as autonomous vehicle navigation, robotic environmental mapping, and intelligent scene perception

 

Bio:
Jeong Yeonwook is a graduate student in the Department of Semiconductor Convergence Engineering at Sungkyunkwan University. His research focuses on thermal interface materials for advanced semiconductor packaging, with a particular emphasis on underfill and non-conductive film (NCF) materials.

Abstract:
With rapid advancements in cutting-edge technologies such as artificial intelligence (AI), fifth-generation (5G) wireless networks, and autonomous driving, semiconductor chips increasingly demand higher performance, faster processing speeds, and greater integration levels. Consequently, effective thermal management has emerged as a critical challenge to ensure device reliability and efficiency. Epoxy-based underfills, extensively utilized in flip-chip packaging due to their excellent mechanical stability, process compatibility, and ease of handling, traditionally employ silica (SiO₂) fillers. However, silica fillers possess inherently low thermal conductivity, which is insufficient for meeting the heightened thermal dissipation requirements associated with next-generation high-power semiconductor devices. Thus, alternative ceramic fillers with intrinsically high thermal conductivity, such as hexagonal boron nitride (hBN), alumina (Al₂O₃), and aluminum nitride (AlN), are being actively explored.
Among these ceramic fillers, hBN stands out for its exceptional thermal conductivity exceeding 300 W/m·K, excellent electrical insulation characteristics, low dielectric constant, and outstanding chemical and mechanical stability. Nonetheless, hBN’s intrinsic platelet-shaped morphology results in weak interparticle bonding, facilitating the formation of internal porosity when nano-sized particles aggregate into larger micro-sized spherical or fibrous structures. This porosity significantly diminishes both thermal conductivity and mechanical integrity. Conventional sintering methods alone typically struggle to achieve adequate densification and strong interparticle bonding, leaving residual pores and suboptimal thermal conduction paths.
To overcome these structural limitations, this study introduces Al₂O₃ precursors as effective sintering aids during the fabrication of hybrid hBN-Al₂O₃ composite fillers, dramatically enhancing particle neck formation and significantly reducing internal porosity. Micro-sized spherical fillers were fabricated via spray drying of slurries containing nano-hBN and Al₂O₃ precursors. Additionally, micro-sized fibrous fillers were prepared by electrospinning polymer-based solutions incorporating the same mixture. Quantitative evaluations through finite element method (FEM) analyses confirmed that the addition of Al₂O₃ substantially enhanced microstructural stability and thermal conductivity by promoting effective interparticle necking and minimizing internal voids.
Moreover, the blending of spherical and fibrous fillers in optimized ratios enabled the formation of extensive three-dimensional thermal percolation networks, markedly improving thermal conduction pathways compared to single-form fillers. FEM simulations further optimized these filler ratios, demonstrating that hybrid filler structures significantly outperform singular spherical filler systems in thermal conductivity. Furthermore, amino silane (APTES) surface treatment effectively introduced reactive amine groups (-NH₂) onto filler surfaces, substantially improving interfacial bonding with epoxy resins and reducing thermal interfacial resistance. Experimental measurements, corroborated by molecular dynamics (MD) simulations, quantified the effectiveness of these interfacial enhancements.
The developed hybrid spherical and fibrous hBN-Al₂O₃ fillers demonstrate significantly enhanced thermal conductivity, markedly reduced internal porosity, and improved interfacial compatibility with the epoxy matrix. These characteristics collectively highlight their strong potential as next-generation thermal interface materials for advanced underfill materials in high-performance flip-chip packaging.

 

Bio:
Wen-Chieh Tsao is currently a second-year master's student in the Department of Electronic Engineering at National Taipei University of Technology (NTUT). He brings several years of industry experience in process engineering and production management within the electronics sector. His current research centers on process optimization and low-frequency noise analysis of IGZO thin-film transistors (TFTs), with a focus on applications in back-end-of-line (BEOL) integration and 3D integrated circuits (3D-ICs).

Abstract:
In this work, we present a low-frequency noise (LFN)-based evaluation methodology for assessing the reliability of bottom-gate amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs) under different post-deposition treatments. As monolithic 3D integration demand low-temperature and BEOL-compatible devices, oxide semiconductors such as a-IGZO have emerged as promising candidates due to their excellent mobility and low thermal budget process compatibility. However, hydrogen incorporation during deposition and fluorine doping can significantly affect the device’s electrical performance [1], [2]. Improving electrical stability remains a key technical challenge. Therefore, this study investigates the low-frequency noise and interface trap characteristics of a-IGZO TFTs subjected to oxygen annealing at the back-gate insulator (BGI) and fluorine doping in the active layer.

 

Bio:
Sheng-Wei Tsai received the B. Sc. degree in electronic engineering from National Formosa University, Yunlin, Taiwan, R.O.C., in 2023. He is currently working toward the M.S. degree in the Institute of Precision Electronic Components, College of Semiconductor and Advanced Technology Research at National Sun Yat-sen University, Kaohsiung.

Abstract:
Advanced heterogeneous integration packaging (AHIP) often requires the creation of high aspect ratio TSVs in silicon substrates. Deep reactive ion etching (DRIE) is the main method currently used, especially under the requirements of precise diameters and fine pitches. Although it can achieve high aspect ratio vias, the processing of DRIE takes a long time and special masks need to be made for different designs, which is costly and limits the flexibility of design and production. In addition, DRIE uses fluoride gas, which produces waste gas and liquid treatment problems and is inconsistent with requirements of ESG environmental sustainability. Modern laser technology has made rapid progress and laser drilling method is regarded as a potential alternative due to its advantages of fast speed, high flexibility, low cost and no need for fluoride gases. It is in line with the trend of miniaturization and high performance of packaging. The industry is in urgent need of fast, flexible and environmentally friendly TSV manufacturing technology, but the existing laser technology applied in TSV production still needs to be optimized to meet the requirements of advanced packaging.
In the paper, we use two process approaches. In the first approach, a slightly larger via diameter is drilled on the surface of the silicon substrate with low energy laser. The purpose is to create a track with a larger via to guide the second high-energy laser to drill via more concentratedly. The second process is to drill a small-diameter through vias, and we use a 20-um laser beam to drill through the silicon substrate. Figures 2 and 3 show the results of making low taper ratio TSVs on silicon substrates using Ultrashort Pulse IR laser. The entrance via diameter (Din) on the top surface of the substrate is 19.7 µm, the middle via diameter and the exit via diameter (Dout) are 16.5 µm and 17.7 µm respectively. The entrance via taper is calculated as 0.229° on the top surface of the 250 µm (h) thick silicon substrate. This study uses Design of Experiments (DOE) to evaluate the effects of five key process parameters, including peak power, drilling time, pulse frequency, number of pulses, and focal plane position, on quality factors such as via roundness, taper, sidewall roughness, and heat-affected zone (HAZ). Analysis of Variance (ANOVA) is used to find out the significant factors affecting the experimental results, and Response Surface Methodology (RSM) is used to establish the optimal process parameters.

 

Bio:
Jhan Jhih-Syuan received the B.Sc. degree in Electrical Engineering from Tunghai University, Taichung, Taiwan, R.O.C., in 2023, She is currently working toward the M.S. degree in Institute of Advanced Semiconductor Packaging and Testing College of Semiconductor and Advanced Technology Research at National Sun Yat-sen University, Kaohsiung.

Abstract:
Applications of AI, automotive electronics, and 5G/6G wireless communications are driving the rapid development of heterogeneous integrated packaging that integrating various small chips (chiplets) and placing them on the same substrate have faced many challenges, among which power overheating and heat dissipation considerations have become the primary difficulties. Advanced heterogeneous integrated packages such as CoWoS use silicon substrate as a platform of interconnection of electricity for various chiplets. Silicon substrate faces problems with heat dissipation and warpage in packaging processes due to CTE mismatch of different package materials. Therefore, the development of glass substrates provides a viable option other than silicon substrates for high-frequency and high-density packaging. However, the thermal conductivity of glass substrate in advanced packaging has also become the next dilemma. Whether there is a material with a suitable CTE to avoid warpage issue and quickly dissipate heat has become the primary research goal.
Aluminum nitride (AlN) ceramic substrate has the potential to be a candidate besides silicon and glass substrates used in advanced heterogeneous integrated packaging. From the comparison of data in the table, silicon, glass, and AlN all have a coefficient of thermal expansion (CTE) suitable for packaging, where AlN has more excellent high thermal conductivity.
In this paper, a picosecond infrared (IR) laser with a wavelength of 1064 nm was employed to drill blind and through vias with a diameter of 50 um to 30 um on a 600 m thick AlN substrate. By combining different optical lenses and focal lengths, high aspect ratios of through vias with the values of 1:12 to 1:20 can be formed on a 600 um thick AlN substrate. Laser drilling quality factors such as via roundness, taper, sidewall roughness, and heat-affected zone (HAZ) will be examined and reported. Design of Experiments (DOEs) and ANOVA analysis are performed to evaluate the effects of process parameters, including peak power, drilling time, pulse frequency, number of pulses, and focal plane position, on these quality factors.

 

Bio:
Mr. Hao-Tse Lo is currently a master's student in the laboratory of Professor Masahiro Kozako in the Department of Electrical and Electronic Engineering at Kyushu Institute of Technology, Japan. His research focuses on polymer-based composite materials for applications in thermal conductivity and electrical insulation, particularly epoxy–alumina systems. He specializes in enhancing thermal conductivity through electric field-induced filler alignment and has presented his work at multiple academic conferences in Japan. Mr. Lo received his bachelor's degree from National Taipei University of Technology and is currently pursuing his master's degree at Kyushu Institute of Technology.

Abstract:
This study focuses on enhancing the thermal and electrical properties of epoxy-based insulating substrates through electric field-induced filler alignment. The orientation of alumina fillers in the thickness direction promotes thermal conductivity while minimizing filler content—thus mitigating issues such as increased viscosity, reduced moldability, and compromised electrical insulation that typically accompany high filler concentrations. To satisfy the key requirements of insulating substrates—thermal conductivity, electrical insulation, and heat resistance—a filler chain structure was formed prior to resin curing. Thermal conductivity was evaluated via the laser flash method, with calculations based on thermal diffusivity, specific heat capacity, and density. Dielectric constant measurements were conducted using an impedance analyzer. The thermal conductivity and dielectric properties of epoxy-alumina　composites with aligned fillers are presented and discussed, demonstrating the effectiveness of electric field-assisted alignment in enhancing overall substrate performance.

 

Bio:
I'm Andy Chang, is currently the R&D Engineer for Tong Hsing Electronic Industries, a manufacturer of ceramic substrate with metallization, and custom semiconductor packages. My current work is on DPC on ceramic design or other advanced electronic sensor devices. The products I contacted are Optical transmitters (Laser Diodes), RF/Microwave Devices, High power LED devices and Medical.

Abstract:
As the size of electronic devices continues to shrink and the demand for higher efficiency increases, the requirements for product reliability also rise, presenting greater challenges to material properties. While ceramic substrates offer excellent thermal conductivity, their brittleness makes thin substrates prone to cracking. Therefore, silicon nitride substrates, with superior thermal conductivity compared to glass and higher toughness than other ceramic substrates, have emerged as one of the optimal solutions to address this challenge.
Silicon nitride (Si₃N₄) has become a promising alternative to aluminum nitride (AlN) and glass substrates in advanced electronic applications due to their exceptional bending strength and fracture toughness. Compared to AlN, Si₃N₄ exhibits superior fracture toughness resistance and mechanical shock resistance, significantly reducing the risk of substrate cracking during fabrication and assembly processes. This leads to improved yield and enhanced product reliability. In contrast to glass substrates, Si₃N₄ offers higher thermal conductivity and structural robustness, and can withstand elevated temperatures and harsh thermal cycling conditions, making it particularly suitable for high-power or thermally demanding environments.

In thin-film circuit processes, Si₃N₄ substrates provide a low coefficient of thermal expansion (CTE), enabling precise and stable thin-film deposition and photolithography. These characteristics support the fabrication of high-density, high-accuracy resistors and conductor patterns. Si₃N₄ also delivers excellent electrical insulation, effectively isolating conductor layers to maintain signal integrity and improve product safety.

When applied in electronic systems, Si₃N₄ substrates significantly enhance heat dissipation and mechanical reliability, making them ideal for applications such as electric vehicle power modules, high-frequency communication devices, and laser modules that demand long-term operational stability. Overall, the combination of mechanical durability, thermal performance, and electrical insulation makes silicon nitride a critical material for next-generation high-performance electronic designs.

 

Bio:
Dr. Ching-Yu Liu is a Senior Engineer at the Industrial Technology Research Institute (ITRI) in Taiwan, specializing in MEMS sensors, semiconductor processes, and FEM simulation in solid and thermal mechanics. She earned her Ph.D. from National Tsing Hua University, focusing on spherical silicon chip technology for retinal prosthesis. Dr. Liu previously worked at Blickfeld GmbH in Germany on LiDAR sensor assembly, and served as Project Manager at Iridium Medical Technology Co. (IMTC), contributing to the development of a bionic artificial retina. With strong international and interdisciplinary experience, she is passionate about advanced MEMS devices and next-generation packaging technologies.

Abstract:
Haptic feedback has become one of the most important sensory interfaces, playing a critical role in enhancing user interaction across applications such as virtual reality (VR), augmented reality (AR), wearable devices, and advanced human-machine interfaces. A key challenge in this field is the development of thin, flexible, and integrable surfaces that can deliver rich and controllable tactile sensations. When a human finger slides over a textured surface, the resulting interaction force is composed of horizontal friction and vertical vibrations. Accurately reproducing this interactive force pattern enables the rendering of virtual textures that simulate real materials. Among the various haptic technologies, electroadhesion stands out due to its simplicity in structure and driving mechanism, making it a promising candidate for next-generation haptic feedback systems.
Traditional electroadhesive devices that incorporate dielectric layers often require high driving voltages—typically in the range of several hundred volts—and are susceptible to dielectric breakdown, limiting their long-term reliability and safety in interactive applications. To address these limitations, we propose a thin-film electroadhesive component that operates at low voltage while maintaining effective and tunable haptic performance. Our device is fabricated using a low-temperature process with polyvinylidene fluoride (PVDF), a high-permittivity dielectric polymer, and features thin-film electrodes to reduce thickness and improve mechanical flexibility. The system is designed to be controlled via a custom-built interface, enabling real-time adjustment of waveform type, pulse width, frequency, and voltage amplitude.
This flexibility allows the device to dynamically modulate the stiffness and adhesive forces experienced by the user’s fingertip, thereby rendering various surface textures and simulating different material sensations. To experimentally validate the performance of our device, we developed a customized friction force measurement setup, consisting of a robotic arm to apply controlled lateral motion and a precision force gauge to measure the resulting friction forces. The measurements indicate that the electroadhesive feedback force ranges from tens to hundreds of millinewtons, depending on the applied voltage and control parameters.
Additionally, we conducted finite element simulations using the same structural parameters and loading conditions to predict electroadhesive behavior. The simulation results showed excellent agreement with experimental data, with deviations less than 10%, confirming the reliability and accuracy of our design and modeling approach.
One of the key advantages of this electroadhesive component is its versatile integrability. Through pattern-based design and fabrication, the thin-film structure can be configured into various form factors. For instance, we developed a ring-shaped electroadhesive device capable of wrapping around or rotating beneath the finger. This flexible design enables seamless integration with other haptic feedback technologies, such as vibrational actuators or deformation devices, facilitating multi-modal tactile feedback in compact and adaptive formats.
Overall, this work demonstrates a scalable, low-voltage, and customizable electroadhesive component that can serve as a fundamental building block for future haptic interfaces in both wearable and immersive systems.

 

Bio:
Naoko Araki received the M.S. and Ph.D. degrees in science from Nara-Women’s University in 2003 and 2006, respectively. She joined Daicel Corporation in 2006, where she conducted research and development of resins for optical waveguides and fibers having flexibility and thermal stability. In 2014 she also joined WOW alliance in Institute of Science Tokyo where she engaged in the development of adhesives. Her research interests include cationic polymerizable resins having high heat-resistance.

Abstract:
We have developed a novel permanent adhesive suitable for both wafer-on-wafer (WOW) and chip-on-wafer (COW) processes, enabling room-temperature bonding without the need for adhesion promoters. This adhesive also shows promise for hybrid bonding applications. Its unique molecular structure provides excellent thermal stability, low outgassing, and minimal weight loss at elevated temperatures, making it ideal for 3D integration using ultra-thin wafers and bumpless through-silicon via (TSV) interconnects.
In previous WOW applications, permanent adhesive demonstrated low contact resistance and high uniformity in TSV interconnects with lengths as short as 12 μm on 300 mm wafers [1–6]. However, COW processes face challenges in using adhesion promoters due to the small surface areas of individual chips [7]. To overcome this limitation, a new adhesive has been developed that does not require adhesion promoters while retaining the thermal and mechanical advantages demonstrated in WOW applications. This adhesive can be coated on only one side, significantly simplifying the bonding process and broadening its applicability to a wider range of integration processes.
The new adhesive can be applied via spin-on, spray, or roll-to-roll techniques, forming uniform layers under 10 μm thick. It cures at 135–170°C and thermally stable up to 300°C. After curing, it exhibits strong adhesion to both Si and SiO₂ surfaces and maintains excellent stability during thermal cycling [8]. Chips and wafers bonded at room temperature showed high mechanical strength and stability and reliability after curing, confirming its suitability for high-throughput and multilevel stacking. We also evaluated its performance in hybrid bonding using Cu-patterned wafers [9]. The adhesive was spin-coated, cured, polished, and diced, followed by hot compression bonding. The resulting copper–polymer hybrid interface was robust and electrically stable, indicating high compatibility with hybrid bonding processes. Notably, the resin’s tolerance to surface contamination offers a key advantage over conventional SiO₂-based bonding, which is sensitive to sub-nanometer particles. The softer properties of the resin may allow bonding even in the presence of sub-micron contaminants, potentially improving yield and process robustness. In addition to its mechanical and thermal properties, the adhesive’s compatibility with both WOW and COW processes—without requiring surface modification—makes it a versatile solution for next-generation 3D integration. Its ability to form reliable interconnects at room temperature contributes to reduced thermal stress and improved process efficiency.
In summary, the newly developed adhesive supports permanent bonding in both WOW and COW processes, and has been specifically demonstrated for hybrid bonding as an alternative to dielectrics. The capability of room-temperature bonding and elastic material characteristics provide the benefits of a low thermal budget in the bonding process, such as reducing warpage and increasing the margin of Cu-Cu connectability. This adhesive makes it a promising solution for advanced semiconductor packaging and 3D integration technologies.

 

Bio:
Shin Jungbin is currently a Master's student in the Department of Intelligent Fab. Tech Convergence at Sungkyunkwan University, with a research interest in high thermal conductivity ceramic material synthesis and composite fabrication. Their recent work involves the development of ceramic-based thermal interface materials, particularly in the area of thermal filler engineering and simulation-based analysis for advanced heat dissipation applications.

Abstract:
Flexible thermoelectric generators (FTEGs) are gaining increasing attention as self-powered energy harvesting solutions, particularly for next-generation wearable electronics, biomedical monitoring systems, and untethered Internet-of-Things (IoT) devices. The core performance of an FTEG depends heavily on its ability to maintain a substantial temperature gradient (ΔT) across the thermoelectric (TE) legs. However, commonly used flexible substrates such as polydimethylsiloxane (PDMS), polyimide (PI), or silicone elastomers exhibit intrinsically low thermal conductivity, which leads to poor lateral heat spreading and localized heat accumulation. This thermal bottleneck critically limits the achievable ΔT and, consequently, reduces the device’s power output.
To overcome this limitation, this study proposes a new class of anisotropic high-thermal-conductivity insulation films based on aligned aluminum nitride (AlN) nanofibers. AlN was selected due to its unique combination of high intrinsic thermal conductivity, electrical insulation, and chemical stability. Electrospinning was employed to fabricate precursor Al-containing nanofibers with high aspect ratios. These fibers were subsequently converted into pure wurtzite-phase ceramic AlN fibers through a high-temperature carbothermal nitridation process under an ammonia atmosphere.
The AlN nanofibers were then directionally aligned and laminated in multiple layers with orthogonal stacking configurations (0° and 90°). The layered composite structure was thermally pressed to promote intimate interfacial contact and directional heat pathways. This configuration enabled the film to exhibit high in-plane thermal conductivity while maintaining electrical insulation—an essential requirement for TE device integration.
To enhance both solar radiation absorption and mechanical flexibility, the top layer of the film was impregnated with a polymer binder mixed with small amounts of carbon black. Silver nanowire (AgNW) networks were employed as flexible electrodes by spin-coating onto the film surface. The fabricated composite film demonstrated excellent mechanical durability, withstanding more than 10,000 cycles in bending fatigue tests without significant performance degradation.
When integrated as a heat-spreading and insulating layer in a Bi₂Te₃-based p/n-type FTEG module, the film showed a significant improvement in the system’s overall performance. Continuous power output data collected over 72 hours under real-world ambient solar conditions revealed that the use of the anisotropic thermal film increased ΔT and boosted power generation compared to control samples with non-engineered substrates.
In addition, finite element method (FEM) simulations were conducted to analyze heat diffusion behavior and to predict the resulting thermoelectric voltage and output power. The simulation results closely matched the experimental data and confirmed that the system followed the theoretical power relationship P=(n⋅S⋅ΔT)2/4RLP = (n·S·ΔT)^2 / 4R_LP=(n⋅S⋅ΔT)2/4RL, where S is the Seebeck coefficient and R_L is the load resistance. The simulations also illustrated the role of fiber orientation, stacking geometry, and material anisotropy in establishing a uniform and efficient temperature gradient across the TE legs.
This work demonstrates a scalable and effective strategy to fabricate anisotropic thermal interface films that are electrically insulating, thermally conductive, and mechanically flexible. The developed AlN nanofiber-based composite is not only a powerful platform for improving FTEG performance but also provides a practical foundation for heat management in wearable electronics, self-powered sensors, and energy-harvesting devices operating with low-grade thermal sources.

 

Bio:
Jeff Chen, graduated from Mechanical Engineering Dep., NYUST in 2002 and started to work in USI as a manufacturing engineer from 2004. He has the experience on board and system assembly. Currently, he focuses on SiP new process and technology in COD. Yoyo Chen, received her bachelor’s degree in Chemical Engineering from Anhui Normal Universi-ty. She started working in 2007 as a manufacture engineer. She has more than 17 years’ experiences in SMT field. Currently, she is responsible for new product introduction and advanced technology development for SiP products.

Abstract:
As businesses continue to struggle with resource allocation and climate change, ASE group is seeking to improve its value contribution through innovations that will promote social and environmental benefits. ASE group’s low carbon strategy is an integral part of the company’s move towards Net Zero, the company continues to improve energy efficiency and adopt renewable energy alternatives across its operations.
The Formic Acid Vacuum Reflow Oven had been used in power module products for years, it uses solder preform to be the interconnection material and no need the clean process after reflow due to no “Flux” in the solder preform, but solder preform process is not easy to be used in SiP module, so if we can have Formic Acid Vacuum Reflow and keep the original solder printing process, then the deflux clean process of SiP module also can be removed as power module, not only saving clean equipment and cleaning addition agent spending but also electric power consumption and wastewater discharge.
The conventional reflow process needs cleaning process to remove flux, not only water-soluble solder paste but also non-clean one due to the post processes requirement, such as underfill or molding, so the deflux clean is always the must process in current SMT. Deflux clean machine consumes a lot of electric power to drive and discharge the considerable wastewater during the cleaning process after SMT reflow, it costs money to purchase flux cleaning equipment and consumes our precious water resources in TW. If there is an alternative process to produce the same products without flux cleaning, we will not need to buy clean machines to save money and electric power, then the saving water can be made good use in others, both economic and environmental benefits can be achieved in one time if this alternative process can work.
As Figure 1, the new/alternative process is expected to use “Formic Acid Vacuum Reflow Oven” with “Flux-free solder paste” instead of the conventional reflow oven, then the clean station can be pulled out from SMT process.

Figure 1. Conventional VS Formic Acid Reflow

The purpose of this paper is to evaluate the engineering workability of the Formic Acid vacuum reflow oven and flux-free solder paste for SiP (System in Package) module to apply the Formic Acid reflow without “Flux”, intend to provide the initial evaluation results for further study reference soon in ASE group.

 

Bio:
Li-Wei Yao has worked at the Industrial Technology Research Institute Electronic and Optoelectronic System Research Laboratories in Taiwan for more than 17 years. He specializes in in-mold electronics technology, 3D conformal sensor module integration, thin-film photolithography etching process, and integration technology for the foldable touch AMOLED panels.

Abstract:
This study presents the integrated design and simulation of a thermoformed center console, highlighting the application of advanced materials and manufacturing technologies to achieve a low-carbon, lightweight, and energy-efficient center console for the automotive industry. The thermoforming process was modeled using simulation software, and the metal screen-printed ink mesh pattern was incorporated to facilitate mesh generation and setting of boundary conditions. A comprehensive analysis of mesh deformation before and after thermoforming facilitates the prediction of surface decorative pattern displacement, ensuring that the pattern after thermoforming aligns with the intended design position. The offset compensation method demonstrates an accuracy of over 90%, underscoring the approach's efficacy. The experimental results indicate that the circuit displacement remains below 0.5%, substantiating the design's stability and reliability. Notably, at a distance of 41 millimeters from the knob, the strain value ranged between 0.46% and 0.5%.

 

Bio:
Nahye Kim received the B.S. degrees in the department of materials science and engineering from the Korea University, Seoul, South Korea, in 2025. She is currently researching in Korea Institute of Industrial Technology and her research interests include the advanced packaging technology.

Abstract:
The advent of the artificial intelligence era and the ongoing miniaturization of semiconductor devices have driven unprecedented demand for high-density, high performance computing technologies, particularly High Bandwidth Memory (HBM). This trend necessitates a significant increase in interconnection density to meet evolving computational requirements. To address these technological challenges, advanced packaging technologies have emerged as promising solutions. Especially, Cu hybrid bonding is one of the most potential methods for vertical stacking with high density due to copper's superior electrical conductivity, cost-effectiveness, and absence of intermetallic compound (IMC) formation. However, copper's inherent susceptibility to oxidation at elevated temperatures poses substantial challenges, leading to both electrical and mechanical degradation that compromises bonding integrity and overall device performance.
This study proposes a glucose vapor-assisted Cu direct bonding to suppress copper oxidation. Glucose was selected as a reducing agent as its hydroxyl and aldehyde groups readily donate H atoms or electrons, serving as a reducing agent for Cu. Furthermore, glucose is eco-friendly, non-toxic and stable at room temperature. Unlike other approaches that require additional plasma treatment or passivation layers for copper oxidation prevention, the proposed glucose vapor method eliminates these supplementary steps, thereby reducing both manufacturing costs and processing time.
The experiment was conducted with 1 micrometer-thick copper films plated on 1 cm × 1 cm and 0.5 cm × 0.5 cm silicon substrates. At first, heating process on hot plate was conducted with and without glucose vapor to confirm the feasibility of oxidation inhibition on Cu. Specimens heated with glucose vapor had much less copper oxide on the surface compared to the other.
This oxidation suppression operates throughout the thermal compression bonding (TCB) process. Comparative analysis was conducted between specimens exposed to glucose vapor and specimens bonded without glucose vapor to evaluate the oxidation prevention efficacy and bonding quality enhancement of glucose. An X-ray photoelectron spectroscopy (XPS) was performed to detect copper oxide’s peak on the surface. Additionally, sheet resistance measurement was performed to assess electrical property changes induced by copper oxide layer formation. The results of both measurements demonstrated oxidation suppression in glucose vapor-assisted samples, confirming the protective mechanism's effectiveness in preventing surface oxidation.
The glucose vapor-assisted approach facilitated Cu direct bonding processes at temperatures below 250℃, undercutting standard bonding temperature of 300-400℃. The bonding quality was evaluated through shear strength measurements and scanning electron microscopy (SEM) cross-sectional analysis to assess mechanical integrity. The specimens benefiting from glucose vapor assistance achieved higher bonding integrity compared to untreated specimens.
The glucose vapor-assisted approach prevented copper surface oxidation during TCB process, resulting in enhanced mechanical strength and improved electrical conductivity. These comprehensive findings demonstrate the substantial potential of glucose vapor protection as a viable, environmentally sustainable, and cost-effective approach for copper oxidation prevention in advanced semiconductor packaging applications, particularly for Cu hybrid bonding.

 

Bio:
Mr. Shaoyou Lu is an engineer at Tong Hsing Electronics, specializing in the development of AMB (Active Metal Brazing) substrates for high-power modules. His expertise includes conductor design, ceramic integration, and electrical reliability. In this presentation, he will share insights on substrate design for high-power applications.

Abstract:
With the global emphasis on electrification, energy efficiency, and carbon neutrality, the demand for high-performance power electronics has grown rapidly in key industries such as electric vehicles (EVs), renewable energy systems, industrial automation, and railway traction. These applications require power modules capable of operating reliably under harsh conditions — high voltage, high current density, elevated temperatures, and frequent switching. To meet these stringent requirements, wide band gap (WBG) semiconductors, such as silicon carbide (SiC) and gallium nitride (GaN), have emerged as superior alternatives to conventional silicon due to their exceptional thermal stability, higher breakdown voltage, and switching efficiency.
As the power density of WBG-based systems continues to increase, the substrate materials used for packaging play an increasingly critical role. Substrates must not only provide mechanical support and electrical insulation but also serve as efficient thermal pathways to manage heat dissipation. Among the available substrate options, silicon nitride (Si₃N₄) ceramics have attracted significant attention due to their unique combination of high thermal conductivity, low dielectric constant, excellent mechanical strength, and superior thermal shock resistance.
To address these requirements, Active Metal Brazing (AMB) technology has been widely adopted in the production of ceramic/metal composite substrates. In AMB substrates, copper (Cu) is bonded directly to the ceramic through a brazing layer containing active elements such as titanium (Ti), forming a reliable structure with integrated electrical and thermal conductivity. Tong Hsing Electronics, a leading manufacturer of advanced ceramic substrates in Taiwan, has been actively developing Si₃N₄-based AMB substrates to support the next generation of high-reliability power modules, particularly those utilizing WBG semiconductors. Module makers are looking for higher power density, however, higher power density always comes with the challenge in circuit design. To push the limit of the substrate, a series of electrical studies were performed in this paper.
In practical module design, trench structures are often incorporated on AMB substrates for electrical routing. However, the trench geometry (including opening width, depth, and spacing) has a significant influence on the local electric field distribution and overall dielectric performance. Improper trench design can lead to field crowding, partial discharge, and premature insulation breakdown, which severely impact system reliability.
This study presents a systematic investigation into the electrical reliability of Si₃N₄ AMB substrates with varying trench opening configurations. Multiple test samples with different trench geometries were fabricated using standard AMB processes and subjected to insulation resistance and dielectric withstand voltage testing under simulated operating conditions. The experimental analysis aims to clarify the correlation between geometric design and electrical insulation behavior, providing valuable insights for future optimization of substrates used in high-density, high-efficiency power module applications.

 

Bio:
I am the leader of the Research Group at RIMTEC Corporation, a member of the Zeon Group. My research focuses on hydrocarbon-based thermosetting resins for electrical insulation, aiming to improve their performance and reliability in industrial and electronic applications. I received my Bachelor of Engineering degree from Kobe University in 2002, and since then, I have been dedicated to exploring innovative solutions in resin technology.

Abstract:
Dicyclopentadiene (DCP) resin can control elasticity and is a thermosetting resin with low viscosity, low moisture absorption, and excellent electrical properties. In power cycle tests using power modules equipped with SiC-MOSFETs, outstanding results have been reported compared to silicone gel sealing materials. In recent years, power modules are expected to be used in various harsh environments, with durability in high-temperature and high-humidity conditions being a significant challenge. This report focuses on the low moisture absorption of dicyclopentadiene resin and presents the results of power cycle tests conducted after exposure to high-temperature and high-humidity environments, comparing it with other sealing resins.
As encapsulation resins, a developed DCPD resin, silicone gel, and epoxy were used. Power modules sealed with these resins were exposed to an environment of 85 °C and 85% relative humidity. After a specified exposure period, power cycling tests were conducted.
The developed DCP resin exhibited approximately twice the power cycle lifetime after exposure, whereas the silicone gel and epoxy encapsulated samples showed significantly reduced lifetimes compared to their pre-exposure performance. This difference is considered to be due to moisture absorption by the silicone gel and epoxy resins, while the DCPD resin remained unaffected by moisture.