Sessions Index

Bio:
Educational background： National Kaohsiung University of Science and Technology. The Master's Degree in Mechanical and Automation Engineering National Kaohsiung University of Science and Technology. The Doctoral Program in Engineering Technology at the College of Engineering(Not graduated) Experience: Advanced Semiconductor Engineering, Inc. Process Engineer of the Engineering Department Advanced Semiconductor Engineering, Inc. CRD Group Equipment Development Divison Project Engineer

Abstract:
The IC packaging is widely applied in semiconductor electronic CoWoS and automotive electronic products. Microwave plasma must be used to treat the surfaces of chips and substrates in advanced packaging. FCBGA products require plasma cleaning either before W/B or before molding. The main goal is to improve the adhesion between the substrate and the Die, and to have a uniform cleaning capability while ensuring good bonding reliability between the substrate and wire bond.

To enhance the reliability of CoWoS products following plasma treatment, it can improve the W/B adhesion. The copper wire can be soldered to the surface of the substrate and Die, and improve hydrophilic properties. In the semiconductor packaging with RF and MW Plasma, RF Plasma is a direct contact method that generates the heat in products and easily causes burning issues. However, MW Plasma is a non-contact method which is more suitable for processing substrates that W/B products already had applied.

The main purpose is to improve the existing issue of the Plasma which is not adhering to the substrate. We had used the Taguchi design of experiments method (L18). The material is FCBGA 95x240 mm substrate. We use water droplet angle data to confirm the cleaning effect!
Change the product from a 5-layers stacked position to a 10-layers mode, and confirm it through relevant experiments, including the spacing between the 5-layers shelves. Preliminary tests show that the reduced spacing can still achieve a cleaning effect. It can pass Cpk process capability and quality control inspection. The target characteristic of the Taguchi method is to achieve a contact angle of 20±5 degrees for water droplets, and to arrange the relevant factors to investigate the effect of Plasma on the surfaces of products at 5 layers and 10 layers.

This research has found that the low vacuum can result in better cleaning effects and welding capabilities. For the different parameters combined with vacuum, the cleaning capability of 10-layer boards is the same as that of 5-layer boards. It can meet the target value of 20±5 degrees and achieve a capability of Cpk>1.67. By using the Taguchi method orthogonal table L18 (21x37) to configure parameter combinations, it bases on the orthogonal table design and perform the drop angle measurement on the production line. To confirm its cleaning capability range <37 degrees, the optimal parameters for the 10-layer boards rack design by the experimental design can significantly improve UPH and Cpk to above 1.67!

Key words: Microwave High Frequency Plasma, Plasma Cleaning, Taguchi Design Experimental Method, Nominal-The-Best, NTB

 

Bio:
“Kuo-Hua Heish is a senior quality technical professional and working for electronic and telecommunication companies for more than 20 years. He is widely regarded as the go-to source on process integration, development, failure analysis and customer engagement for any technical and quality improvements. Additionally, Kuo-Hua is very keen on new material survey and application tests, especially in Heterogeneous Integration for product reliability improvements. With his quality and process improvement experiences, now is leading a process development team in WNC for advanced manufacturing process development and settlement. He is also willing to share, being a tutor for the industry-academia collaboration, invited to speak to organizations and universities in Taiwan.

Abstract:
The traditional underfill process typically requires defluxing/cleaning process to remove flux residues, ensuring the reliability of subsequent packaging. However, with the increasing awareness of environmental protection and the growing demand for process simplification, no-clean underfill technology has become an important focus in the industry. This technology eliminates the needs for chemical and water cleaning associate to energy consumption, which not only enhances production efficiency and reduces manufacturing costs but also significantly lessens environmental impact. The core of no-clean underfill technology lies in low residue fluxing process optimization, allowing for minimal or negligible flux residue during the reflow process, thereby eliminating the need for post-reflow cleaning while maintaining the mechanical strength and reliability required by conventional underfill processes.
In this study, two types of ultra-low residue flux materials were evaluated combining with normal underfill adhesives and flux compatible claimed underfill. The ultra-low residue flux was applied to the packaged components through a dipping process, followed by bottom fill technology for adhesive filling without any flux cleaning. Subsequently, multi-reflows and thermal cycling tests were conducted to assess such non-clean underfill process and material reliability. The results indicate that combining ultra-low residue fluxes with traditional underfill adhesives, or pairing them with flux compatible underfill adhesive, all successfully achieve a no-clean underfill process and pass 3X multi-reflow and 3000 cycles of thermal cycling testing.

 

Bio:
Danny Chang is a semiconductor process graduate student at National Yang Ming Chiao Tung University and an equipment engineer at GlobalWafers. With a background in materials science and dual master's degrees in semiconductor processing and business management, he has hands-on experience in wafer polishing systems, defense manufacturing projects, and product development. Danny combines engineering expertise with strong project execution skills, making him a versatile contributor in high-tech industries.

Abstract:
This study investigates the influence of pre-heating treatment on the electromigration (EM) reliability of flip-chip micro bump, with the objective of improving the lifetime of interconnects in advanced semiconductor packaging. Electromigration is a critical reliability concern in microelectronic micro bump, as the migration of metal atoms under high current densities can lead to void formation, resistance increase, and eventual interconnect failure. This research explores whether thermal pre-treatment, which promotes intermetallic compound (IMC) formation, can enhance the resistance to electromigration-induced degradation.
The experimental methodology involved preparing several flip-chip micro bump test samples under different thermal and electrical stress conditions. The pre-heating treatment was carried out at 210°C for either 5 or 15 minutes, and the electromigration stress was applied at 0.75 A and 150°C. Scanning Electron Microscopy (SEM) and Energy Dispersive X-ray Spectroscopy (EDS) were used to analyze the microstructural and compositional changes in the micro bump post-testing.
Five key sample groups were analyzed:
1. Sample (1): No pre-heating or EM applied. This served as the baseline for material composition.
2. Sample (2): Pre-heated at 210°C for 15 minutes without EM. This group allowed for the observation of IMC growth (primarily Cu₆Sn₅) due to thermal treatment alone.
3. Sample (3): No pre-heating, subjected to EM at 0.75 A and 150°C. This sample failed after approximately 480 hours, showing a 16.2% increase in resistance.
4. Sample (4): Pre-heated at 210°C for 5 minutes and then exposed to EM under identical conditions. This sample exhibited extended EM life (approximately 720 hours) and a lower resistance increase of 11.3%.
5. Sample (5): Pre-heated at 210°C for 15 minutes followed by EM. This sample failed more rapidly (240 hours) with a resistance change of only 2.8%, suggesting that excessive IMC formation may introduce brittleness or stress concentrations that negate the benefits of pre-treatment.
The results demonstrate that moderate pre-heating (5 minutes at 210°C) can effectively enhance the EM performance of micro bump by forming a stable IMC layer that inhibits atom migration. However, overexposure to thermal treatment (15 minutes) may result in excessive IMC formation, which can degrade mechanical integrity and reduce EM lifetime. Therefore, optimizing pre-heating parameters is crucial for achieving reliable interconnects in flip-chip packaging.
This study contributes valuable insights into the materials engineering of micro bump in advanced packaging applications and supports the hypothesis that controlled thermal treatment prior to EM exposure can be a viable method to enhance reliability. Further research should explore the mechanical stress profiles and microstructural evolution in more detail to refine the pre-conditioning strategies for mass production environments

 

Bio:
T. Y. Ouyang received a Ph.D. degree in physics from National Taiwan University, Taiwan, in 2015. He was a postdoctoral fellow with the Center for Condensed Matter Sciences (CCMS), Taiwan, from 2016 to 2018. He is currently a senior engineer at the Industrial Technology Research Institute (ITRI).

Abstract:
A scalable via array substrate is manufactured and enables the provision of small-volume, large-variety production packaging producibility evaluation. This scalable via array substrate is comprised of pre-fabricated redistribution layers and customized redistribution layers. The pre-fabricated redistribution layers have consisted of four-metal levels of copper RDLs, and 180 µm height through mold vias. Dual active switch dies were embedded in the through mold vias, which act as a bridge to program and modulate the signal transmission between integrated heterogeneous chips (Bluetooth, flash memory, and microcontroller unit). With the integration of various functionality chips, we can define the routing interconnection traces using simplified 2P1M customized redistribution layers, reducing the complexity of layout design. A scalable via array substrate provides a cost-effective packaging architecture and is expected to be a promising solution for high-performance system-in-package. The pre-fabricated redistribution layers guarantee a stable manufacturing yield, shortening 50% the time-to-market and reducing the production cost.

 

Bio:
1. Name : Nam Son Park 2. Title : Professor 3. Affiliation : Tech University of korea Prof. Nam son Park is a Research Professor at Tech University of Korea (TUK) in the Semiconductor Package–PCB Center. With over 30 years of industry experience, he specializes in semiconductor packaging and advanced substrate processing. Prof. Park holds a master’s degree in Precision Mechanical Engineering from Hanyang University and is pursuing a Ph.D. in Advanced Materials Engineering at TUK. He has contributed extensively to international conferences like ISMP, ICSE, and AIS/I3S, covering topics such as plasma processing, microvia etching, and flip-chip packaging. His research focuses on next-gen packaging substrates, including glass and 2.1D substrates, and ultra-fine line/space patterning.

Abstract:
INTRODUCTION
Conventional CO₂ laser drilling combined with wet desmear processes has limitations in forming fine-pitch microvias, particularly in advanced microcircuit applications. Although ultraviolet (UV) laser drilling can produce smaller via diameters, its use is limited for build-up films (BUF) protected by polyethylene terephthalate (PET). Direct plasma exposure of the BUF can cause filler protrusion and increase surface roughness. This, in turn, necessitates thicker seed layers in the semi-additive process (SAP) and ultimately hinders the realization of fine circuit patterns.

EXPERIMENTAL METHODS
To address these limitations, we sputter-deposited 50–200 nm-thick copper (Cu) and nickel–chromium (Ni–Cr) thin films onto the BUF surface prior to nanosecond UV laser drilling. These metallization layers served as protective coatings for the BUF during the subsequent plasma desmear process. After laser drilling, a plasma desmear was performed to remove residual smear and assess the surface integrity. A 3D laser microscope was used to analyze debris and via morphology, particularly around the via openings in a 200 nm-thick sacrificial metal barrier layer (SMBL). In addition, focused ion beam scanning electron microscopy (FIB-SEM) was used to examine the quality of the microvias fabricated in the BUF under various UV laser drilling parameters.

RESULTS AND DISCUSSION
Microvias with diameters below 10 μm were successfully formed without increasing the surface roughness of the BUF, demonstrating the effectiveness of the SMBL coating. The results indicate that a metal layer thickness of at least 100 nm is sufficient to protect the BUF during both UV laser drilling and the subsequent plasma desmear. Optimized plasma desmear conditions were established to effectively eliminate residual smear while minimizing via enlargement. Surface profilometry and FIB-SEM analyses confirmed the structural integrity and precise dimensional control of the microvias, validating the feasibility of this approach for high-density interconnect applications.

CONCLUSION
This study proposes a practical method for microvia fabrication in SAP-based advanced packaging. Integrating sputtered thin Cu and Ni–Cr sacrificial metal barrier layers with UV laser drilling and plasma desmear processes enables the fabrication of sub-10 μm microvias with low surface roughness and high reliability. The proposed method effectively overcomes the limitations of conventional CO₂ laser drilling and wet desmear processes, offering a promising solution for next-generation fine-pitch interconnection technologies.

 

Bio:
Student at the Microsystem Packaging Laboratory, Sungkyunkwan University

Abstract:
Carbon nano Tubes are known for their exceptional thermal conductivity. Given this outstanding property, there have been many tries to apply CNTs in other materials where thermal management and mechanical strength are paramount.
However, directly mixing CNTs into solder materials presents a significant challenge due to the density mismatch between CNTs and the solder.
To overcome this issue, we employed a method that involves coating CNTs with Cu. Through the three steps of Cu decorating, we can mitigate the density difference and successfully mix the Sn-decorated MWCNTs into the solder. This approach enhances the thermal properties of the composite solder.
Reflow process is a high-temperature process that utilizes thermal energy and causes warpage and thermal damage problems. In order to overcome this problem, such as laser assisted bonding, several alternative temperature processes have been studied. One of these alternative soldering process, is Intense Pulsed Light soldering, which enables large area soldering with short process time of several microseconds. Since lead-free solder was found to be harmful to the environment and human body, many lead-free solders have been studied. Among those lead-free solders, the Sn-3.0Ag-0.5Cu solder alloy composition has been commonly used, because of its excellent mechanical properties and reliability. In this study, because of the properties of MWCNT that can prevent the propagation of cracks in the solder, Sn-MWCNT and SAC 305 composite materials were synthesized to enhance drop and thermal reliability. Experiment condition of IPL soldering was different pulse widths (2.75, 3.0, 3.25 ms) and pulse number. The shear strength was analyzed through a ball shear test, and the drop impact test was performed by JESD22-B110 standard. The coated Sn-MWCNTs were measured via TEM. The microstructure and fracture surface of the solder were observed using a scanning electron microscope. Long-term reliability of solder joints was evaluated through a high storage temperature test, and it was confirmed that the shear strength decreased over time due to the influence of IMCs growth and coarsening, and the decrease of shear strength value was measured to be the lowest at 0.1% Sn-MWCNT content. In addition, The evaluation of resistance before and after the drop impact test was compared, and the difference in density according to the Sn-MWCNT content was measured. In the case of thermal conductivity, the junction temperature was compared through an IR camera, and it was confirmed that the highest thermal conductivity was achieved in the case of 0.1% Sn-MWCNT particle content.
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Bio:
Jie-Ming Li is a master’s student in the Department of Mechanical and Electro-mechanical Engineering at National Sun Yat-sen University. Since 2024, he has been a member of the MOEMS Laboratory under the supervision of Associate Professor Mei-Ling Wu. His research focuses on thermal deformation behavior and finite element modeling in semiconductor packaging. Specifically, he investigates warpage and stress distribution in QFN lead frames under thermal loading, using three-dimensional thermo-mechanical coupling simulations in ANSYS to analyze the effects of sawing lane geometry and provide design optimization strategies.

Abstract:
With growing demands for packaging reliability, QFN packages often encounter warpage issues during thermal processes. This study investigates the deformation behavior of a 17.1 mm × 16.4 mm QFN lead frame under heating, focusing on the impact of varying sawing-line widths. A three-dimensional thermo-mechanical model, incorporating material and thermal parameters, was implemented within the ANSYS platform to replicate the heating-induced deformation of the QFN lead frame. The simulation applied a temperature ramp from 25°C to 200°C under a 1 Block strip configuration with different sawing widths (0.3 / 0.7 / 0.9 mm). Results show that increased sawing-line width reduces peak deformation near the region due to enhanced local stress relief, while deformation trends remain symmetrical. These findings highlight the role of geometric design in managing thermal warpage and suggest that optimizing sawing-line width is an effective cutting approach to improve structural stability in QFN packaging.

 

Bio:
Shih-Yun Tu is a Bachelor of Science (B.S.) candidate in the Department of Mechanical and Electro-Mechanical Engineering at National Sun Yat-sen University. She is an IEEE Student Member in 2025. Since joining the MOEMS Laboratory in 2024, she has been engaged in research related to microelectronic packaging, simulation mechanics, and dynamic material response. Her current research focuses on analyzing micromechanical vibrations and wafer-edge stress behavior during post-CMP cleaning. Through a combined experimental and simulation-based approach, she investigates the influence of vibration and structural support on wafer surface stress distribution and cleaning quality. Using finite element analysis and vibration measurement, she developed optimized wafer support structures to minimize surface defects and enhance wafer cleaning yield and uniformity. In 2024, she participated in an industry-academia collaboration project with Taiwan Semiconductor Manufacturing Company (TSMC), under the guidance of Professor Mei-Ling Wu.

Abstract:
Based on the Chemical Mechanical Polishing (CMP) process, dynamic properties of wafer cleaning stage are studied, then simulations and analysis are made to improve cleaning capacity of the stage. The improvement of the stress distribution in the wafer could be an important factor, and an increase in the stability of the machine may be contributed to the analysis of vibration characteristics and the optimization of the support parameters. The reinforced wafer support structure was developed to obtain higher structure rigidity and to minimize stress non-uniformity and surface defects due to vibration. It stabilizes the downforce of the cleaning grinding wheel, resulting in uniform clean of particulate contaminants on a wafer. And, consequently, it promotes for enhanced quality of wafer cleaning and yield and facilitates better adhesion between photoresist and pattern accuracy in photolithography processes while it prevents problems such as electromigration between the metal layers and dielectric breakdown. This work goes further to compare the mechanical disturbance behavior between pre-CMP and post-CMP cleaning and to study the vibration phenomenon of stick-slip between the polishing pad and wafer substrate. The influence of these oscillations on the wafer final surface quality is analyzed extensively.

 

Bio:
Chien-Hao Liu (S’12–M’15) received the BS and MS degrees in mechanical engineering from National Taiwan University, Taipei, Taiwan, in 2005 and 2007, respectively. Then, he received his MS and Ph.D. in electrical engineering from the University of Wisconsin–Madison (UW-Madison), Madison, WI, USA, in 2013 and 2014, respectively. He was a research assistant with the Electrical and Computer Engineering Department at UW-Madison from 2011 to 2014. From 2014 to 2015, he was a research associate with the Electrical and Computer Engineering Department at UW-Madison. He is currently an associate professor with the Mechanical Engineering Department at National Taiwan University. His research interests include RF/microwave circuits, antennas, frequency-selective surfaces, acoustic metamaterials.

Abstract:
In this research, we propose a graphene-based composite material for providing high EMC/EMI shielding and superior heat dissipation for IC protection applications. In contrast to most composite EMC shielding materials such as CNTs, graphite, and metal nanoparticles, the presented composite has relatively uniform distributions of graphene inclusions, resulting in high shielding effeteness (SE) in the standard required frequency band ranging from 100 MHz to 3 GHz for IC applications [1]-[2]. In addition, it demonstrates sufficient SE with 10 dB over the range from 8 GHz to 12 GHz for X-band absorptions and military applications. Some samples have been fabricated via the mixing and annealing process, and their effective permittivity and SE are experimentally extracted via waveguide measurements. The composite is integrated with several bare die with RF oscillating signals and its EMC shieling capability is characterized via the self-built EMC scanning probe stations. In addition, the thermal conductivity of the composite is experimentally examined with the well-known 3-omenga methods and the measured values are larger than most packaging materials by order of 10-fold to 100-fold. It is demonstrated that the proposed composite integrated with bare IC can provide efficient EMC/EMI shielding in the desired RF frequency bands and good heat dissipation without degrading the performance. The research results are expected to be beneficial for the IC packaging and the next generation of high-power hetero-integrated IC.

 

Bio:
Dr. Ching-Feng Yu is an Assistant Professor in the Department of Mechanical Engineering at National United University, specializing in advanced electronic packaging and 3D heterogeneous integration technologies. He received his Ph.D. in Power Mechanical Engineering from National Tsing Hua University in 2014, focusing on the mechanical behavior and electromigration resistance of intermetallic compounds. Prior to his academic position, Dr. Yu accumulated over six years of R&D and engineering experience at institutions such as the Industrial Technology Research Institute (ITRI), AU Optronics, and the National Chung-Shan Institute of Science and Technology. His professional work spans heterogeneous chip packaging, automotive display modules, and thermal structural design for defense applications. His research interests include low-warpage packaging, deep learning for advanced packaging inspection, microscale structure modeling, and quantum-based materials simulation. He has authored more than 20 SCI journal papers and 25 conference papers, and has received awards including the ITRI Outstanding Research Award and multiple Best Paper recognitions at the IMPACT International Conference. Dr. Yu is also actively involved in national research projects and academic review committees, demonstrating strong capabilities in cross-disciplinary collaboration and technology innovation.

Abstract:
In high-performance computing and artificial-intelligence applications, organic redistribution-layer (RDL) interposers are rapidly gaining traction because they offer fine pitch, low IR drop and better cost scalability than silicon bridges. Yet fabricating more than a few metal-polyimide layers with the conventional semi-additive process (SAP) is difficult. Each additional layer demands a >300 °C polyimide cure, and the accumulated coefficient-of-thermal-expansion mismatch can push panel-size glass carriers into millimetre-level warpage, degrading lithography alignment and yield [1].
Recent studies have introduced the Hyper-RDL (HRDL) architecture to address this bottleneck. HRDL forms one-metal two-polymer sub-modules on separate carriers, then joins them through low-temperature metal-polymer hybrid bonding. Bonding at 180 to 250 °C and 2 MPa preserves both Cu-Cu and PI-PI interfaces and delivers an average shear strength of about 48 kgf/cm-2 while keeping resistance drift below 1.5 % after 1000 thermal cycles [2]. By eliminating most hard-cure steps, a four-layer HRDL stack has been shown to shrink glass-substrate warpage from roughly 2.8 mm to 0.13 mm, a twenty-fold reduction compared with SAP [2]. Panel-level trials on 12-inch glass further cut deflection from more than 2500 µm to under 500 µm after four layers, confirming that low-temperature bonding can control distortion on large formats [1,3].
Although HRDL greatly mitigates process-induced warpage, published flows still complete die placement, epoxy-mold encapsulation and wafer thinning after the RDL stack is finished. These downstream steps re-heat the substrate or remove mechanical support, re-introducing stress and partially eroding the flatness benefits earned at the RDL stage. A manufacturing sequence that can maintain low stress through the entire module build-up is therefore essential.
The present work proposes an enhanced HRDL-inspired process that re-orders the key operations, as illustrated in Fig. 1. Fine-pitch RDL and through-mold vias are first patterned on separate carriers. Active dies are then mounted, over-molded and back-thinned to the target z-height while the structure remains fully supported. After applying a polyimide passivation to seal exposed copper, the upper and lower RDL modules are aligned and joined by Cu / PI hybrid bonding at sub-250 °C. The carrier is subsequently laser-debonded, and solder balls are attached to form the final ball-grid array. By locking in dimensional stability before bonding, the new flow limits final package deflection to below 100 µm on 300 mm glass while sustaining 2 µm line-space and 6 µm through capability. This sequence therefore offers a robust path to ultra-flat, high-layer-count RDL interposers that outperform both SAP and baseline HRDL in warpage control, mechanical strength and electrical reliability.

 

Bio:
Chao-Kai Hsu is a seasoned professional with extensive experience in the field of wafer-level packaging. He joined the Industrial Technology Research Institute (ITRI) in Taiwan in 2004 and has since been dedicated to driving technological innovation and achieving key breakthroughs. From 2004 to 2005, Hsu worked in the Microelectromechanical Systems (MEMS) department, where he contributed to the development and validation of splitter technology for optical coupling. This foundational experience strengthened his expertise in optical integration and set the stage for his future technical pursuits. From 2005 to 2021, he transitioned to the 3D Integrated Circuit (3DIC) department, focusing on wafer molding, wafer thinning, and the development of flexible light source technologies. His contributions were instrumental in advancing 3DIC packaging technologies and applications. In 2021, Hsu joined the Heterogeneous Chip Integration and Assembly department, where he specializes in 3D Fan-Out Wafer-Level Packaging (3D-FOWLP)—a cutting-edge technology that enables high-density heterogeneous integration. This has since become one of his primary areas of expertise. Hsu currently serves as a researcher at the Electronics and Optoelectronics System Research Laboratories (EOSRL) of ITRI. With his deep technical knowledge, hands-on experience, and unwavering commitment to innovation, he continues to drive progress in the semiconductor packaging industry and actively shares his insights to inspire future developments.

Abstract:
To meet the rising demand for high-performance, multifunctional electronic systems, this study proposes an innovative dual fan-out module 3D packaging architecture for large-size, low-warpage, high-density multi-chip heterogeneous integration. Traditional fan-out packages face severe warpage due to interactions between multilayer RDLs and molding compounds—especially in 3D stacked or large-format designs.
Our solution integrates carrier preparation, RDL and copper pillar processes, high-density chip packaging, wafer molding and thinning, polymer coating, passivation, and precision bonding of dual fan-out modules. Experiments conducted on silicon, ABF molded, and RDL TMV molded wafers demonstrated that warpage in 100 mm RDL TMV wafers was reduced from 0.52 mm to 0.04 mm after bonding. The module bond strength reached 118.6 kgf, exceeding the industry threshold of 9.3 kgf. A fine 20 µm chip-to-chip gap was achieved, with no delamination or voids observed after 10 reflow cycles. SEM, SAT, and X-ray analyses confirmed excellent structural integrity.
This dual fan-out 3D packaging platform offers high reliability, fine-pitch scalability, and excellent adaptability, making it a strong candidate for next-generation SiP applications in AIoT, HPC, and edge computing.

 

Bio:
My name is Lin Po Yuan. I completed my undergraduate studies at Southern Taiwan University of Science and Technology, and I am currently pursuing my graduate degree at National Sun Yat-sen University, majoring in Advanced Semiconductor Packaging and Testing. My hobbies include working out and watching movies.

Abstract:
Abstract
In modern power electronics and semiconductor packaging, silver paste has emerged as a critical material due to its exceptional electrical and thermal conductivity. This material is widely utilized to form reliable interconnects and die-attach layers, with stencil printing followed by sintering being a prevalent deposition technique. However, a frequent challenge in this process is the “dog-ear” effect, characterized by edge bulging or excessive accumulation of paste around printed features. This undesired morphology can lead to non-uniform bonding interfaces, degraded thermal contact, and compromised long-term reliability, particularly in fine-pitch or high-power applications where precision is paramount. Such defects are especially problematic in advanced microelectronics, where even minor irregularities can significantly impact device performance and durability under operational stresses.
This study aims to systematically investigate and optimize the silver paste stencil printing process to mitigate or eliminate the dog-ear effect through a combination of experimental measurements and advanced fluid dynamics simulation. A stainless-steel stencil with an aperture size of 5.9 mm × 4.9 mm and a thickness of 80 μm serves as the experimental platform. Key printing parameters, including squeegee angle (65°), printing speed (10–20 mm/s), separation speed (1–2 mm/s), and squeegee pressure (4–6 kg), are systematically varied to assess their impact on paste deposition quality and edge morphology. These parameters are critical in determining the flow behavior and final printed structure of the shear-thinning silver paste, which exhibits complex rheological properties that influence its behavior during printing.
To enhance understanding of the underlying mechanisms, ANSYS FLUENT is employed to simulate the internal flow of the silver paste, incorporating its rheological properties such as viscosity curves, yield stress, and shear-thinning behavior. This simulation approach enables a detailed modeling of the deposition behavior, providing insights into how paste flow dynamics contribute to the dog-ear effect under varying conditions. The simulated paste profiles are experimentally validated using a high-precision surface profile scanner (VR5200), allowing for a quantitative comparison between simulation predictions and real-world outcomes. This validation step ensures the reliability of the computational model and its applicability to practical scenarios, bridging the gap between theoretical analysis and industrial application.
By correlating experimental data with simulation results, this research identifies the key factors driving the dog-ear phenomenon, including the interplay between printing speed, separation dynamics, squeegee pressure, and the paste’s viscoelastic properties. Based on these findings, optimal printing conditions are proposed to achieve uniform edge profiles and enhance overall printing reliability. These insights offer practical guidance for industry practitioners, particularly in optimizing die-attach and packaging processes for high-performance power electronics. The study’s outcomes are expected to contribute to improved manufacturing yields, reduced defect rates, and the development of robust semiconductor devices, addressing the growing demands of advanced electronic applications in fields such as renewable energy, electric vehicles, and 5G technology.

 

Bio:
Hello everyone, my name is Yeh Bao-Lin. I graduated from the Department of Automation Engineering at National Formosa University and am currently a second-year master's student at the Institute of Advanced Semiconductor Packaging and Testing at National Sun Yat-sen University. I’m passionate about semiconductor packaging technologies, and in my free time, I enjoy playing baseball.

Abstract:
In high-power semiconductor module packaging, silver (Ag) sintering has emerged as a promising die-attach technology due to its excellent thermal and electrical conductivity, as well as its ability to withstand high operating temperatures. As packaging structures evolve toward higher integration and enhanced thermal management, incorporating a Die Top System (DTS) on the die has become an effective approach to improve both heat dissipation and mechanical robustness. This study aims to systematically investigate the reliability differences between single-step and double-step sintering processes when applied to DTS-integrated structures, focusing on the bonding quality and long-term performance to provide a process guideline for advanced packaging design.
Silver paste is applied using stencil printing, with stencil apertures measuring 4.9 × 5.9 mm and a thickness of 80 μm. After printing, the paste height and shape are measured using a VR-5200 surface profiler to verify uniform deposition and edge quality. Both single and double sintering processes are carried out under a bonding pressure of 20 MPa. The experimental parameters include three sintering temperatures (230°C, 260°C, and 280°C) and two sintering durations (2 minutes and 5 minutes). In the double-step sintering process, the die is first attached and sintered, followed by the placement of the DTS and a second sintering under the same conditions. This design allows for a comparative analysis of the microstructural and bonding performance changes before and after DTS integration, enabling a deeper understanding of how sintering sequence influences joint evolution.
To evaluate the structural integrity and reliability of the bonded layers, multiple experimental tests are planned. Scanning Acoustic Tomography (SAT) will be used to detect interfacial delamination, while the Dage 4000+ system will be used to perform die shear and peeling tests. The microstructure of the sintered layer will be examined using Scanning Electron Microscopy (SEM), and porosity will be quantified based on cross-sectional SEM images using ImageJ software. In addition, Thermal Cycling Tests (TCT) lasting 500 and 1000 hours will be conducted to simulate long-term thermal fatigue conditions. After TCT, all evaluations will be repeated to observe changes in reliability and material degradation.
The objective of this study is to investigate the effects of the DTS structure and different sintering sequences on the microstructure and mechanical stability of the die-attach layer, and to further identify the most suitable process parameters. In the future, we hope that the experimental results will provide concrete references for the packaging design of high-reliability power modules. In addition to improving the bonding strength and thermal performance of the die-attach layer, the findings from this study may also be applicable to other fields such as automotive electronics, renewable energy systems, and high-power electronic devices.

 

Bio:
my name is Tsung-Chieh Wu . I am currently a second-year master's student at the Institute of Advanced Semiconductor Packaging and Testing at National Sun Yat-sen University. My research focuses on the application of High Glass Transition Temperature Epoxy Resin in Power Module Packaging. I am currently interning at the R&D department of ASE Group.

Abstract:
In recent years, the demand for high-reliability and thermally robust power module packaging has surged, driven by the rapid development of electric vehicles, renewable energy systems, and high-power industrial electronics. Traditional epoxy molding compounds (EMCs) often suffer from warpage, delamination, and thermal degradation when subjected to elevated temperatures or harsh operating environments, primarily due to their limited glass transition temperature (Tg) and insufficient thermal conductivity. To address these challenges, this study investigates the use of high-Tg epoxy resins as molding materials in advanced power module packaging.

In the initial phase, five epoxy molding compounds with different glass transition temperatures were selected for comparative evaluation based on their datasheet properties, including thermal stability and low coefficient of thermal expansion (CTE). These materials were molded onto standardized power module test vehicles utilizing a single-side cooling configuration. Experimental procedures include thermal cycling (−40 °C to 150 °C) and high-temperature storage (e.g., 200 °C for 1000 hours), with all test conditions intentionally designed to exceed the requirements defined in the AQG 324 automotive reliability standard. Post-test characterizations, including cross-section analysis (CSA), scanning acoustic tomography (SAT), and scanning electron microscopy (SEM), were employed to evaluate internal voids, delamination, and crack propagation.

Additionally, a series of thermal and mechanical analyses were performed to assess each material’s intrinsic properties. Thermomechanical analysis (TMA) and differential scanning calorimetry (DSC) were conducted to confirm their thermal expansion characteristics and accurately determine Tg. Dynamic mechanical analysis (DMA) was used to evaluate the viscoelastic behavior of the EMCs under temperature-dependent mechanical stress, providing additional insight into modulus performance near and beyond Tg. Thermogravimetric analysis (TGA) was performed to assess decomposition behavior under continuous heating, and a rheometer was employed to study the flow behavior and viscosity of the uncured epoxies during molding, ensuring suitability for void-free encapsulation. The combination of these analyses allows for a comprehensive understanding of material behavior across both thermal and mechanical reliability domains.

Experimental results demonstrated that high-Tg epoxy resins consistently exhibited superior stability and reliability under thermal stress conditions. They showed enhanced interfacial adhesion and reduced CTE mismatch, which effectively minimized internal defects such as delamination and microcracking. Thermal aging tests confirmed their structural integrity after prolonged high-temperature exposure. The materials also maintained encapsulation performance through extended thermal cycling, validating their applicability in harsh environments such as automotive under-hood systems and industrial power inverters. These findings provide practical guidance for the selection and qualification of robust EMC materials in next-generation power module packaging, especially for applications requiring extended service life under extreme thermal conditions.

 

Bio:
Hello, my name is Tsung-Han Li, a second-year master’s student at the Institute of Advanced Semiconductor Packaging and Testing, National Sun Yat-sen University. Currently, I am also working as an R&D intern at ASE Group (Advanced Semiconductor Engineering), where I’m part of a department focused on the development of power module packaging technologies, especially for electric vehicle (EV) applications. Our team explores various innovative packaging approaches, such as copper and silver sintering, as well as next-generation EMC (Epoxy Molding Compound) materials. My personal research focuses on the design, analysis, and application of Insulated Metal Substrate (IMS) in power modules, aiming to bridge the gap between academic insight and real-world implementation. By combining my university research and hands-on industrial experience, I strive to contribute practical and forward-looking solutions to the field of power electronics packaging.

Abstract:
The rapid proliferation of electric vehicles (EVs) necessitates advancements in power module technology, particularly in thermal management, reliability, and cost-effectiveness. Traditional ceramic substrates, including Direct Bonded Copper (DBC) and Active Metal Brazed (AMB), are widely utilized due to their excellent thermal conductivity and insulating properties. However, they present significant challenges primarily arising from mismatches in coefficients of thermal expansion (CTE) between ceramic and copper layers, causing stress-induced reliability issues such as delamination and chipping. Consequently, substrate design flexibility is limited to symmetrical copper layers, restricting further improvements.

Insulated Metal Substrates (IMS) offer a promising alternative, exhibiting superior CTE compatibility with copper layers, significantly reducing thermal and mechanical stress. This inherent advantage enables IMS substrates to employ more flexible structural designs, including asymmetric copper layer configurations, without compromising reliability. Furthermore, IMS substrates can be manufactured thinner by reducing dielectric layer thickness, significantly decreasing thermal resistance and enhancing heat dissipation performance.

Leveraging these advantages, this research evaluates three distinct IMS substrate designs: symmetrical copper layers, thicker upper copper with thinner lower copper layers, and thicker lower copper with thinner upper copper layers. Each IMS configuration maintains an identical total thickness as traditional DBC (ZTA) and AMB substrates. By strategically reducing the dielectric layer thickness, IMS substrates allow proportional thickening of copper layers, optimizing thermal performance.
Finite Element Analysis (FEA) simulations were conducted using ANSYS to assess thermal distribution and mechanical warpage behavior across various substrate configurations. Experimental validation included thermal resistance measurements using T3STER, warpage analyses via PS400 Shadow Moiré, and dielectric breakdown voltage tests to evaluate insulation strength across different dielectric materials. Integrating simulation with experimental results ensures a comprehensive and accurate evaluation of IMS substrates under realistic operational conditions.

The primary goal of this study is to identify the optimal IMS structural configuration, balancing superior thermal performance, enhanced mechanical reliability, and excellent insulation capability. The results will provide valuable guidance for effective power module substrate designs, validating the practical viability of IMS as a suitable replacement for conventional ceramic substrates in EV and advanced electronic applications. Ultimately, this research significantly contributes to developing highly efficient, reliable, and cost-effective power module solutions, thereby accelerating the adoption of advanced power electronics technologies.

Key Words: Power Module Substrate, Insulated Metal Substrate (IMS), Finite Element Analysis (FEA), Thermal Management, Warpage, Insulation Strength

 

Bio:
Ching-Kuan Lee is currently a Researcher with Industrial Technology Research Institute, Hsinchu, Taiwan.

Abstract:
Gallium nitride high electron mobility transistors are characterized by fast switching speeds and small chip sizes, making it challenging to achieve low parasitic inductance and high heat dissipation in packages for power electronics applications. In this paper, a packaging technique is developed for the fabrication of horizontal 650V, 30A GaN power transistors in discrete packages. The electrical contacts are silver sintered materials fabricated on direct plated ceramic (DPC) substrates using flip chip bonding technology and attached to a copper frame for heat dissipation and electrical connection. We performed process stress simulations and compared them with actual experimental samples. We fabricated discrete packages, characterized their static performance, and verified 1000-cycle temperature cycling tests (TCT). The data show the feasibility of this discrete package for power electronics applications.

 

Bio:
My name is Ming-Pei Lu, and I am currently a second-year master's student at the Institute of Advanced Semiconductor Packaging and Testing at National Sun Yat-sen University in Taiwan. My research focuses on the warpage behavior of high glass transition temperature (High Tg) epoxy molding compounds used in semiconductor packaging. I am particularly interested in understanding how material properties and process parameters influence thermal-mechanical deformation during packaging processes, with the goal of improving reliability and manufacturability in advanced electronic modules.

Abstract:
With the widespread deployment of wide bandgap (WBG) semiconductor technologies such as silicon carbide (SiC) in automotive and high-temperature power electronics, packaging structures are increasingly challenged by severe thermal-mechanical stress. Warpage deformation has become a critical issue that significantly affects the reliability and lifetime of power modules. To improve thermal stability and effectively mitigate warpage, this study investigates several high glass transition temperature (Tg) epoxy molding compounds (EMCs) as encapsulation materials, benchmarked against standard commercial EMCs. A representative single-side cooled power module structure is modeled for simulation and validation.

The study begins with experimental characterization of thermal-mechanical properties of EMCs, including measurements of coefficient of thermal expansion (CTE), modulus behavior, and glass transition temperature using TMA (Thermo-Mechanical Analysis), DMA (Dynamic Mechanical Analysis), DSC (Differential Scanning Calorimetry), and rheometry. These measured parameters are then integrated into a finite element model (FEM) that simulates the warpage behavior during the transfer molding process. The model also includes the sintered Ag die-attach layer, DBC substrate, and heatsink interface to reflect real package complexity.

Simulation results indicate that differences in elastic modulus and CTE among EMCs can result in significant warpage variations, reaching up to several hundred microns. Warpage deformation is found to be concentrated in the chip central region and strongly correlated with stress accumulation near material interfaces. Furthermore, the study explores how adjusting package thickness ratio, material stiffness, and cooling profiles can serve as effective strategies to reduce deformation.

To validate simulation accuracy, shadow moiré fringe analysis is employed to measure the warpage profile of post-molded samples. Additionally, scanning acoustic tomography (SAT) is used to identify delamination or void defects at key interfaces. The experimental observations show strong agreement with simulation results, confirming the effectiveness of the proposed modeling workflow and materials characterization approach.

This study demonstrates that proper material selection, along with fine-tuned process control, can significantly mitigate warpage in high-temperature power modules using high Tg EMCs. The research outcomes offer practical guidelines for packaging engineers in optimizing encapsulation strategies to enhance the reliability and mechanical stability of next-generation power electronic systems under high thermal stress conditions.

 

Bio:
My name is Kuan Chih Chen. I am currently a second-year master's student at the Institute of Advanced Semiconductor Packaging and Testing at National Sun Yat-sen University. My research focuses on the application of copper sintering in high-power modules. I am currently interning at the R&D department of ASE Group.

Abstract:
With the increasing demand for high-reliability and high-efficiency power modules in electric vehicles and industrial applications, the selection of die-attach materials has become a critical factor affecting both thermal management and long-term reliability of the module. Sintered silver has long been widely adopted as the standard bonding material in high-end packaging due to its excellent thermal and electrical conductivity, along with superior thermal stability and mechanical strength. However, its high material cost and demanding processing requirements—such as elevated temperature and pressure—limit its adoption in cost-sensitive applications.
As a promising alternative, sintered copper has garnered significant attention in recent years owing to its excellent thermal conductivity, robust mechanical properties, and significantly lower material cost compared to silver. Nevertheless, one of the major challenges hindering its widespread adoption in practical module applications is its susceptibility to oxidation during the high-temperature sintering process. Oxidation at the bonding interface can degrade electrical conductivity and reduce joint strength.
In this study, two types of sinterable copper paste formulations were selected to evaluate their feasibility as substitutes for sintered silver. The experimental procedures included tensile and shear strength measurements to assess mechanical reliability, as well as thermal cycling tests (TCT) to simulate fatigue behavior under long-term thermal stress conditions. To further improve joint quality, process optimization targeting low void ratio was also implemented, as excessive porosity can adversely affect both thermal conduction and mechanical integrity. Cross-sectional inspection and microstructural analysis were conducted to investigate interfacial bonding behavior and failure mechanisms.
This work provides a comprehensive comparison between sintered copper and sintered silver, highlighting the performance potential of copper-based die-attach materials and analyzing the key challenges that must be overcome for commercialization in high-reliability power module applications. The findings reveal that while sintered silver still outperforms in terms of electrical and thermal performance, optimized sintered copper joints demonstrate comparable mechanical integrity and thermal fatigue resistance under certain conditions. Additionally, the influence of particle morphology, surface finish of the substrate, and sintering atmosphere were identified as critical factors influencing the joint quality of copper-based materials. Scanning Electron Microscopy (SEM) and Energy Dispersive X-ray Spectroscopy (EDS) analyses provided insights into microstructural evolution and oxidation patterns, confirming that controlled sintering environments and protective surface treatments are essential to mitigate interface degradation. These results suggest that with appropriate material formulation and process control, sintered copper has the potential to become a cost-effective and reliable alternative for future high-performance power electronic packaging.

 

Bio:
Hung-Chi Chang is now a Ph.D. Student in the Institute of Electronics, National Yang Ming Chiao Tung University, Taiwan. His interesting research topic is electrostatic discharge (ESD) protection design for semiconductors and integrated circuits.

Abstract:
An effective solution to significantly improve electrostatic discharge (ESD) robustness of the silicon carbide vertical double-diffused metal-oxide-semiconductor field-effect transistor (SiC VDMOSFET) is proposed by co-packaging a transient voltage suppressor (TVS) inside the package with SiC device together. The weakness of ESD test on SiC VDMOSFET is the gate-to-source mode (GS mode), where positive or negative ESD zapping is applied to the gate of the device while its source is grounded and its drain is floating. With co-packaged TVS, the 1700-V SiC VDMOSFET can pass human-body-model (HBM) ESD level of ± 8 kV in the GS mode test, as well as no degradation on its switching performance verified by double pulse test.

 

Bio:
My name is WU BING-ZONG. I am currently a second-year master's student at the Institute of Advanced Semiconductor Packaging and Testing at National Sun Yat-sen University. My research focuses on the application of copper-to-copper bonding in high-power modules. I am currently interning at the R&D department of ASE Group.

Abstract:
A comprehensive and systematic comparison of the bonding structure between the substrate and the pin holder, focusing on two copper-to-copper joining technologies—ultrasonic welding and conventional solder paste bonding. Due to copper’s excellent electrical and thermal conductivity, it is widely used in various electronic packaging modules, especially in high-power and high-current applications such as automotive electronics, battery systems, and power modules. Therefore, ensuring the quality, strength, and long-term reliability of copper-to-copper interconnections is critical not only for the performance of individual modules but also for the stability and safety of the overall system.

In this research, key evaluation metrics—including contact resistance and shear strength—were selected to quantitatively assess and compare the performance of the two bonding techniques. Ultrasonic welding enables direct solid-state bonding by applying high-frequency mechanical vibrations under ambient or low-temperature conditions. This method does not require additional filler materials such as solder paste or flux, which greatly simplifies the bonding process. Furthermore, it avoids common problems such as thermal damage, material incompatibility, and interfacial delamination often seen in conventional soldering processes. The joints formed by ultrasonic welding are tightly bonded and exhibit low electrical resistance and high mechanical integrity, making them highly suitable for high-frequency, high-current applications in advanced electronic systems.

On the other hand, conventional solder paste bonding involves the melting and solidification of a filler metal, which relies heavily on thermal processing and precise control of heat profiles. This process is susceptible to the formation of voids, cracks, and brittle intermetallic compounds due to gas entrapment, flux decomposition, and insufficient wetting. These defects can degrade both mechanical strength and electrical conductivity over time, especially under conditions of thermal cycling or vibration. Moreover, the high temperatures required for soldering can impose additional stress or damage on sensitive components or multilayer packaging structures, making the process less suitable for compact, high-density designs.

The experimental results of this study clearly demonstrate that ultrasonic welding provides superior electrical and mechanical performance compared to solder paste bonding. In addition to reduced contact resistance and higher joint strength, ultrasonic welding offers advantages such as process simplification, minimal thermal impact, no flux or filler residue, and enhanced long-term reliability. These characteristics make ultrasonic welding a highly promising technique for next-generation electronic packaging, particularly in demanding fields where durability, stability, and miniaturization are essential.

As power electronic systems continue to evolve toward higher integration, greater efficiency, and increased reliability, ultrasonic welding presents itself as a future-forward solution to overcome the limitations of traditional soldering. It aligns well with the industry’s pursuit of environmentally friendly, low-temperature, and robust interconnection methods. In summary, ultrasonic welding not only enhances bonding performance but also provides a solid technological foundation for the continued advancement of high-performance power modules and electronic devices.

 

Bio:
I am a researcher at the Institute of Scientific and Industrial Research, Osaka University, working in the Flexible 3D Integration Collaborative Research Laboratory. My research focuses on the back-end processes of semiconductor manufacturing, particularly on the evaluation of encapsulation resins, reliability testing, and performance analysis.

Abstract:
With the rapid advancement of electrification technologies, power modules, which are essential components that manage electrical currents by rectifying, amplifying, or switching, have expanded into the field such as electric vehicles, renewable energy, aerospace, and robotics. These modules typically consist of a substrate, a semiconductor die, and bonding wires, which are mounted and interconnected before being encapsulated for protection. However, increasing the demand for smaller, more efficient modules capable of enduring demanding operating environments, one promising strategy for reducing module size involves replacing traditional gel encapsulation with epoxy encapsulation, which eliminates bulky outer casings and can reduce packaging volume significantly. Therefore, to ensure durability in challenging conditions such as elevated temperatures, humidity, thermal cycling, and electrical stress, it is essential to thoroughly assess the reliability of epoxy encapsulation. Generally, failures in power modules often occur at the interface between the epoxy and substrate, due to the formation of gaps and voids arising from thermal stresses mismatches in the thermal expansion coefficients of as well as the epoxy’s glass transition.
Recently, various epoxy materials with high-glass transition temperature (Tg) resins, whose thermal expansion properties closely match those of copper substrates, have been developed and have mitigated many common failure modes that were mentioned above. In this context, cycloaliphatic epoxy resins have garnered significant interest due to their inherently rigid molecular structure and offer superior thermal stability, reduced moisture absorption, and enhanced dimensional stability, compared to conventional bisphenol A-based epoxies. As a result, these attributes make them particularly suitable for power modules exposed to rapid temperature fluctuations and high humidity, conditions that often cause repeated resin swelling and interface degradation. Moreover, cycloaliphatic epoxies typically exhibit higher Tg and improved thermal properties, approaching those of advanced engineering plastics. This makes them promising candidates for applications involving SiC power devices and other high-temperature environments where conventional epoxies may fall short.
In this study, we compare a cycloaliphatic epoxy resin used for encapsulating copper substrates with a conventional bisphenol A-type epoxy resin. Samples are fabricated using a face-down compression molding method that simulates actual device packaging. In order to compare their reliability, pressure cooker tests and power cycling tests were evaluated for their mechanical properties, interfacial delamination, and crack formation before and after tests by scanning acoustic tomography (SAT), shear strength tests, and scanning electron microscopy (SEM). These experiments are currently underway, and we anticipate that the results will serve as one of the key guidelines for material selection and encapsulation design, ultimately contributing to the enhanced durability of power modules.

 

Bio:
I am currently an R&D Engineer at Tong Hsing Electronic Industries, Ltd., specializing in the development and application of conductive paste printing and sintering technologies. Before joining Tong Hsing, I spent over a decade in the PCB industry, where I worked as a Product Engineer and R&D Engineer. During that time, I gained extensive experience in product development and developed a solid understanding of PCB manufacturing processes. With a strong background in electronic materials and process engineering, I am committed to advancing high-performance conductive materials for next-generation electronic packaging applications.

Abstract:
ABSTRACT
With the rapid development of high-power applications such as electric vehicles, high-speed charging systems, and smart grids, the power density within modules has significantly increased. This escalation places stringent demands on thermal management structures and electrical reliability. Traditionally, metal spacers (e.g., AlSiC, CuMo) have been employed as vertical interconnects and heat-conducting elements between devices and substrates in power modules. While these materials offer excellent performance, they come with high material costs, complex mechanical processing requirements, and risks associated with supply chain instability. Under the current trend of global supply chain restructuring, these issues pose challenges to design flexibility and cost control in high-end power modules.
On the other hand, ceramic substrates—owing to their high thermal conductivity, excellent electrical insulation, and thermal stability—have increasingly become the mainstream base materials for high-power modules. If vertical electrical interconnection can be realized through precision via drilling combined with high-temperature sintered conductive pastes, traditional metal spacer structures can potentially be replaced, while retaining electrical and thermal functionalities and reducing overall material costs. Furthermore, compared to conventional electroplating via-filling techniques, printed via-filling methods offer simpler processes and support for larger via sizes and diverse geometries, thereby enhancing manufacturing flexibility.
This study focuses on integrating high-temperature sintered metal paste via-filling technology with the Direct Plated Copper (DPC) process to achieve vertical interconnection and high-density metallization on ceramic substrates. High-temperature sintered pastes exhibit excellent conductivity and stable microstructures post-sintering, forming high-adhesion interfaces with ceramic via walls. Under optimized sintering conditions, their electrical performance can sustain operational voltages from several hundred volts to kilovolt levels and current loads of tens of amperes.
Simultaneously, the DPC process enables the fabrication of precision copper circuitry on ceramic surfaces via direct plating. This process supports low-impedance, locally variable thickness designs to meet regional electrical and thermal dissipation requirements. By integrating these two technologies, the need for traditional spacer structures can be eliminated, allowing ceramic substrates to achieve more highly integrated structural designs. This advancement ultimately enhances power density, reliability, and manufacturing flexibility in power modules.
In summary, this study aims to validate the feasibility and effectiveness of the proposed integrated process in high-power module applications. It will focus on key aspects such as via filling quality, electrical conductivity, voltage endurance, and interface reliability between the paste and substrate, providing concrete solutions for the design and manufacturing of next-generation high-power modules.

 

Bio:
Hello everyone, my name is Ming-Ru Wu, and I am currently a second-year master's student at the Institute of Advanced Semiconductor Packaging and Testing, National Sun Yat-sen University. I focus on research in semiconductor packaging technology, particularly in the design and testing of high-performance electronic devices. During my studies, I have participated in several semiconductor-related research projects, gaining valuable academic experience. Apart from my academic work, I enjoy playing table tennis. It not only helps me relax and unwind but also improves my concentration and reflexes. I also enjoy discussing the latest developments in technology with friends and hope to contribute to the semiconductor industry in the future. I aim to combine my professional knowledge and interests in my future career, constantly challenging myself, learning, and growing.

Abstract:
The thermal dissipation performance of Epoxy Molding Compound (EMC) plays a critical role in the reliability and efficiency of electronic power modules. This study compares the thermal dissipation performance of high Glass Transition Temperature (Tg) EMC and high thermal conductivity EMC to evaluate their effectiveness in managing heat in power module applications. High Tg EMC materials are characterized by superior thermal stability and enhanced resistance to thermal cycling, making them suitable for high-temperature environments. In contrast, high thermal conductivity EMC materials are designed to improve heat conduction and reduce the temperature rise within the module, ensuring more efficient thermal management.

This study aims to systematically investigate the thermal dissipation behavior in modules through experimental and simulation methods, comparing the differences between high Tg and high thermal conductivity Epoxy Molding Compound. The thermal conductivity of the materials used ranges from 0.8 to 3 W/m·K, evaluating the actual model in molding comparisons. By comparing the thermal properties and behavior of both materials, the study assesses their suitability for different thermal management challenges in power modules.

In order to confirm the thermal transfer behavior of Epoxy Molding Compound in modules, this study uses ANSYS to perform numerical simulations of thermal conductivity. The thermal properties of the materials are analyzed, and the temperature transfer conditions are compared with actual measurement results. These simulations help to validate the real-world situation and refine the predictive models of heat flow within power modules, ensuring accurate simulations for optimizing material selection and module design.

In addition to simulations, Scanning Electron Microscopy (SEM) was also used to observe the material structure. These high-magnification observations allow for a comparison of internal material differences, providing insights into the microstructure of the EMC and its impact on thermal dissipation. By correlating the experimental data with the material properties, this study identifies key factors affecting thermal dissipation efficiency and compares the differences in heat dissipation across different materials. The microstructural observations further enhance the understanding of how the material's composition, structure, and surface characteristics influence its thermal performance.

The results from this research show that high Tg EMC materials, while providing exceptional thermal stability and resistance to degradation under high-temperature conditions, might not offer the most efficient heat conduction, which is crucial for high-power applications. On the other hand, high thermal conductivity EMC materials excel in minimizing temperature rise within the module, ensuring faster heat transfer and superior thermal management efficiency. These materials are better suited for applications where efficient heat dissipation is critical.

 

Bio:
Lo-Ching Wu received the B. Mgt. degree in Department of Logistics and Operations Management from National Kaohsiung University of Science and Technology, Kaohsiung, Taiwan, R.O.C., in 2023. She is currently working toward the M.S. degree in Institute of Advanced Semiconductor Packaging and Testing, College of Semiconductor and Advanced Technology Research at National Sun Yat-sen University, Kaohsiung.

Abstract:
As the international gold price rises, the cost of gold (Au) wire bonding package increases accordingly. In the packaging industry, various out-source assembly and testing houses (OSATs) have successively replaced Au bonding wires with other metal wires such as silver wire, copper wire or aluminum wire. Among them, copper wire and aluminum wire are mainly used in consumer electronics, industrial products, and low-cost electronic products, while the more expensive gold, silver wire and other precious metal wires are employed in high-end products such as in automotive, military, and aerospace applications.
Automotive electronic products have a long-span life and the relevant product specifications are more stringent. If the bond-wires used in the product are prone to oxidation, corrosion and other adverse conditions, it will cause product failure and have a high probability of affecting the user's life safety. Therefore, automotive electronic products must have higher reliability standards and environmental test tolerance of temperature and humidity, longer product life cycle, high failure standards that should be included in the consideration of bond-wire selection for electronic packaging.
This study will explore using silver alloy wire to replace gold wire as the bonding wire for stacked NAND flash memory packages that aims to meet automotive grade levels of electronic products. In the experiments there are two types of silver alloy wires, referred as silver Type A and Type B. The composition of the Type A is Ag 96%, Pd 3.5%, other < 0.5%, and that of the Type B is Ag ≧ 98%, other < 2%. Both silver types have wire diameter of 0.7 mil (~17.5 m). In this paper, we apply the factorial design of experiment (DOE) and analysis of variance (ANOVA) to find out the significant factors of wire bonding process for two candidates of silver alloy wires. Ball shear strength is major one of quality factors for evaluation. Response Surface Method (RSM) is used to achieve the optimal parameters of the significant process factors.

 

Bio:
2018 ~ 2024 School of Materials Science and Engineering, Gyeongkuk National Univ., B.S. 2025 ~ present Advanced Packaging Integration Center, Korea Institute of Industrial Technology, Researcher 2025 ~ present Gyeongkuk National Univ. Materials Science and Engineering, Currently enrolled in a master's degree

Abstract:
INTRODUCTION
To meet the demands of micro-pitch I/O density in advanced packaging for AI and high-performance semiconductors, both substrate pad miniaturization and high-reliability soldering are essential. Conventional mass reflow (MR) processes are widely used due to their productivity; however, prolonged exposure to high temperatures (~260 °C for several minutes) can induce significant warpage and thermal damage. This becomes increasingly problematic in fine-pitch applications where reduced solder volumes exacerbate defects such as opens or bridging due to warpage.
In contrast, laser selective reflow (LSR) offers a more localized and energy-efficient bonding approach by selectively irradiating only the solder joint areas, enabling rapid solder melting while minimizing thermal impact on the entire substrate. This study evaluates the advantages of LSR bonding by comparing the mechanical reliability and fracture characteristics of SAC305 solder joints formed on direct palladium immersion gold (DPIG) surfaces, a Ni-less alternative designed for improved RF performance and sustainable processing.

EXPERIMENTAL METHODS
The test vehicle used in this study was an FR-4-based PCB with solder mask-defined Cu pads (350 µm diameter). The surface finish applied was DPIG, comprising 0.15 µm of Pd followed by 0.15 µm of Au. SAC305 solder paste was stencil-printed onto the pads, and 450 µm diameter SAC305 solder balls were aligned and mounted uniformly.
LSR bonding was performed using a 1070 nm fiber laser with a 15 × 15 mm beam area. The laser was irradiated at 1.56 W/mm² for 2 seconds, reaching a peak joint temperature of ~250 °C. MR bonding was conducted in a nitrogen convection oven with a 6-minute reflow cycle, peaking at ~250 °C.
High-speed shear testing (1 m/s, 50 µm shear height) was conducted on 25 samples per condition to ensure statistical significance. Fracture surfaces were examined via scanning electron microscope (SEM) and classified as ductile (0–25% brittle), mixed (25–75%), or brittle (75–100%) based on the brittle fracture area ratio.
RESULTS AND DISCUSSION
X-ray analysis confirmed that void formation was minimal in both bonding methods, with the LSR process exhibiting negligible voids. Figure 1 presented the internal solder microstructures. The MR samples (Figure 1a and 1b) exhibited large columnar β-Sn grains with a coarse eutectic network, whereas the LSR samples (Figure 1c and 1d) showed fine equiaxed grains and a uniformly distributed eutectic structure, resulting from rapid localized heating and solidification.
In both bonding cases, Cu₆Sn₅ intermetallic compounds (IMCs) were formed at the solder–substrate interface. The Pd/Au layers of the DPIG surface finish were fully consumed during bonding, leading to direct Cu–Sn interfacial reactions. As shown in Figure 2, the IMC thickness in the LSR samples was significantly thinner than that in the MR joints.
Shear strength measurements indicated that the LSR samples exhibited higher mechanical strength than the MR samples, which was attributed to the formation of thinner IMCs and a more refined microstructure. Fracture mode analysis also confirmed that the LSR joints exhibited a lower ratio of brittle fracture compared to the MR joints.

CONCLUSION
The findings demonstrate that LSR bonding on DPIG surfaces provides superior joint reliability, higher shear strength, and reduced brittle fracture behavior compared to traditional MR bonding. Furthermore, by eliminating the Ni layer and minimizing thermal exposure, the LSR + DPIG combination supports both RF performance and green manufacturing objectives, such as energy efficiency and material sustainability.

 

Bio:
Ms. Chih Chieh Huang is currently an undergraduate student in the Department of Chemical Engineering and Materials Science at Yuan Ze University. Her research focuses on electromigration reliability of micro-joints in advanced packaging, with particular emphasis on surface finishes such as ENEPIG and ultra-thin Ni(P). Integrating finite element simulation with experimental characterization, he investigates failure mechanisms at the microscale. Her work also explores the impact of 5G high-frequency signal transmission on the electrical integrity and structural stability of packaging materials, aiming to develop reliable and low-resistance interconnects for next-generation high-speed communication systems.

Abstract:
The incessant trend toward ultrathin, multifunctional electronics necessitates a continuous shrinkage in the joint size, result in serious electromigration-induced failures in the join structures. In this study, electromigration reliability of eutectic Sn-Cu (Sn-0.7Cu) micro joints with three different surface coatings over the Cu pads was investigated by ANSYS simulation and metallographic analysis. This study reported that the ultrathin-Ni(P)-type ENEPIG surface finish not only promotes larger Sn grains in solder bumps in the as-reflow state (compared to OSP) but also markedly reduces the electrical resistance as well as Joule heating of micro joints (compared to traditional ENEPIG), both of which favor retarding Cu pad depletion and enhancing joint electromigration reliability. Based on the results of the present studies, we concluded that the ultrathin-Ni(P)-type ENEPIG surface finish significantly mitigates electromigration-induced damage to Cu traces while improving micro joint structural integrity and electrical reliability.

 

Bio:
Student from Department of Aerospace and Systems Engineering, Feng Chia University, Taichung 407, Taiwan, R.O.C

Abstract:
To alleviate the high computational cost, extensive modeling effort, and accuracy limitations associated with conventional simulation-driven machine learning, such as artificial neural network (ANN), random forest (RF), support vector machine (SVM), gaussian process regression (GPR), and convolutional neural network (CNN), this study aims to introduce a systematically optimized ensemble stacking learning (ESL) framework, the performance of which is driven by a structured optimization process that selects the best combination of base ML model candidates, an appropriate meta-learner, and finely tuned hyperparameters. This framework involves training multiple base ML models (e.g., ANN, RF, SVM, GPR, CNN) along with a meta ML model that learns to integrate their predictions. The proposed ESL framework is evaluated by applying it to accurately and effectively predict the process-induced warpage of an SiC power MOSFET module during manufacturing. To characterize the process-induced warpage, a finite element analysis (FEA)-based process modeling technique is developed. The effectiveness of the proposed ESL framework is demonstrated by comparing its predictions with those obtained from an ANN trained on a larger dataset. The results confirm that the proposed ESL framework delivers significantly higher prediction accuracy than any individual base ML model, thereby substantially reducing reliance on computationally intensive simulations.

 

Bio:
Zi-Chen Fang received the B.Sc. degree in Department of Biomechatronic Engineering from National Ilan University, Ilan, Taiwan, R.O.C., in 2023, He is currently working toward the M.S. degree in Institute of Advanced Semiconductor Packaging and Testing, College of Semiconductor and Advanced Technology Research at National Sun Yat-sen University, Kaohsiung.

Abstract:
The dielectric resonator antenna (DRA) possesses lower losses and higher efficiency compared to metal antennas at high microwave and millimeter-wave frequencies. DRAs are commonly used in compact portable wireless devices due to the ease of packaging and integration. A DRA is typically constructed of ceramic material for its high-Q potential that radiates electromagnetic energy transition from a higher dielectric constant to air. In this study, various DRA geometries are fabricated on organic substrates by using semiconductor molding organic materials and processes. A hexagonal-shaped DRA is proposed for investigation. For comparison, a rectangular DRA of similar dimensions and the same height is also considered. The configurations of both the hexagonal and rectangular DRAs with microstrip feedlines are illustrated in Figure 1. The designed dimensions of the hexagonal and rectangular DRAs are proposed to be simulated for comparison.
Both DRA shapes are fed by a microstrip line on the same substrate material, sharing the same dielectric constant. The simulation frequency range is set between 24 and 32 GHz, centered at 28 GHz. The purpose of the study is to explore the effect of geometric shape on resonant frequency and bandwidth characteristics. Preliminary simulated results of the reflection coefficients, S11, are presented in the Fig. 2, where the resonant frequencies of the hexagonal and rectangular DRAs are compared. These geometric differences cause DRAs to exhibit distinct resonant modes and radiation field patterns. Further optimization of the hexagonal DRA geometry will be explored as a promising strategy to improve antenna performance in the millimeter-wave frequency range. Electric field distributions, gain, and radiation patterns for the proposed DRAs will also be revealed. Additional performance metrics, including resonant frequency, −10 dB impedance bandwidth, radiation patterns, and gain, will be presented in subsequent article.

 

Bio:
Zhao Heng-Chen received the B.Sc. degree in mechanical engineering from National Kaohsiung University of Science and Technology, Kaohsiung, Taiwan, R.O.C., in 2023, She is currently working toward the M.S. degree in Institute of Advanced Semiconductor Packaging and Testing College of Semiconductor and Advanced Technology Research at National Sun Yat-sen University, Kaohsiung.

Abstract:
ABSTRACT
Dielectric resonator antenna (DRA) offers advantages such as low metallic loss, high efficiency, broadband characteristics, and easy manufacturing, which is very suitable for modern wireless communication systems in millimeter wave applications. In this work, semiconductor molding material and processes are used to fabricate DRAs of various shapes on the organic substrates. A conical and truncated-conical DRAs are proposed for investigation. A truncated cone is a shape formed by cutting off the apex to be a plane parallel to the base (bottom plane) or, equivalently, perpendicular to the height. For comparison, a cylindrical DRA with the same base diameter and height as the conical and truncated-conical structures is also considered. Figures 1 (a) and (b) illustrate the conical and truncated-conical DRAs, respectively, which are fed with a microstrip feedline on the same substrate of the dielectric constant different with the proposed DRA’s material. On count of the configurations of the conical and truncated-conical DRAs are proposed to do simulation.
The simulation frequency range is set between 20 and 50 GHz, centered at 28 GHz. The purpose of the study is to explore the effect of geometric shape on resonant frequency and bandwidth characteristics. Preliminary simulated results of the reflection coefficients, S11, for both proposed DRAs compared with the cylindrical DRA of the same base diameter are presented in the Fig. 2. The conical and truncated-conical DRAs demonstrate higher resonant frequencies than the cylindrical counterpart. The different resonant modes exhibit based on the facts of the DRA's geometric transformation and radiate the different EM-field patterns depending on their shape. Further studies on optimizing the geometry of various shaped DRAs will be presented as an effective approach for enhancing antenna performance in the mm-wave frequency range. The electric field distribution inside the proposed DRAs and antenna gain, radiation patterns will be revealed. Further performance metrics, including −10 dB impedance bandwidth, radiation gain, and radiation patterns will be discussed in the subsequent full paper.

 

Bio:
Tzu-Ching Sun received the B. Sc. degree in electrical engineering from National Taiwan Ocean University, Keelung, Taiwan, R.O.C., in 2023. She is currently working toward the M. S. degree in Institute of Advanced Semiconductor Packaging and Testing, College of Semiconductor and Advanced Technology Research at National Sun Yat-sen University, Kaohsiung.

Abstract:
In package substrate layout design, an area typically defined by a "keep-out" zone is enforced to be free of copper or any other board feature, such as traces, pours, vias, and even component pads within this zone. In the high-speed substrate layout, the copper keep-out is a designated area where other board copper features are prohibited to minimize electrical interference and improve signal integrity. High speed signals are susceptible to signal reflections, crosstalk, and impedance variations. This is crucial for signal integrity, minimizing unwanted coupling, such as crosstalk and parasitic inductive and capacitive effects, and ensuring proper impedance control to reduce signal reflections. By maintaining keep-out zone in substrate layout, these abovementioned impacts are minimized, leading to a stable and reliable signal transmission. This study explores signal integrity related to the presence or absence of a copper keep-out zone, specifically focusing on signal integrity of the differential-pair routing traces in the adjacent layers. Ansys HFSS software solver is used to simulate the transmission loss of the differential-pair signals and the degree of mutual interference with the adjacent differential-pair signals with and without the copper keep-out.

 

Bio:
Yu-Hur Shih received the B.Sc. degree in electronic engineering from National Ilan University, Ilan, Taiwan, R.O.C., in 2023, She is currently working toward the M.S. degree in Institute of Advanced Semiconductor Packaging and Testing College of Semiconductor and Advanced Technology Research at National Sun Yat-sen University, Kaohsiung.

Abstract:
Dielectric resonator antenna (DRA) possesses some attractive features such as low loss, small size, wide bandwidth, ease of excitation, and high degree of design freedom to meet the demands for applications in millimeter-wave (mm-wave) mobile communication. In the mm-wave frequency range, increased propagation losses and reduced effective aperture size necessitate antennas with higher efficiency and improved directionality to maintain overall system performance.
Dielectric Resonator Antennas (DRAs) have emerged as highly promising candidates for wireless and mobile mm-wave applications due to their advantages in efficiency, miniaturization, and frequency stability. DRAs utilize high-permittivity, low-loss dielectric materials as resonators and radiate electromagnetic energy through their intrinsic resonant modes. One of the most crucial factors affecting DRA radiation performance is its geometric configuration, which directly influences mode distribution, field patterns, impedance matching, bandwidth, and gain.

We present the configurations of the proposed trapezoidal and pyramidal (prism) DRAs. The trapezoidal DRA has a bottom side length of DL, side width of DLW, a top side length of DL, side width of DUW, a height of Dh, and a dielectric constant of erDRA (= 21), loss tangent of 0.008. It is placed at the center of a square substrate with a side length of SW, thickness of h, dielectric constant of 2.2, and loss tangent of 0.009. A pyramidal (prism) DRA with a same side length of DL, a height of Dh, and the same dielectric constant of erDRA as the trapezoidal type is also placed at the center of a square substrate that has a same size as trapezoidal DRA, for comparison. A rectangular DRA is also included and simulated for comparison. Among the various known geometries, the rectangular DRA is the most commonly used due to its simple structure and ease of fabrication. However, its uniform top and bottom surfaces often lead to modal limitations, resulting in narrower bandwidth and lower gain. To address these limitations, this study investigates tapered modifications to the top surface of the rectangular DRA, transforming it into trapezoidal and pyramidal (or prism) shapes. Specifically, by reducing the top width of the original rectangular DRA to 2 mm (trapezoidal) and 0 mm (prism), the radiation characteristics and gain are expected to improve significantly.

 

Bio:
Department of Chemical Engineering at Sungkyunkwan University. My research focuses on multifunctional flexible devices, including stretchable electronics, soft sensors, and bio-interfacing platforms. I am particularly interested in integrating electrical functionality with mechanical compliance for next-generation wearable and implantable systems. My recent work includes the development of liquid metal-based circuit architectures and textile-integrated electronic devices for soft robotics and biomedical applications.

Abstract:
Organic electrochemical transistors (OECTs) have garnered significant attention as emerging components for a wide range of bioelectronic applications, including real-time biological sensing, electrophysiological signal recording, and neuromorphic information processing. Due to their ability to operate efficiently in aqueous environments—where most biological reactions naturally occur—OECTs are particularly well-suited for seamless integration with living tissues and biofluids. One of the critical aspects in optimizing the performance of OECTs is a deeper understanding of how electrolyte materials interact with the organic semiconductor channel. In particular, ion transport within the electrolyte governs electrochemical doping and screening effects that directly modulate the channel conductivity and switching characteristics.

To enhance device sensitivity, stability, and signal transduction, materials with high ionic mobility such as ion gels and ionic liquids have been widely explored. However, despite numerous studies reporting performance improvements via the introduction of novel ion-conducting materials or surface modifications, the detailed mechanism of pre-diffusion-induced electrochemical effects remains poorly understood. In this study, we introduce a new class of solid-state, choline-based ionic electrolytes and systematically investigate the pre-diffusion effect of [Ch][Ace] ionic liquids on the electrical performance of OECTs. The choline-based ions serve not only as efficient charge transporters but also as functional dopants that can interact with charged species within the conducting polymer matrix. This dual functionality enables modulation of ionic screening and capacitance behavior, ultimately leading to an optimized channel environment.

Our results demonstrate that the presence of [Ch][Ace] promotes a shift in the gate voltage of maximum transconductance toward 0 V, which significantly reduces power supply noise and enhances the quality of recorded biological signals. Specifically, the system achieves high signal-to-noise ratios in electrocardiogram (ECG) monitoring without the need for external biasing or amplification circuitry. Furthermore, the choline-based solid electrolyte exhibits excellent biocompatibility, non-volatility, and mechanical stability, making it a compelling candidate for long-term use in wearable or implantable bioelectronics. The findings presented here not only highlight the functional potential of choline-derived ionic materials but also provide insight into the pre-diffusion mechanisms that govern ion–channel interactions in OECTs, paving the way for the development of next-generation organic biosensors with improved reliability, sensitivity, and user comfort.