Bio:
Frank earned his Ph.D. from Carnegie Mellon University in Pittsburgh, Pennsylvania. He is currently a Vice President at TSMC Technology Inc. in San Jose, California, where he leads the Custom Design Methodology group. His work focuses on advancing analog/RF design automation and migration for cutting-edge nodes, as well as pioneering 3D COUPE silicon photonics design and analysis methodologies. Prior to his role at TSMC, Frank served as Vice President at Synopsys in Mountain View, California. During his tenure there, he significantly contributed to a diverse array of products, including IR/EM analysis, RC extraction, advanced delay calculation, static timing analysis, timing optimization, advanced placement and routing, physical synthesis, cell characterization, and both SPICE and fast SPICE circuit simulation.
Abstract:
As artificial intelligence workloads scale exponentially, energy efficiency has emerged as a critical bottleneck in sustaining performance growth. This keynote explores how TSMC’s advanced semiconductor technologies are reshaping the energy-performance landscape for AI. We will highlight the latest innovations across process nodes, 3D integration, and advanced packaging—including CoWoS®, InFO®, and the COUPE architecture—that are purpose-built to reduce energy per operation while supporting massive compute density. The talk will delve into how TSMC’s technology platforms enable AI accelerators, GPUs, and edge AI chips to achieve unprecedented power efficiency, addressing both datacenter and edge deployment challenges. By bridging silicon scaling and system-level optimization, TSMC is empowering its ecosystem to build sustainable AI infrastructure for the future.