Sessions Index

Bio:

Shaw Fong currently serves as the Principal Engineer at one of the Kulim Campuses of Intel Malaysia. With ~24 years of extensive experience in the semiconductor industry, he has held various positions that encompass a wide range of technical domains including packaging processes, assembly, testing, and material technology development. Throughout his career, Shaw Fong has played a pivotal role in advancing multiple packaging and product development initiatives, with a particular focus on warpage development and mechanical testing. His technical acumen and leadership have significantly contributed to innovative solutions and improved efficiencies within these critical areas.

In 2023, Shaw Fong was honored with the prestigious IEEE/EPS William Chen Distinguished Award, recognizing his significant contributions to the IEEE in driving advancement in semiconductor assembly and testing field. He has been nominated to the IEEE/EPS Board of Governance and serves as Region-10 Program Director. He is also engaging in IEEE Malaysia Section as the Executive Committee (Industrial Relations). Additionally, he is an active Committee Member of both the Electronic Engineering Technical Division (eETD) and the Material Engineering Technical Division (MaTD) of the Institution of Engineers Malaysia (IEM). His recent designation as a Professional Engineer by the Malaysia Board of Engineers (BEM), along with his advisory roles with various local universities, underscores his unwavering commitment to engineering excellence and education. Shaw Fong holds a total of 12 combined patents and trade secrets, and he is a key driver of technical innovation at Intel Malaysia, having achieved over 90 technical publications. Outside of his professional endeavors, Shaw Fong is a devoted family man with two sons and a passionate sports enthusiast, particularly in football, where he proudly supports Liverpool FC.

Abstract:

The global semiconductor industry is undergoing a critical transformation, driven by the convergence of advanced packaging, heterogeneous integration, and AI-centric applications. At the forefront of this evolution is the Heterogeneous Integration Roadmap (HIR), developed by the IEEE Electronics Packaging Society (EPS), which outlines a 15-year vision for integrating diverse components—logic, memory, sensors, and photonics—into compact, high-performance systems. HIR serves as a pre-competitive guide for industry, academia, and governments, fostering collaborative innovation and standardization across the semiconductor value chain [1].

Malaysia is aligning its national ambitions with this global framework through the National Semiconductor Strategy (NSS), launched in May 2024. This ten-year, three-phase roadmap aims to elevate Malaysia from a traditional OSAT hub to a global leader in IC design, advanced packaging, and wafer fabrication, supported by RM25 billion in fiscal incentives and a target of RM500 billion in investments [2][3]. Regional ecosystems are critical to this transformation. Penang’s “Silicon Design @5km+” initiative, Selangor’s SIDEC and ASEM programs, and Sarawak’s SMD Semiconductor—home to Borneo’s first Chip Design Centre—are building robust design and packaging capabilities [4].
These efforts position Malaysia as a strategic partner for Taiwan, whose semiconductor leadership complements Malaysia’s strengths. Opportunities for collaboration include joint R&D in heterogeneous integration, talent exchange, and cross-border investment. By aligning Malaysia’s NSS with the IEEE HIR, both nations can co-create a resilient, innovation-driven semiconductor ecosystem that supports global supply chain diversification and regional technological sovereignty.

 

Bio:
Yeong Seok Ham is currently a Ph.D. student in the Department of Mechanical Engineering at KAIST, Republic of Korea. His research focuses on mechanical reliability of semiconductor interconnects, including interfacial fracture energy measurements and reliability assessment of ultra-low k dielectric materials. In addition to BEOL structures, he is also conducting research on interfacial adhesion and reliability evaluation of advanced packaging materials such as underfill-glass and underfill-Cu interfaces. His work aims to improve interfacial adhesion and structural robustness in advanced semiconductor devices.

Abstract:
Over the past several decades, the semiconductor industry has undergone remarkable advancements in the scaling of integrated circuits and the increase in transistor density, driving significant improvements in the performance of microelectronic devices. As device dimensions continue to shrink, the line width and spacing in back-end-of-line (BEOL) interconnects have also been reduced, leading to an increase in resistance-capacitance (RC) delay, which hampers the signal transmission speed of chips. To mitigate RC delay, ultra-low k (ULK) dielectrics have been employed in intermetal dielectric (IMD) layers, with carbon-doped silicon oxide (SiOC:H) being one of the most commonly used ULK dielectrics. However, the high porosity of ULK poses mechanical reliability challenges, including cracking and interfacial delamination at the interface with SiCN (etch stop layer). These mechanical failures occur under varying fracture modes, as the mode mixity of applied loads depends on factors such as the position within the interconnect structure, the stack configuration, and the material properties. Thus, the quantitative evaluation of fracture energy under different fracture modes is crucial for enhancing the mechanical reliability of SiCN-ULK interfaces.

In this study, the fracture energy of SiCN-ULK interfaces under three plasma treatment conditions (Pristine, H2, and NH3) was quantitatively measured using fracture mechanics-based experiments. Double cantilever beam (DCB) test and four-point bending (FPB) test were conducted to measure the fracture energy Gc under pure mode I and mixed-mode loading conditions, respectively. Fracture surface analysis were conducted using optical microscopy (OM), atomic force microscopy (AFM), X-ray photoelectron spectroscopy (XPS), transmission electron microscopy (TEM), and focused ion beam- scanning electron microscopy (FIB-SEM) to elucidate the fracture mechanism depending on fracture modes.

As a result of DCB test, there was no significant increase in Gc regardless of the plasma treatment conditions. In contrast, the results of the FPB test showed that the Gc was increased by approximately 43.1% by H2 plasma treatment, and by approximately 67.5% by NH3 plasma treatment, compared to the pristine condition. From the fracture surface analysis, the discrepancy in results between the DCB test and the FPB test has been attributed to the difference in crack paths under different fracture modes. This indicates that while plasma treatment is effective in improving mechanical reliability under mixed-mode loading, it has a limitation in enhancing the mechanical reliability against cohesive failure under pure mode I loading.

This study provides insights into the influence of plasma treatment on the mechanical reliability of SiCN-ULK interfaces under varying fracture modes, contributing to the design of mechanically robust BEOL interconnects capable of withstanding diverse fracture conditions.

Keywords: Mechanical reliability, Back-end-of-line, Ultra-low k dielectrics, Fracture energy, Fracture mode, Crack path difference

Acknowledgements: This work was supported by Samsung Electronics Co., Ltd (IO240522-10052-01)

 

Bio:
Ming-chun Hsieh is a researcher at Flexible 3D System Integration Laboratory and a PhD student at the university of Osaka, Japan. She has over 10 years of experience in packaging reliability analysis, specializing in electron microscopy techniques and the development of metal pastes. Her research focuses on advancing packaging technologies through materials characterization and reliability assessment.

Abstract:
With the increasing demand for higher packaging density in modern electronics, continuous innovations are being made in the manufacturing technologies, constituent materials, and structural designs of packaging substrates. Consequently, engineers and researchers face growing challenges in evaluating the interconnection reliability of newly developed substrates with diverse architectures. Failures in packaging substrates are widely recognized to be strongly influenced by mismatches in the coefficient of thermal expansion (CTE) among the layered structural materials. Although various reliability evaluation methods have been proposed to simulate damage occurring during manufacturing and in-field operation, a widely applicable and efficient testing approach has yet to be fully established. The thermal cycling test (TCT) is commonly employed to assess interconnection reliability in semiconductor packaging substrates. However, it is inherently time-consuming. To reduce the test duration, increasing the upper temperature limit is a frequently adopted strategy. Nevertheless, the selection of this upper temperature limit is often based on empirical practices rather than systematic criteria. In this study, we focused on the glass transition temperature (Tg) of the build-up film in the packaging substrate, as its physical properties—including CTE—undergo significant changes when the temperature exceeds this threshold. TCT was performed under two thermal conditions: one with the upper temperature below Tg, and another above Tg. In parallel, substrate warpage was experimentally measured at 150 ºC and 175 ºC using a 3D metrology system.
Two three-layer stacked packaging substrates were intentionally fabricated using identical materials and dimensions, with the build-up film having a Tg of 153 ºC, but differing in interconnection reliability. This difference was introduced by applying distinct electroless Cu plating methods at the micro-via bottom. Specifically, substrate A incorporates an electroless Cu plating layer with a higher density of voids—i.e., structural defects—than substrate B. Both substrates were subjected to TCT under the two conditions: Condition 1, cycling between -55 ºC and 150 ºC; and Condition 2, cycling between -55 ºC and 175 ºC, with each temperature held for 15 min per cycle. The upper temperature limits were selected with reference to the Tg of the build-up film.
Under Condition 1, substrate B exhibited a Life(10%)—defined as the cycle count at which 10% cumulative failure occurs—of approximately 300 cycles, while substrate A reached approximately 900 cycles, consistent with the expected difference in reliability. However, under Condition 2, where the upper temperature exceeded the Tg of the build-up film, the Life(10%) values of both substrates converged to approximately 100 cycles, making it difficult to distinguish their relative reliability. These TCT results will be analyzed in conjunction with the measured substrate warpage shown in Fig.1 during our presentation to evaluate whether the Tg of the build-up film can serve as a meaningful reference when selecting the upper temperature limit in TCT-based reliability testing.

 

Bio:
I am Shen-Yu Yang. I come from Tainan, Taiwan and graduate with a master's degree in Institute of Material Science & Engineering from National Central University. In graduate school, I was major in solid oxide fuel cell. After that, I have been in WNC Corporation, WNC provides comprehensive technical support in RF antenna design, software design, hardware design, mechanical design, system integration, user interface development, and product testing & certification. I am a technical supervisor in Advanced Mfg. Process Development Center and involved in advanced manufacturing processes about molding process and EMI shielding. In addition, I participate in radar and antenna package including material and process selection. Besides actual products manufacturing, I have also used simulation tool to simulate PCB/PCBA warpage. Based on PCB/PCBA simulation tool, I can know how to modify every PCB layer circuit. It is an honor to attend Impact 2025.

Abstract:
The performance demands for automotive electronic products are steadily increasing, leading to strict reliability requirements. The Network Access Device (NAD) module is a key hardware component that enables wireless communication and connectivity in vehicles, presents coplanarity issue due to its relatively large dimensions. As the NAD module must be mounted onto the main board to function properly, there is an increasing need to meet tighter warpage specifications. Additionally, to satisfy electromagnetic interference (EMI) shielding requirements, a metal structural component referred to as the shielding frame and cover, is mounted onto the printed circuit board (PCB). The combined effects of this shielding structure and modularized PCBA result in a more complex warpage behavior. In this study, a finite element analysis (FEA) approach is applied to simulate the structural behavior of the NAD module with an attached shielding frame at the module level. The mechanical model consists of the PCB, mounted components, traces, shielding frame, and ball grid array (BGA). To accurately predict PCB warpage, key simulation parameters, such as contact definitions, element birth and death techniques, and reference temperatures, are carefully defined because they significantly influence the warpage contour and magnitude. The simulation conditions are categorized into two groups: one investigates the reference temperature of the shielding frame, and the other examines the modeling for solder structure underneath the shielding frame. The simulation results based on the finalized settings are then compared with actual warpage measurements obtained using a 3D optical profiler. The study aims to evaluate the influence of the shielding frame on PCB warpage behavior and provide insights for future design optimization.

 

Bio:
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Abstract:
In recent years, as mobile devices and high-frequency communication components continue to evolve towards thinner, smaller, and higher performance, electronic packaging technology has been facing more severe reliability challenges. Although the Flip-Chip structure has become an indispensable mainstream technology in high-performance applications, its mechanical lifespan under thermal cycling environments remains a concern. When the chip is connected to the substrate through solder balls, the difference in the coefficient of thermal expansion (CTE) between the chip and the package substrate leads to repeated deformation during thermal cycling, resulting in solder ball fatigue, crack propagation, and even complete package failure. Typical solutions rely on full filling underfill to provide overall stress redistribution and mechanical support. However, underfill technology still presents several limitations, such as long dispensing and curing times, difficulty in rework, and challenges in flux flow control, which can result in voids or packaging defects. To address these issues, strategies involving "localized reinforcement" and "material reduction" have begun to gain attention. This study focuses on the potential of the epoxy flux adhesion method in wafer-level chip scale packaging (WLCSP). Unlike full-coverage underfill, epoxy flux uses selective filling to reinforce only the areas around the solder balls where stress tends to concentrate. This approach strikes a balance between mechanical strength and process flexibility, while also reducing material usage and manufacturing costs. It is particularly suitable for mid-range products or cost-sensitive applications. In this study, a comprehensive three-dimensional model was constructed using the finite element method (FEM) to evaluate the effects of different epoxy flux fill heights on solder ball reliability. The simulation was based on a temperature cycling test (TCT) ranging from -40°C to +90°C, with lead-free SAC305 solder as the interconnect material. The model incorporated package geometry, material nonlinearity, and thermo-mechanical coupling to simulate stress evolution and equivalent plastic strain accumulation during thermal cycling. To improve simulation accuracy, material properties and geometric parameters of experimental samples were collected and used for result validation through cross-comparison.
Simulation results showed that when the epoxy flux fill height reached 100% of the solder ball height, it provided optimal mechanical support for the package and effectively limited the growth of equivalent plastic strain. Compared to the unfilled baseline model, the strain in high-stress areas was reduced by approximately 17.2%, as shown in Figure 3. Even at 60% fill height, a noticeable reduction in deformation was observed. These results demonstrate that the local reinforcement strategy can significantly enhance thermal cycling life without requiring full encapsulation. Compared to traditional underfill, epoxy flux offers greater process flexibility and material efficiency, aligning well with future trends in electronic module design focused on high efficiency and low material consumption. In conclusion, epoxy flux, as a new reinforcement solution that simplifies processing while improving reliability, shows great potential for applications in high-frequency and space-constrained conditions. Future research could further explore its material characteristics, fluidity, and thermosetting reaction mechanisms, as well as integrate and compare it with other selective reinforcement technologies such as local underfill or sidefill, to establish a more comprehensive packaging reliability solution.

 

Bio:
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Abstract:
With the rapid advancement of high-performance computing (HPC) and artificial intelligence (AI) technologies, large-area electronic packaging - often exceeding 100 × 100 mm²—has become increasingly prevalent. While these large-format packages support higher power delivery and integration density, they also introduce significant reliability challenges, particularly with regard to the durability of the solder joints. A major concern is the degradation of the solder joint during thermal cycling testing (TCT), which replicates the mechanical and thermomechanical stresses encountered in real-world operating and environmental conditions. In such packages, warpage and mismatches in the coefficients of thermal expansion (CTE) among constituent materials can result in severe localized stress concentrations, particularly at the outermost corner solder joints. This study systematically investigates the influence of the presence of edge bonds and its interaction with solder joints under TCT conditions. Three edge bond configurations were analyzed: (1) without edge bond, (2) with edge bond embedded in the substrate but not contacting solder joints, and (3) with edge bond directly contacting the first row of solder joints. Finite element analysis was employed to simulate stress distributions and identify high-risk failure zones for each configuration.
The simulation results indicate that the highest energy concentration occurs consistently at the top of the outermost corner solder joint. This location is especially prone to failure due to exposure to mechanical strain and warpage-induced deformation. In particular, both the absence of edge bonding and the direct contact between the edge bond and solder joints exacerbate energy accumulation in this region, increasing the likelihood of early failure. On the contrary, edge bonding that avoids direct contact with solder joints effectively redistributes stress and shifts the critical energy zone away from the outermost joints. These results confirm that edge bonds function as mechanical buffers, mitigating CTE-induced stress and delaying crack initiation in vulnerable solder joints. However, the efficacy of this buffering depends on avoiding direct mechanical coupling between the edge bond and the solder balls. Direct contact can inadvertently transmit stress rather than absorb it, counteracting the intended stress-relief function. Therefore, the implementation of strategic edge bonds - specifically designed to avoid direct solder joint - can significantly enhance solder joint and overall package robustness during thermal cycling. This insight is particularly valuable for the design of large-area packages in next-generation HPC and AI applications.

 

Bio:
Yuan-Hong Ding is currently a master's student in the Department of Mechanical and Electro-Mechanical Engineering at National Sun Yat-sen University, working under the supervision of Dr. Meng-Kai Shih in the Micro-Packaging Mechanics Design and Analysis Laboratory (MPMDA Lab). He holds a bachelor's degree in Mechanical Engineering from Tamkang University and is currently focusing on research in the field of electronic packaging reliability.

Abstract:
Fan-out packaging has gained widespread adoption in portable electronic products such as smartphones and laptops due to its high I/O density and compact form factor. However, its mechanical integrity under drop impact remains a critical reliability concern, particularly for solder joints. This study investigates solder joint behavior during drop impact events through a two-phase approach combining experimental material characterization and finite element analysis. Initially, uniaxial tensile tests were performed to examine the strain rate-dependent mechanical response of polyimide (PI). The results indicated that both the Young’s modulus and yield strength of PI increased with strain rate, confirming its viscoelastic sensitivity. These material properties were incorporated into a detailed finite element model of a board-level assembly to accurately simulate dynamic drop conditions. Simulations were conducted in accordance with JEDEC standards and validated against published experimental data, confirming the model’s accuracy in capturing solder joint stress behavior.
The validated model was subsequently employed to assess the effects of structural and material parameters on solder joint reliability using response surface methodology (RSM). The analysis revealed that the Young’s modulus of PI significantly influences stress accumulation within the solder joints. Increasing both the modulus and thickness of the PI layer, while concurrently reducing die thickness and the modulus of the epoxy molding compound (EMC), effectively reduced von Mises stress in the solder balls. Based on the RSM-derived optimization framework, the ideal parameter set was determined as follows: a die thickness of 370 μm, PI thickness of 6 μm, PI modulus of 5.4 GPa, underfill modulus of 7 GPa, and EMC modulus of 17.4 GPa. This optimized configuration achieved a 25% reduction in von Mises stress relative to the baseline design, indicating improved drop resilience. Further investigation demonstrated that increasing the underfill modulus to 15 GPa yielded additional benefits, lowering the von Mises stress in the solder region of copper pillar bumps (CPB-SnAg) from 36.2 MPa to 25.8 MPa, and the maximum principal stress in the copper portion (CPB-Cu) from 80.7 MPa to 65.5 MPa—without compromising solder joint integrity. These findings underscore the importance of PI mechanical properties, structural optimization, and judicious material selection in enhancing the drop reliability of fan-out packages. The methodologies and insights presented offer a practical approach to advancing the robustness of next-generation electronic devices under mechanical shock environments.

 

Bio:
Jui-Chang Chuang, also known as Oscar, is a Ph.D. candidate advised by Professor Chang-Chun Lee. His research specializes in mechanical simulation for neutral axis estimation in flexible electronics, warpage prediction in panel-level packaging, and stress distribution analysis in porous metamaterials. He also applies nanoindentation techniques to extract mechanical parameters and investigate energy dissipation behavior in thin films and porous metamaaterial material. He previously worked at TSMC APTS for two years, where he worked on mechanical simulation for advanced packaging and contributed to nanoindentation-based material characterization methodologies. During that time, he held over 2 patents related to TIM material and lid structure. He currently collaborates with ITRI, focusing on mechanical simulation for flexible electronics and panel-level packaging, particularly addressing die-first shifting and RDL mechanical deformation behaviors. He holds over 10 patents about flexible electronics and panel-level packaging.

Abstract:
To address increasing bandwidth demands and the limitations imposed by Moore’s law, advanced packaging strategies are employed, including Chiplet architectures, heterogeneous integration, and co-packaged optics, to enhance power efficiency and data transmission performance in high-performance computing, artificial intelligence (AI), and next-generation Ethernet systems. Glass substrates are selected for their favorable properties, including low dielectric loss, high thermal stability, and a coefficient of thermal expansion (CTE) closely matching the CTE of silicon material, minimizing thermomechanical mismatch at interfaces. Through-glass via (TGV) structures are utilized to enable vertical interconnections for DC and RF signal transmission, supporting high-density and low-loss routing essential for complex multi-chip modules. Moreover, panel-level glass packaging is adopted to satisfy enhancing demands for larger substrate sizes in advanced AI chip designs. On the other hand, TGV plays a critical role in ensuring reliable, high-aspect-ratio vertical interconnects across large form factors. However, during the manufacturing process, conventional measurement techniques are found to be inadequate for capturing changes in residual stress within the TGV regions due to the opacity and complexity of multilayer assemblies. This limitation underscores the need for advanced, integrated measurement and modeling approaches capable of resolving three-dimensional stress fields with sufficient accuracy. Therefore, physical estimation of TGV structures is investigated in this study. Surface optical full-field measurements, including the PhotoStress method and digital image correlation (DIC), are used to capture detailed surface stress and strain distributions on TGV substrates. The PhotoStress method is applied to visualize principal stress differences through birefringent coatings under polarized light. DIC is employed to obtain high-resolution, full-field displacement and strain maps by tracking deformation of a finely applied random speckle pattern during thermal loading. Finite element analysis (FEA) is conducted to simulate internal and depth-direction stress distributions, with realistic TGV geometries, anisotropic material properties, and thermal cycling profiles carefully defined. Experimental optical data and FEA simulations are calibrated and integrated through a hybrid modeling approach. FEA is validated with optical measurement in surface distribution based on lower than 10% difference, enabling the back-calculation of stresses along the blind via sidewalls and in the depth direction. Through this hybrid integration, complex three-dimensional stress fields within TGV structures under thermal cycling are accurately reconstructed. Critical insights into stress concentration zones, failure-prone interfaces, and thermal-mechanical reliability issues are thereby provided to inform advanced packaging design optimization and enhance the predictive accuracy of reliability assessments for high-performance electronic applications. A test vehicle is selected, consisting of a copper-filled TGV substrate measuring 50 mm in length by 50 mm in width, with vias of 30 micrometers in diameter. The aspect ratio is defined as 10 for the TGV sample to represent typical high-aspect-ratio via configurations encountered in advanced glass substrate applications. The TGV sample is prepared with appropriate surface treatments and metallization to ensure adhesion and electrical continuity. Finally, this hybrid modeling approach is considered effective for mitigating the timeline required for the design of large-scale TGV substrates, enabling more efficient evaluation of thermomechanical reliability and interconnect performance.