Sessions Index

Bio:

Current Position:  Global Sr. Packaging Account TD Head

Organization:  Applied Materials

 

Job Experience:

Over 35 years of job experience in semiconductor industry, especially focusing on advanced packaging technologies.

Packaging Research Development Center, SPIL (in ASX)

Product Development, Quality, & Sales, bumping RD, Amkor Taiwan

Process & Quality, TI-Acer memory company

 

Award:

2018-2025, SEMICON Taiwan packaging industry contribution award

Invited as SEMICON Taiwan packaging committee co-chairman

Invited as IMPACT packaging committee executive co-chairman

Invited as TILA (Taiwan Intelligent Leader Association) chairman

Invited as invited / keynote speakers in over 50 packaging symposium in the world.

Abstract:

 

Bio:

Vincent has accumulated over 35 years of experience in Technology Development, Operations, Business, Sales, and Marketing, demonstrating success at renowned companies such as IBM, Amkor, ASE, TSMC, and GLOBALFOUNDRIES. He joined Applied Materials in 2016.
Currently leading Technology Pathfinding, Corporate, and Business Development within the Advanced Packaging and ICAPS division at Applied Materials, Vincent is responsible for establishing strategic alliances and partnerships essential to advancing technology for future product solutions. He oversees all aspects of critical technology transitions pertaining to Heterogeneous Integration, next-generation silicon integration, and volumetric scaling associated with advanced packaging technologies, including 3DIC Heterogeneous Integration.
In addition, Vincent serves on the Advisory Board of BESI, a company that specializes in advanced packaging equipment, and holds the position of Vice-Chairman at iNEMI, a consortium dedicated to the global electronics manufacturing supply chain.
Vincent holds a degree in Pure and Applied Sciences from Champlain Regional College and a Bachelor of Engineering degree from Concordia University. He is the author and co-author of over 40 patents in the field of advanced semiconductor packaging and heterogeneous integration.

Abstract:

 

Bio:

Deepak Kulkarni is a Senior Fellow at Advanced Micro Devices (AMD), where he leads the Instinct and Optics Technology Development team. In this role, he develops heterogeneous architectures for AMD’s AI accelerator products and oversees Photonics technology development.
With twenty years in technology development, Deepak has led the development of several innovative technologies such as panel-level fan-out, Embedded Multi-die Interconnect Bridge (EMIB), Elevated Fan-Out Bridge (EFB), and 3.5D packaging solutions. Recognized with top awards at both AMD and Intel, and a frequent voice on high-level industry panels, Deepak brings both technical depth and strategic vision to advancing heterogeneous integration.
Deepak Kulkarni's technical interests cover Co-packaged Optics, Panel-level packaging, and design- technology co-optimization. He holds forty patents and has published over twenty papers. He earned his PhD in Mechanical Engineering with a minor in Computational Science from the University of Illinois at Urbana-Champaign.

Abstract:

The ever-growing demand for AI computing power is propelling rapid advancements in packaging technology. AMD is at the forefront of these innovations, leading the way in 2.5D, 3D, and 3.5D packaging technologies. Beyond these advancements, we are pioneering the transformation of packages into complete systems by integrating components such as co-packaged optics.

This presentation will delve into the limitations of wafer-scale and explore the emerging trend of panel-scale packages that integrate entire systems. The discussion will emphasize the intersection of architecture, optics, and thermal design, illustrating how these elements converge to meet the increasing demands of high-performance, energy-efficient applications.

 

Bio:

Yu-Hua Chen received the Ph.D. degree in Chemistry from National Taiwan University in 2001. Since 2001, he has been with the Industrial Technology Research Institute (ITRI),Electronics and Optoelectronic Research Laboratories (EOL), as a member of the Packaging Technology Division in 2001~2012. Since 2012, he joined the Unimicron to develop the next generation substrate technology.

Abstract:

As the demand for energy-efficient, high-performance computing continues to accelerate, heterogeneous integration has emerged as a key enabler for next-generation electronic systems. Advanced substrates play a crital role in this evolution, serving as the foundational platform for integrating diverse chiplets—including logic, memory, RF, and photonics—into a single package. This presentation explores the latest innovations in substrate technologies. We will discuss the development of advanced substrate materials, and the adoption of advanced build-up layers and redistribution layers (RDLs). Emphasis will be placed on how these substrates facilitate chiplet-based architectures and enable system-level performance improvements in AI, HPC, and edge computing applications. By advancing substrate capabilities, we unlock new possibilities for heterogeneous integration, driving innovation across the semiconductor ecosystem.

 

Bio:

Naresh Kumar Asokan is Global product Manager in Panel Packaging and Solutions Group.
Naresh has more than 17 years of experience in semiconductor equipment industry and joined Applied Materials in 2020 following the acquisition of Tango Systems, where he led Engineering and product Marketing for PVD products. He has over 10 years of experience working on capital equipment development for substrate technologies.
He holds a master’s degree in Busies Management and B. Tech in Mechanical engineering from Anna University.

Abstract:

Introduction to Topaz PVD / Etch tools for panel level processing

 

Bio:

Co-invented digital lithography, acquired by Applied Materials in 2014. Invented Scattering Bars Optical Proximity Correction acquired by ASML in 1999, widely adopted for DUV & immersion lithography. He holds 100+ patents, dual MS from RIT, NY, USA.

Abstract:

International Data Corporation (IDC) projects the AI Supercycle will accelerate semiconductor revenue to $1 trillion before 2029—years earlier than expected. As monolithic transistor scaling approaches physical limits with rising costs, performance scaling now depends on heterogeneous integration to meet HPC demands. Emerging 2.5D–3.5D architectures impose unprecedented lithography challenges: imaging fields >6X reticle size (>100 mm × 100 mm) without stitching errors, 2 µm line/space RDL features with tight CD uniformity, and per-unit overlay correction for >10 µm placement shifts on warped substrates often exceeding 12 mm. Conventional steppers and LDI tools cannot meet these requirements simultaneously. Applied Materials’ Digital Lithography Technology (DLT) has already demonstrated 2 µm RDL patterning on production panels, achieving <10% CDU across 515 mm × 510 mm glass or CCL substrates. This talk previews the next-generation DLT platform, which expands design and process windows while improving overlay robustness. Key innovations include high-speed scanning alignment combined with Digital Dynamic Connection™ (DDC) to achieve design-intent overlay on shifted unit packages, improving yield. DDC enables per-unit wiring alignment across multiple masking layers for better design-rule compliance with minimal throughput impact.

 

Bio:

Bernhard Mueller has been active in the SEMI industry since 1995, beginning his career as a SEMI metrology application engineer. Since 2011, he has led application development at Applied Materials YTG team, focusing on the implementation of electron-beam based measurement and inspection technologies in the display industry and SEMI heterogeneous integration processes.

Abstract:

Test and inspection in advanced packaging face challenges due to shrinking feature sizes, complex 3D structures, and heterogeneous integration, which limit the effectiveness of traditional optical methods. Electron beam (e-beam) technology overcomes these limitations by offering nanometer-scale resolution and material-sensitive contrast. It enables precise defect detection, overlay measurement, and CD metrology even in high-aspect-ratio and buried structures. E-beam systems also support non-contact inline inspection with high throughput. This makes them essential for ensuring yield and reliability in cutting-edge semiconductor packaging.