Sessions Index

Bio:

Cooper Li is a Signal Integrity Engineer at Advanced Micro Devices (AMD), specializing in high-speed digital design and signal integrity analysis for next-generation data center platforms. With over eight years of industry experience, he has led and contributed to numerous high-performance system designs, including data center servers and Ethernet switches. Cooper holds a Master’s degree in Electronics and Communications Engineering from.

Abstract:

With the rapid advancement of artificial intelligence (AI) and machine learning (ML) applications, PCI Express (PCIe) technology has emerged as critical infrastructure due to its superior bandwidth, low latency, and reliable high-performance communication channels capable of managing intensive parallel computing demands. As industry requirements continue to escalate, accelerating the adoption of next-generation PCIe specifications has become imperative; however, numerous signal integrity (SI) challenges must first be addressed to achieve these higher performance targets reliably. This paper investigates key SI issues associated with high-speed signal breakout designs from dense CPU or GPU pin fields, emphasizing the significant influence of breakout trace impedance, spacing constraints, and crosstalk noise in high-layer-count printed circuit board (PCB) stackups. Through comprehensive simulation-based performance analyses, we compare current-generation PCIe Copper Link channel solutions against anticipated next-generation demands, with particular emphasis on the implications of Pulse Amplitude Modulation with four levels (PAM4) signaling and the substantially increased operational frequencies introduced in PCIe 6.0 and 7.0 standards. Our findings demonstrate that meticulous optimization of breakout impedance, careful management of signal routing geometry, and strategic layer assignments can effectively mitigate noise coupling, reflections, resonance effects, and other signal degradation mechanisms. These optimizations lead to significant improvements in channel performance, including enhanced signal-to-noise ratio (SNR) and overall signal quality. The methodologies and design guidelines presented in this paper provide essential insights and practical recommendations for achieving robust, high-quality signal integrity in advanced PCIe interconnect implementations, facilitating the successful deployment of PCIe 7.0 at speeds up to 128 Gbps per lane in future data center and AI computing platforms.

 

Bio:

Katie Tsai is a senior Signal Integrity engineer with over ten years of experience in high-speed signal design, simulation, and validation across both system-level and 3DIC domains. She has assisted customers in establishing 3DIC analysis flows involving advanced packaging technologies such as CoWoS and InFO. She currently works at AMD as a Signal Integrity Application Engineer, responsible for simulation optimization of high-speed/DDR interface platforms and supporting customer-side R&D and debugging.

Abstract:

"As DDR interfaces advance toward higher data rates, CPU breakout (BO) design becomes increasingly critical. Among the available layout techniques, tabbed routing is widely used in breakout routing. However, whether tabbed routing is truly necessary for maintaining signal integrity remains an open question. Existing design flows often rely solely on simulation, lacking validation against real-world implementation.
This paper presents a structured validation methodology that evaluates the necessity of tabbed routing through both simulation and measurement. S-parameters are extracted from test boards with and without tabbed routing, and eye diagram analysis is conducted using the S2eye tool. We compare simulation-based and measurement-based S2eye results to assess the correlation and highlight the practical implications of layout choices.
The evaluation includes both simulation and validation results for key performance metrics such as Insertion Loss (IL), Return Loss (RL), Far-End Crosstalk (FEXT), and Time Domain Reflectometry (TDR), along with eye diagram analysis using the S2eye methodology. These metrics provide a comprehensive view of how tabbed routing influences signal quality across both frequency and time domains.
This analysis highlights how the presence or absence of tabbed routing affects key signal integrity metrics, providing valuable insights into its actual benefits and limitations in practical designs."

 

Bio:

Jun Wei is a Signal Integrity Engineer at SHPE AMD, specializing in signal integrity with a focus on high-speed input/output (HSIO) interfaces, particularly PCIe Gen5 and Gen6 standards. In this role, he is dedicated to ensuring the performance and reliability of advanced communication interfaces, optimizing designs to mitigate signal degradation and enhance overall system functionality.

Abstract:

"With the growing demand for higher data rates in digital communications, the shift from Non-Return to Zero (NRZ) signaling to Pulse Amplitude Modulation (PAM4) signaling is essential for maximizing bandwidth efficiency. PAM4 effectively doubles the data rate by using four signal levels, enabling greater data transmission within the same bandwidth compared to NRZ. However, PAM4 signal amplitude is reduced to one-third of NRZ, resulting in approximately 9.6 dB degradation. This amplitude reduction makes PAM4 signaling is more susceptible to noises such as power noise and crosstalk that can adversely affect signal integrity at the receiver [1].
This paper investigates crosstalk effects—specifically Far-End Crosstalk (FEXT) and Near-End Crosstalk (NEXT) - in high-density PAM4 Serializer/Deserializer (SerDes) implementations on printed circuit board (PCB) pin-field breakouts. Our analysis focuses on crosstalk interactions between NRZ aggressors and PAM4 victims while considering trace-to-via coupling (T-V coupling). This coupling occurs when long shallow-layer NRZ signals cross over SerDes PTH vias, presenting design challenges in densely packed PCB layouts (Fig. 1).
Through theoretical modeling, we quantified degradations in signal quality due to crosstalk in both NRZ and PAM4 systems. Our findings show that the signal-to-noise ratio (SNR) can be significantly compromised, resulting in an increase of bit-error rates (BER) in high-density configurations [2]. We investigated FEXT and NEXT mechanisms to understand how the characteristics of PAM4 may worsen these issues further.
The simulation setup involves extracting six pairs of channels using a 3D EM simulator (Ansys Electronics Desktop). One link operates in the shallow layer with NRZ modulation at 16 Gbps (PCIe Gen 4), while five PAM4 links in deeper layers operate at 64 Gbps (PCIe Gen 6). The end-to-end channel simulations were performed using Keysight ADS software, processing 1 million bits with optimized presets to ensure the best performance (Fig. 2). Our results indicate a 25% performance improvement when the NRZ channel is disabled, highlighting its detrimental impact on overall margin due the crosstalk impact (Fig. 3).
To address crosstalk challenges, we propose optimization strategies, including adjusting PCB routing to minimize T-V coupling. However, density requirements and fixed pin assignments limit this feasibility. Thus, changing the routing pattern from Model #2 to Model #1 achieves approximately 70% reduction in T-V coupling (Fig. 4A and B). Our comparative analysis reveals a maximum delta of 9 dB between routing models, underscoring the effectiveness of these optimization strategies (Fig. 5 and Fig. 6).
Additionally, we advocate for asymmetric pin field routing (Fig. 7) and propose CAD tools to automate the layout process, allowing adjustments to trace-to-via distances, enhancing layout efficiency while considering manufacturing capabilities.
In summary, this study provides valuable insights into the crosstalk challenges in high-density PAM4 SerDes PCB designs, emphasizing performance implications and offering critical mitigation strategies for optimizing high-speed data transmission in next-generation communication systems."

 

Bio:

Aik Hong is a highly skilled Signal Integrity Engineer with 6 years of experience in LSIO and DDR memory interfaces which focus on critical areas such as connector modeling, 3D modeling methodology, comprehensive channel analysis, and PCB channel optimization. He is passionate about solving complex SI challenges and contributing to DDR5 and DDR6 solutions.

Abstract:

"Achieving high data rates on DDR memory in modern electronics hinges on robust signal integrity, particularly in systems utilizing dual-inline memory module (DIMM) connectors. These connectors play a pivotal role in maintaining signal integrity, especially in DDR5 2 DIMM-per-Channel (2DPC) systems, which are designed to enhance memory capacity. The branch topology inherent in 2DPC systems introduces inter-symbol interference (ISI), with DIMM connectors contributing to parasitic effects such as inductance and capacitance. These effects can lead to signal reflections, material losses, and crosstalk, ultimately causing bit errors, data corruption, and potential system failures. Therefore, accurate connector modeling is essential for designers to simulate and optimize the signal integrity performance of 2DPC systems.
Incorporating a DIMM connector into a design necessitates a precise simulation model to achieve accurate end-to-end system performance. This is particularly critical for high-bandwidth applications like DDR5 MRDIMM 2DPC 1of2 11.2G enablement. Key considerations include configuring the return path, setting up excitation ports, and accurately representing the mating PCB stack-up. The challenge lies in the seamless integration of the connector and PCB models, as variations in fringe fields make it difficult to delineate where the connector ends and the board begins. To accurately model signal reflection, return loss (RL), insertion loss (IL), and crosstalk, a uniform transmission line is necessary. The board-level fan-out, pad stack, and return pin connections significantly influence the overall performance of the DIMM connector, often as much as the connector itself. Thus, having precise models to simulate the DIMM connector alongside the PCB DIMM pad/vias models is crucial.
The proposed methodology has the potential to enhance system-level signal integrity margins, through accurate modeling and reduce pessimism in the model. Potentially improving performance by more than one speed bin. This is a key enabler for achieving 11.2G in MRDIMM 2DPC 1of2 topologies and 8G in RDIMM 2DPC 1of2 configurations. This paper focuses on the connector modeling methodology, examining the impact of simulated eye margins on RDIMM and MRDIMM 2DPC systems with and without proper DIMM connector modeling. Additionally, it correlates 3D models against actual lab measurement data in the frequency domain.
In conclusion, the paper outlines future steps to achieve robust modeling in the DIMM region, including the integration of first and second DIMMs with DIMM-to-DIMM routing. Active lab correlation will also be a part of future endeavors, ensuring that the models align with real-world performance. This comprehensive approach aims to enhance the accuracy and reliability of DIMM connector modeling, ultimately supporting the development of high-performance electronic systems."