Sessions Index

Bio:

Dr Devan Iyer joined GEA in March 2024 as a Chief Strategist for Advanced Electronic Packaging . Dr Iyer has more than 35 years of experience in component and systems design & packaging technology , assembly & test manufacturing and Business unit leadership . He has served as Senior Vice President of Business units at Amkor Technology and Corporate Vice President at Texas Instruments. He has also worked for Infineon Technologies & General Electric.
As R&D Director, he also led industry consortia in advanced pack aging at Institute of Microelectronics in Singapore and at the Packaging Research Center at Georgia Tech in electronic packaging designs and technology. Dr Iyer has more than 250 technical publications and 35 patents to his credit.

Abstract:

 

Bio:

Dr. Raja Swaminathan is the Corporate Vice President of Heterogeneous Integration Technologies at AMD, spearheading the development of AMD's advanced packaging and heterogeneous integration roadmap. He also leads the Optics technology development at AMD, driving innovation in high-speed optical interconnects and photonics integration.

With a distinguished career spanning roles at Intel, Apple, and now AMD, Dr. Swaminathan's expertise in design-technology co-optimization and dedication to optimizing power, performance, area, and cost (PPAC) have led to significant technological advancements such as EMIB, Apple's Mx packages, 3D V-Cache, and 3.5D architectures for AI accelerators.

Dr. Swaminathan holds a PhD from Carnegie Mellon University and an undergraduate degree from IIT Madras. With over 100 patents and more than 40 published papers to his name, he was recently recognized as an IEEE Fellow and serves as a technical advisor to multiple startups. His unwavering commitment to heterogeneous integration continues to drive the boundaries of silicon technology. He also shares his insights on life and leadership, drawing lessons from the semiconductor industry, on his LinkedIn profile.

Abstract:

Chiplet architectures are becoming foundational to the continued economic and power-efficient scaling of AI hardware and edge computing. As Moore’s Law slows, the convergence of system integration and advanced packaging has emerged as a critical enabler at the intersection of technology and architecture. This keynote will explore how heterogeneous integration—spanning 2.5D and 3D hybrid bonded architectures—is driving AMD’s industry-leading roadmap to optimize power, performance, area, and cost (PPAC). Beyond packaging, the talk will highlight the broader system-level innovations required to integrate diverse chiplets into cohesive, high-performance modules. Topics will include chiplets for AI, system integration challenges, interconnect strategies, and solutions for large-scale chiplet-based systems.

 

Bio:

Dr. CP Hung, IEEE Fellow, is currently Vice President of Corporate R&D, at ASE Group, responsible for next-generation product development featuring integrated technologies, as well as a broad range of advanced chip, package, test, and system integrating solutions for multiple ASE and USI Sites.

He holds 354 patents encompassing IC packaging structure, process, substrate and characterization technology. He has published over 142 conference and journal papers.

Abstract:

By exploring the data center and AI landscape, heterogeneous integration (HI) through advanced packages is propelling pivotal complex integration in various structures, with optimizing stress, thermal and electrical limits for dynamic challenges on compute bandwidth, energy efficiency and smaller form factors, thus, highlighting required collective collaboration.

 

Bio:

Dennis ( Tiang-Ho) born in Taiwan , has been working in PCB industry from 1987. Dennis has been with Kinsus since 2005. He spends most of his time in the R&D department and is currently a Senior Director at the Advanced Product R&D team. Dennis has also authored more than 15 books on PCB and publishes regularly on PCB magazines.

Abstract:

The talk briefly describes some of the advanced packaging technology platforms like CoWoS with focus on high performance compute for AI applications. The talks covers salient aspects of large substrates with needs and challenges centered around power delivery, low loss , low warpage and high volume manufacturing. Material selection and their properties will also be discussed during this talk. Some of the innovative materials & processes to meet the demands and challenges will also be highlighted.

 

Bio:

Ander leads an international team dedicated to advancing PCBA processes, fostering continuous innovation and improving manufacturing efficiency. He oversees comprehensive Design for Excellence (DfX) evaluations, ensuring new product designs meet the highest standards of manufacturability, quality, and reliability. Ander manages in-depth process & material failure analyses to identify and address potential product issues, driving improved long-term performance and reliability. He also directs efforts in developing Co-package technology, achieving significant advancements in assembly integration and optical testing capabilities.

Abstract:

With the rapid development of AI computational capabilities, the increasing size and quantity of ASIC and GPU chips have posed significant challenges to SMT packaging processes. This has escalated the complexity in chip design and process integration, introducing substantial challenges to the overall packaging workflow.

Current issues in the production and application of large Ball Grid Arrays primarily revolve around the following aspects: a) Soldering Defects - The increased risk of warpage-induced soldering failures in Large Form Factor components, such as Head-in-Pillow (HIP) effects, solder joint opens, and solder bridging b) Radiation Dosage: HBM and other radiation-sensitive components impose restrictions on X-ray inspection time and frequency. 2.5D or 3D High Performance Computing (HPC) components and product designs require high-intensity X-ray sources that can penetrate through their layers to inspect solder joints and TIM. c) Thermal Conductivity: Warpage effects during High Power Component assembly introduce a gap in the interface between the component and the cold plate, decreasing the effectiveness of metal TIM2 (compressible TIMs).

These challenges highlight the need to develop innovative strategies in advanced packaging technologies and inspection methodologies, as well as refine process controls to mitigate issues related to warpage, radiation sensitivity, and thermal efficiency in next-generation AI-enabled devices. To address these challenges, this study focuses on improvements from three perspectives: Material Selection-  By using low-CTE substrates along with reinforced PCB strength, symmetrical PCB designs, and balanced copper distribution, the goal is to mitigate the impact of warpage. SMT Process Optimization- Techniques such as specific reflow fixtures, corner supports for Large Form Factor components, low-temperature solder paste, and tailored reflow profiles effectively reduce thermal deformation during soldering. Inspection and Analysis Techniques-  Thermal deformation measurement and warpage analysis are employed to evaluate dynamic deformation trends of both PCBs and components across reflow temperature profiles. Additionally, CT-X-ray techniques enable multi-layer depth analysis of solder joints, providing comprehensive 3D insights into defects like solder joint opens and HIP issues.